1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SMP related functions 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Denis Joseph Barrow, 7 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 8 * 9 * based on other smp stuff by 10 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> 11 * (c) 1998 Ingo Molnar 12 * 13 * The code outside of smp.c uses logical cpu numbers, only smp.c does 14 * the translation of logical to physical cpu ids. All new code that 15 * operates on physical cpu numbers needs to go into smp.c. 16 */ 17 18 #define KMSG_COMPONENT "cpu" 19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 20 21 #include <linux/cpufeature.h> 22 #include <linux/workqueue.h> 23 #include <linux/memblock.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/mm.h> 27 #include <linux/err.h> 28 #include <linux/spinlock.h> 29 #include <linux/kernel_stat.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/irqflags.h> 33 #include <linux/irq_work.h> 34 #include <linux/cpu.h> 35 #include <linux/slab.h> 36 #include <linux/sched/hotplug.h> 37 #include <linux/sched/task_stack.h> 38 #include <linux/crash_dump.h> 39 #include <linux/kprobes.h> 40 #include <asm/access-regs.h> 41 #include <asm/asm-offsets.h> 42 #include <asm/machine.h> 43 #include <asm/ctlreg.h> 44 #include <asm/pfault.h> 45 #include <asm/diag.h> 46 #include <asm/facility.h> 47 #include <asm/fpu.h> 48 #include <asm/ipl.h> 49 #include <asm/setup.h> 50 #include <asm/irq.h> 51 #include <asm/tlbflush.h> 52 #include <asm/vtimer.h> 53 #include <asm/abs_lowcore.h> 54 #include <asm/sclp.h> 55 #include <asm/debug.h> 56 #include <asm/os_info.h> 57 #include <asm/sigp.h> 58 #include <asm/idle.h> 59 #include <asm/nmi.h> 60 #include <asm/stacktrace.h> 61 #include <asm/topology.h> 62 #include <asm/vdso.h> 63 #include <asm/maccess.h> 64 #include "entry.h" 65 66 enum { 67 ec_schedule = 0, 68 ec_call_function_single, 69 ec_stop_cpu, 70 ec_mcck_pending, 71 ec_irq_work, 72 }; 73 74 enum { 75 CPU_STATE_STANDBY, 76 CPU_STATE_CONFIGURED, 77 }; 78 79 static u8 boot_core_type; 80 DEFINE_PER_CPU(struct pcpu, pcpu_devices); 81 /* 82 * Pointer to the pcpu area of the boot CPU. This is required when a restart 83 * interrupt is triggered on an offline CPU. For that case accessing percpu 84 * data with the common primitives does not work, since the percpu offset is 85 * stored in a non existent lowcore. 86 */ 87 static struct pcpu *ipl_pcpu; 88 89 unsigned int smp_cpu_mt_shift; 90 EXPORT_SYMBOL(smp_cpu_mt_shift); 91 92 unsigned int smp_cpu_mtid; 93 EXPORT_SYMBOL(smp_cpu_mtid); 94 95 #ifdef CONFIG_CRASH_DUMP 96 __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; 97 #endif 98 99 static unsigned int smp_max_threads __initdata = -1U; 100 cpumask_t cpu_setup_mask; 101 102 static int __init early_smt(char *s) 103 { 104 get_option(&s, &smp_max_threads); 105 return 0; 106 } 107 early_param("smt", early_smt); 108 109 /* 110 * The smp_cpu_state_mutex must be held when changing the state or polarization 111 * member of a pcpu data structure within the pcpu_devices array. 112 */ 113 DEFINE_MUTEX(smp_cpu_state_mutex); 114 115 /* 116 * Signal processor helper functions. 117 */ 118 static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) 119 { 120 int cc; 121 122 while (1) { 123 cc = __pcpu_sigp(addr, order, parm, NULL); 124 if (cc != SIGP_CC_BUSY) 125 return cc; 126 cpu_relax(); 127 } 128 } 129 130 static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) 131 { 132 int cc, retry; 133 134 for (retry = 0; ; retry++) { 135 cc = __pcpu_sigp(pcpu->address, order, parm, NULL); 136 if (cc != SIGP_CC_BUSY) 137 break; 138 if (retry >= 3) 139 udelay(10); 140 } 141 return cc; 142 } 143 144 static inline int pcpu_stopped(struct pcpu *pcpu) 145 { 146 u32 status; 147 148 if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 149 0, &status) != SIGP_CC_STATUS_STORED) 150 return 0; 151 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); 152 } 153 154 static inline int pcpu_running(struct pcpu *pcpu) 155 { 156 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, 157 0, NULL) != SIGP_CC_STATUS_STORED) 158 return 1; 159 /* Status stored condition code is equivalent to cpu not running. */ 160 return 0; 161 } 162 163 /* 164 * Find struct pcpu by cpu address. 165 */ 166 static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) 167 { 168 int cpu; 169 170 for_each_cpu(cpu, mask) 171 if (per_cpu(pcpu_devices, cpu).address == address) 172 return &per_cpu(pcpu_devices, cpu); 173 return NULL; 174 } 175 176 static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) 177 { 178 int order; 179 180 if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) 181 return; 182 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; 183 pcpu->ec_clk = get_tod_clock_fast(); 184 pcpu_sigp_retry(pcpu, order, 0); 185 } 186 187 static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) 188 { 189 unsigned long async_stack, nodat_stack, mcck_stack; 190 struct lowcore *lc; 191 192 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 193 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 194 async_stack = stack_alloc(); 195 mcck_stack = stack_alloc(); 196 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 197 goto out; 198 memcpy(lc, get_lowcore(), 512); 199 memset((char *) lc + 512, 0, sizeof(*lc) - 512); 200 lc->async_stack = async_stack + STACK_INIT_OFFSET; 201 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET; 202 lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET; 203 lc->cpu_nr = cpu; 204 lc->spinlock_lockval = arch_spin_lockval(cpu); 205 lc->spinlock_index = 0; 206 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); 207 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); 208 lc->preempt_count = PREEMPT_DISABLED; 209 if (nmi_alloc_mcesa(&lc->mcesad)) 210 goto out; 211 if (abs_lowcore_map(cpu, lc, true)) 212 goto out_mcesa; 213 lowcore_ptr[cpu] = lc; 214 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, __pa(lc)); 215 return 0; 216 217 out_mcesa: 218 nmi_free_mcesa(&lc->mcesad); 219 out: 220 stack_free(mcck_stack); 221 stack_free(async_stack); 222 free_pages(nodat_stack, THREAD_SIZE_ORDER); 223 free_pages((unsigned long) lc, LC_ORDER); 224 return -ENOMEM; 225 } 226 227 static void pcpu_free_lowcore(struct pcpu *pcpu, int cpu) 228 { 229 unsigned long async_stack, nodat_stack, mcck_stack; 230 struct lowcore *lc; 231 232 lc = lowcore_ptr[cpu]; 233 nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET; 234 async_stack = lc->async_stack - STACK_INIT_OFFSET; 235 mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; 236 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); 237 lowcore_ptr[cpu] = NULL; 238 abs_lowcore_unmap(cpu); 239 nmi_free_mcesa(&lc->mcesad); 240 stack_free(async_stack); 241 stack_free(mcck_stack); 242 free_pages(nodat_stack, THREAD_SIZE_ORDER); 243 free_pages((unsigned long) lc, LC_ORDER); 244 } 245 246 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) 247 { 248 struct lowcore *lc, *abs_lc; 249 250 lc = lowcore_ptr[cpu]; 251 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); 252 cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); 253 lc->cpu_nr = cpu; 254 lc->pcpu = (unsigned long)pcpu; 255 lc->restart_flags = RESTART_FLAG_CTLREGS; 256 lc->spinlock_lockval = arch_spin_lockval(cpu); 257 lc->spinlock_index = 0; 258 lc->percpu_offset = __per_cpu_offset[cpu]; 259 lc->kernel_asce = get_lowcore()->kernel_asce; 260 lc->user_asce = s390_invalid_asce; 261 lc->user_timer = lc->system_timer = 262 lc->steal_timer = lc->avg_steal_timer = 0; 263 abs_lc = get_abs_lowcore(); 264 memcpy(lc->cregs_save_area, abs_lc->cregs_save_area, sizeof(lc->cregs_save_area)); 265 put_abs_lowcore(abs_lc); 266 lc->cregs_save_area[1] = lc->user_asce; 267 lc->cregs_save_area[7] = lc->user_asce; 268 save_access_regs((unsigned int *) lc->access_regs_save_area); 269 arch_spin_lock_setup(cpu); 270 } 271 272 static void pcpu_attach_task(int cpu, struct task_struct *tsk) 273 { 274 struct lowcore *lc; 275 276 lc = lowcore_ptr[cpu]; 277 lc->kernel_stack = (unsigned long)task_stack_page(tsk) + STACK_INIT_OFFSET; 278 lc->current_task = (unsigned long)tsk; 279 lc->lpp = LPP_MAGIC; 280 lc->current_pid = tsk->pid; 281 lc->user_timer = tsk->thread.user_timer; 282 lc->guest_timer = tsk->thread.guest_timer; 283 lc->system_timer = tsk->thread.system_timer; 284 lc->hardirq_timer = tsk->thread.hardirq_timer; 285 lc->softirq_timer = tsk->thread.softirq_timer; 286 lc->steal_timer = 0; 287 } 288 289 static void pcpu_start_fn(int cpu, void (*func)(void *), void *data) 290 { 291 struct lowcore *lc; 292 293 lc = lowcore_ptr[cpu]; 294 lc->restart_stack = lc->kernel_stack; 295 lc->restart_fn = (unsigned long) func; 296 lc->restart_data = (unsigned long) data; 297 lc->restart_source = -1U; 298 pcpu_sigp_retry(per_cpu_ptr(&pcpu_devices, cpu), SIGP_RESTART, 0); 299 } 300 301 typedef void (pcpu_delegate_fn)(void *); 302 303 /* 304 * Call function via PSW restart on pcpu and stop the current cpu. 305 */ 306 static void __pcpu_delegate(pcpu_delegate_fn *func, void *data) 307 { 308 func(data); /* should not return */ 309 } 310 311 static void pcpu_delegate(struct pcpu *pcpu, int cpu, 312 pcpu_delegate_fn *func, 313 void *data, unsigned long stack) 314 { 315 struct lowcore *lc, *abs_lc; 316 unsigned int source_cpu; 317 318 lc = lowcore_ptr[cpu]; 319 source_cpu = stap(); 320 321 if (pcpu->address == source_cpu) { 322 call_on_stack(2, stack, void, __pcpu_delegate, 323 pcpu_delegate_fn *, func, void *, data); 324 } 325 /* Stop target cpu (if func returns this stops the current cpu). */ 326 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 327 pcpu_sigp_retry(pcpu, SIGP_CPU_RESET, 0); 328 /* Restart func on the target cpu and stop the current cpu. */ 329 if (lc) { 330 lc->restart_stack = stack; 331 lc->restart_fn = (unsigned long)func; 332 lc->restart_data = (unsigned long)data; 333 lc->restart_source = source_cpu; 334 } else { 335 abs_lc = get_abs_lowcore(); 336 abs_lc->restart_stack = stack; 337 abs_lc->restart_fn = (unsigned long)func; 338 abs_lc->restart_data = (unsigned long)data; 339 abs_lc->restart_source = source_cpu; 340 put_abs_lowcore(abs_lc); 341 } 342 asm volatile( 343 "0: sigp 0,%0,%2 # sigp restart to target cpu\n" 344 " brc 2,0b # busy, try again\n" 345 "1: sigp 0,%1,%3 # sigp stop to current cpu\n" 346 " brc 2,1b # busy, try again\n" 347 : : "d" (pcpu->address), "d" (source_cpu), 348 "K" (SIGP_RESTART), "K" (SIGP_STOP) 349 : "0", "1", "cc"); 350 for (;;) ; 351 } 352 353 /* 354 * Enable additional logical cpus for multi-threading. 355 */ 356 static int pcpu_set_smt(unsigned int mtid) 357 { 358 int cc; 359 360 if (smp_cpu_mtid == mtid) 361 return 0; 362 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); 363 if (cc == 0) { 364 smp_cpu_mtid = mtid; 365 smp_cpu_mt_shift = 0; 366 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) 367 smp_cpu_mt_shift++; 368 per_cpu(pcpu_devices, 0).address = stap(); 369 } 370 return cc; 371 } 372 373 /* 374 * Call function on the ipl CPU. 375 */ 376 void smp_call_ipl_cpu(void (*func)(void *), void *data) 377 { 378 struct lowcore *lc = lowcore_ptr[0]; 379 380 if (ipl_pcpu->address == stap()) 381 lc = get_lowcore(); 382 383 pcpu_delegate(ipl_pcpu, 0, func, data, lc->nodat_stack); 384 } 385 386 int smp_find_processor_id(u16 address) 387 { 388 int cpu; 389 390 for_each_present_cpu(cpu) 391 if (per_cpu(pcpu_devices, cpu).address == address) 392 return cpu; 393 return -1; 394 } 395 396 void schedule_mcck_handler(void) 397 { 398 pcpu_ec_call(this_cpu_ptr(&pcpu_devices), ec_mcck_pending); 399 } 400 401 bool notrace arch_vcpu_is_preempted(int cpu) 402 { 403 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) 404 return false; 405 if (pcpu_running(per_cpu_ptr(&pcpu_devices, cpu))) 406 return false; 407 return true; 408 } 409 EXPORT_SYMBOL(arch_vcpu_is_preempted); 410 411 void notrace smp_yield_cpu(int cpu) 412 { 413 if (!machine_has_diag9c()) 414 return; 415 diag_stat_inc_norecursion(DIAG_STAT_X09C); 416 asm volatile("diag %0,0,0x9c" 417 : : "d" (per_cpu(pcpu_devices, cpu).address)); 418 } 419 EXPORT_SYMBOL_GPL(smp_yield_cpu); 420 421 /* 422 * Send cpus emergency shutdown signal. This gives the cpus the 423 * opportunity to complete outstanding interrupts. 424 */ 425 void notrace smp_emergency_stop(void) 426 { 427 static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED; 428 static cpumask_t cpumask; 429 u64 end; 430 int cpu; 431 432 arch_spin_lock(&lock); 433 cpumask_copy(&cpumask, cpu_online_mask); 434 cpumask_clear_cpu(smp_processor_id(), &cpumask); 435 436 end = get_tod_clock() + (1000000UL << 12); 437 for_each_cpu(cpu, &cpumask) { 438 struct pcpu *pcpu = per_cpu_ptr(&pcpu_devices, cpu); 439 set_bit(ec_stop_cpu, &pcpu->ec_mask); 440 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, 441 0, NULL) == SIGP_CC_BUSY && 442 get_tod_clock() < end) 443 cpu_relax(); 444 } 445 while (get_tod_clock() < end) { 446 for_each_cpu(cpu, &cpumask) 447 if (pcpu_stopped(per_cpu_ptr(&pcpu_devices, cpu))) 448 cpumask_clear_cpu(cpu, &cpumask); 449 if (cpumask_empty(&cpumask)) 450 break; 451 cpu_relax(); 452 } 453 arch_spin_unlock(&lock); 454 } 455 NOKPROBE_SYMBOL(smp_emergency_stop); 456 457 /* 458 * Stop all cpus but the current one. 459 */ 460 void smp_send_stop(void) 461 { 462 struct pcpu *pcpu; 463 int cpu; 464 465 /* Disable all interrupts/machine checks */ 466 __load_psw_mask(PSW_KERNEL_BITS); 467 trace_hardirqs_off(); 468 469 debug_set_critical(); 470 471 if (oops_in_progress) 472 smp_emergency_stop(); 473 474 /* stop all processors */ 475 for_each_online_cpu(cpu) { 476 if (cpu == smp_processor_id()) 477 continue; 478 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 479 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 480 while (!pcpu_stopped(pcpu)) 481 cpu_relax(); 482 } 483 } 484 485 /* 486 * This is the main routine where commands issued by other 487 * cpus are handled. 488 */ 489 static void smp_handle_ext_call(void) 490 { 491 unsigned long bits; 492 493 /* handle bit signal external calls */ 494 bits = this_cpu_xchg(pcpu_devices.ec_mask, 0); 495 if (test_bit(ec_stop_cpu, &bits)) 496 smp_stop_cpu(); 497 if (test_bit(ec_schedule, &bits)) 498 scheduler_ipi(); 499 if (test_bit(ec_call_function_single, &bits)) 500 generic_smp_call_function_single_interrupt(); 501 if (test_bit(ec_mcck_pending, &bits)) 502 s390_handle_mcck(); 503 if (test_bit(ec_irq_work, &bits)) 504 irq_work_run(); 505 } 506 507 static void do_ext_call_interrupt(struct ext_code ext_code, 508 unsigned int param32, unsigned long param64) 509 { 510 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); 511 smp_handle_ext_call(); 512 } 513 514 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 515 { 516 int cpu; 517 518 for_each_cpu(cpu, mask) 519 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_call_function_single); 520 } 521 522 void arch_send_call_function_single_ipi(int cpu) 523 { 524 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_call_function_single); 525 } 526 527 /* 528 * this function sends a 'reschedule' IPI to another CPU. 529 * it goes straight through and wastes no time serializing 530 * anything. Worst case is that we lose a reschedule ... 531 */ 532 void arch_smp_send_reschedule(int cpu) 533 { 534 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_schedule); 535 } 536 537 #ifdef CONFIG_IRQ_WORK 538 void arch_irq_work_raise(void) 539 { 540 pcpu_ec_call(this_cpu_ptr(&pcpu_devices), ec_irq_work); 541 } 542 #endif 543 544 #ifdef CONFIG_CRASH_DUMP 545 546 int smp_store_status(int cpu) 547 { 548 struct lowcore *lc; 549 struct pcpu *pcpu; 550 unsigned long pa; 551 552 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 553 lc = lowcore_ptr[cpu]; 554 pa = __pa(&lc->floating_pt_save_area); 555 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, 556 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 557 return -EIO; 558 if (!cpu_has_vx() && !cpu_has_gs()) 559 return 0; 560 pa = lc->mcesad & MCESA_ORIGIN_MASK; 561 if (cpu_has_gs()) 562 pa |= lc->mcesad & MCESA_LC_MASK; 563 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, 564 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 565 return -EIO; 566 return 0; 567 } 568 569 /* 570 * Collect CPU state of the previous, crashed system. 571 * There are three cases: 572 * 1) standard zfcp/nvme dump 573 * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true 574 * The state for all CPUs except the boot CPU needs to be collected 575 * with sigp stop-and-store-status. The boot CPU state is located in 576 * the absolute lowcore of the memory stored in the HSA. The zcore code 577 * will copy the boot CPU state from the HSA. 578 * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory) 579 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true 580 * The state for all CPUs except the boot CPU needs to be collected 581 * with sigp stop-and-store-status. The firmware or the boot-loader 582 * stored the registers of the boot CPU in the absolute lowcore in the 583 * memory of the old system. 584 * 3) kdump or stand-alone kdump for DASD 585 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == false 586 * The state for all CPUs except the boot CPU needs to be collected 587 * with sigp stop-and-store-status. The kexec code or the boot-loader 588 * stored the registers of the boot CPU in the memory of the old system. 589 * 590 * Note that the legacy kdump mode where the old kernel stored the CPU states 591 * does no longer exist: setup_arch() explicitly deactivates the elfcorehdr= 592 * kernel parameter. The is_kdump_kernel() implementation on s390 is independent 593 * of the elfcorehdr= parameter. 594 */ 595 static bool dump_available(void) 596 { 597 return oldmem_data.start || is_ipl_type_dump(); 598 } 599 600 void __init smp_save_dump_ipl_cpu(void) 601 { 602 struct save_area *sa; 603 void *regs; 604 605 if (!dump_available()) 606 return; 607 sa = save_area_alloc(true); 608 regs = memblock_alloc_or_panic(512, 8); 609 copy_oldmem_kernel(regs, __LC_FPREGS_SAVE_AREA, 512); 610 save_area_add_regs(sa, regs); 611 memblock_free(regs, 512); 612 if (cpu_has_vx()) 613 save_area_add_vxrs(sa, boot_cpu_vector_save_area); 614 } 615 616 void __init smp_save_dump_secondary_cpus(void) 617 { 618 int addr, boot_cpu_addr, max_cpu_addr; 619 struct save_area *sa; 620 void *page; 621 622 if (!dump_available()) 623 return; 624 /* Allocate a page as dumping area for the store status sigps */ 625 page = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE); 626 if (!page) 627 panic("ERROR: Failed to allocate %lx bytes below %lx\n", 628 PAGE_SIZE, 1UL << 31); 629 630 /* Set multi-threading state to the previous system. */ 631 pcpu_set_smt(sclp.mtid_prev); 632 boot_cpu_addr = stap(); 633 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; 634 for (addr = 0; addr <= max_cpu_addr; addr++) { 635 if (addr == boot_cpu_addr) 636 continue; 637 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == 638 SIGP_CC_NOT_OPERATIONAL) 639 continue; 640 sa = save_area_alloc(false); 641 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, __pa(page)); 642 save_area_add_regs(sa, page); 643 if (cpu_has_vx()) { 644 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, __pa(page)); 645 save_area_add_vxrs(sa, page); 646 } 647 } 648 memblock_free(page, PAGE_SIZE); 649 diag_amode31_ops.diag308_reset(); 650 pcpu_set_smt(0); 651 } 652 #endif /* CONFIG_CRASH_DUMP */ 653 654 void smp_cpu_set_polarization(int cpu, int val) 655 { 656 per_cpu(pcpu_devices, cpu).polarization = val; 657 } 658 659 int smp_cpu_get_polarization(int cpu) 660 { 661 return per_cpu(pcpu_devices, cpu).polarization; 662 } 663 664 void smp_cpu_set_capacity(int cpu, unsigned long val) 665 { 666 per_cpu(pcpu_devices, cpu).capacity = val; 667 } 668 669 unsigned long smp_cpu_get_capacity(int cpu) 670 { 671 return per_cpu(pcpu_devices, cpu).capacity; 672 } 673 674 void smp_set_core_capacity(int cpu, unsigned long val) 675 { 676 int i; 677 678 cpu = smp_get_base_cpu(cpu); 679 for (i = cpu; (i <= cpu + smp_cpu_mtid) && (i < nr_cpu_ids); i++) 680 smp_cpu_set_capacity(i, val); 681 } 682 683 int smp_cpu_get_cpu_address(int cpu) 684 { 685 return per_cpu(pcpu_devices, cpu).address; 686 } 687 688 static void __ref smp_get_core_info(struct sclp_core_info *info, int early) 689 { 690 static int use_sigp_detection; 691 int address; 692 693 if (use_sigp_detection || sclp_get_core_info(info, early)) { 694 use_sigp_detection = 1; 695 for (address = 0; 696 address < (SCLP_MAX_CORES << smp_cpu_mt_shift); 697 address += (1U << smp_cpu_mt_shift)) { 698 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == 699 SIGP_CC_NOT_OPERATIONAL) 700 continue; 701 info->core[info->configured].core_id = 702 address >> smp_cpu_mt_shift; 703 info->configured++; 704 } 705 info->combined = info->configured; 706 } 707 } 708 709 static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, 710 bool configured, bool early) 711 { 712 struct pcpu *pcpu; 713 int cpu, nr, i; 714 u16 address; 715 716 nr = 0; 717 if (sclp.has_core_type && core->type != boot_core_type) 718 return nr; 719 cpu = cpumask_first(avail); 720 address = core->core_id << smp_cpu_mt_shift; 721 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) { 722 if (pcpu_find_address(cpu_present_mask, address + i)) 723 continue; 724 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 725 pcpu->address = address + i; 726 if (configured) 727 pcpu->state = CPU_STATE_CONFIGURED; 728 else 729 pcpu->state = CPU_STATE_STANDBY; 730 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); 731 smp_cpu_set_capacity(cpu, CPU_CAPACITY_HIGH); 732 set_cpu_present(cpu, true); 733 if (!early && arch_register_cpu(cpu)) 734 set_cpu_present(cpu, false); 735 else 736 nr++; 737 cpumask_clear_cpu(cpu, avail); 738 cpu = cpumask_next(cpu, avail); 739 } 740 return nr; 741 } 742 743 static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) 744 { 745 struct sclp_core_entry *core; 746 static cpumask_t avail; 747 bool configured; 748 u16 core_id; 749 int nr, i; 750 751 cpus_read_lock(); 752 mutex_lock(&smp_cpu_state_mutex); 753 nr = 0; 754 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); 755 /* 756 * Add IPL core first (which got logical CPU number 0) to make sure 757 * that all SMT threads get subsequent logical CPU numbers. 758 */ 759 if (early) { 760 core_id = per_cpu(pcpu_devices, 0).address >> smp_cpu_mt_shift; 761 for (i = 0; i < info->configured; i++) { 762 core = &info->core[i]; 763 if (core->core_id == core_id) { 764 nr += smp_add_core(core, &avail, true, early); 765 break; 766 } 767 } 768 } 769 for (i = 0; i < info->combined; i++) { 770 configured = i < info->configured; 771 nr += smp_add_core(&info->core[i], &avail, configured, early); 772 } 773 mutex_unlock(&smp_cpu_state_mutex); 774 cpus_read_unlock(); 775 return nr; 776 } 777 778 void __init smp_detect_cpus(void) 779 { 780 unsigned int cpu, mtid, c_cpus, s_cpus; 781 struct sclp_core_info *info; 782 u16 address; 783 784 /* Get CPU information */ 785 info = memblock_alloc_or_panic(sizeof(*info), 8); 786 smp_get_core_info(info, 1); 787 /* Find boot CPU type */ 788 if (sclp.has_core_type) { 789 address = stap(); 790 for (cpu = 0; cpu < info->combined; cpu++) 791 if (info->core[cpu].core_id == address) { 792 /* The boot cpu dictates the cpu type. */ 793 boot_core_type = info->core[cpu].type; 794 break; 795 } 796 if (cpu >= info->combined) 797 panic("Could not find boot CPU type"); 798 } 799 800 /* Set multi-threading state for the current system */ 801 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; 802 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; 803 pcpu_set_smt(mtid); 804 cpu_smt_set_num_threads(smp_cpu_mtid + 1, smp_cpu_mtid + 1); 805 806 /* Print number of CPUs */ 807 c_cpus = s_cpus = 0; 808 for (cpu = 0; cpu < info->combined; cpu++) { 809 if (sclp.has_core_type && 810 info->core[cpu].type != boot_core_type) 811 continue; 812 if (cpu < info->configured) 813 c_cpus += smp_cpu_mtid + 1; 814 else 815 s_cpus += smp_cpu_mtid + 1; 816 } 817 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); 818 memblock_free(info, sizeof(*info)); 819 } 820 821 /* 822 * Activate a secondary processor. 823 */ 824 static void smp_start_secondary(void *cpuvoid) 825 { 826 struct lowcore *lc = get_lowcore(); 827 int cpu = raw_smp_processor_id(); 828 829 lc->last_update_clock = get_tod_clock(); 830 lc->restart_stack = (unsigned long)restart_stack; 831 lc->restart_fn = (unsigned long)do_restart; 832 lc->restart_data = 0; 833 lc->restart_source = -1U; 834 lc->restart_flags = 0; 835 restore_access_regs(lc->access_regs_save_area); 836 cpu_init(); 837 rcutree_report_cpu_starting(cpu); 838 init_cpu_timer(); 839 vtime_init(); 840 vdso_getcpu_init(); 841 pfault_init(); 842 cpumask_set_cpu(cpu, &cpu_setup_mask); 843 update_cpu_masks(); 844 notify_cpu_starting(cpu); 845 if (topology_cpu_dedicated(cpu)) 846 set_cpu_flag(CIF_DEDICATED_CPU); 847 else 848 clear_cpu_flag(CIF_DEDICATED_CPU); 849 set_cpu_online(cpu, true); 850 inc_irq_stat(CPU_RST); 851 local_irq_enable(); 852 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 853 } 854 855 /* Upping and downing of CPUs */ 856 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 857 { 858 struct pcpu *pcpu = per_cpu_ptr(&pcpu_devices, cpu); 859 int rc; 860 861 if (pcpu->state != CPU_STATE_CONFIGURED) 862 return -EIO; 863 if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != 864 SIGP_CC_ORDER_CODE_ACCEPTED) 865 return -EIO; 866 867 rc = pcpu_alloc_lowcore(pcpu, cpu); 868 if (rc) 869 return rc; 870 /* 871 * Make sure global control register contents do not change 872 * until new CPU has initialized control registers. 873 */ 874 system_ctlreg_lock(); 875 pcpu_prepare_secondary(pcpu, cpu); 876 pcpu_attach_task(cpu, tidle); 877 pcpu_start_fn(cpu, smp_start_secondary, NULL); 878 /* Wait until cpu puts itself in the online & active maps */ 879 while (!cpu_online(cpu)) 880 cpu_relax(); 881 system_ctlreg_unlock(); 882 return 0; 883 } 884 885 static unsigned int setup_possible_cpus __initdata; 886 887 static int __init _setup_possible_cpus(char *s) 888 { 889 get_option(&s, &setup_possible_cpus); 890 return 0; 891 } 892 early_param("possible_cpus", _setup_possible_cpus); 893 894 int __cpu_disable(void) 895 { 896 struct ctlreg cregs[16]; 897 int cpu; 898 899 /* Handle possible pending IPIs */ 900 smp_handle_ext_call(); 901 cpu = smp_processor_id(); 902 set_cpu_online(cpu, false); 903 cpumask_clear_cpu(cpu, &cpu_setup_mask); 904 update_cpu_masks(); 905 /* Disable pseudo page faults on this cpu. */ 906 pfault_fini(); 907 /* Disable interrupt sources via control register. */ 908 __local_ctl_store(0, 15, cregs); 909 cregs[0].val &= ~0x0000ee70UL; /* disable all external interrupts */ 910 cregs[6].val &= ~0xff000000UL; /* disable all I/O interrupts */ 911 cregs[14].val &= ~0x1f000000UL; /* disable most machine checks */ 912 __local_ctl_load(0, 15, cregs); 913 clear_cpu_flag(CIF_NOHZ_DELAY); 914 return 0; 915 } 916 917 void __cpu_die(unsigned int cpu) 918 { 919 struct pcpu *pcpu; 920 921 /* Wait until target cpu is down */ 922 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 923 while (!pcpu_stopped(pcpu)) 924 cpu_relax(); 925 pcpu_free_lowcore(pcpu, cpu); 926 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); 927 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); 928 pcpu->flags = 0; 929 } 930 931 void __noreturn cpu_die(void) 932 { 933 idle_task_exit(); 934 pcpu_sigp_retry(this_cpu_ptr(&pcpu_devices), SIGP_STOP, 0); 935 for (;;) ; 936 } 937 938 void __init smp_fill_possible_mask(void) 939 { 940 unsigned int possible, sclp_max, cpu; 941 942 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; 943 sclp_max = min(smp_max_threads, sclp_max); 944 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; 945 possible = setup_possible_cpus ?: nr_cpu_ids; 946 possible = min(possible, sclp_max); 947 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) 948 set_cpu_possible(cpu, true); 949 } 950 951 void __init smp_prepare_cpus(unsigned int max_cpus) 952 { 953 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) 954 panic("Couldn't request external interrupt 0x1201"); 955 system_ctl_set_bit(0, 14); 956 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) 957 panic("Couldn't request external interrupt 0x1202"); 958 system_ctl_set_bit(0, 13); 959 smp_rescan_cpus(true); 960 } 961 962 void __init smp_prepare_boot_cpu(void) 963 { 964 struct lowcore *lc = get_lowcore(); 965 966 WARN_ON(!cpu_present(0) || !cpu_online(0)); 967 lc->percpu_offset = __per_cpu_offset[0]; 968 ipl_pcpu = per_cpu_ptr(&pcpu_devices, 0); 969 ipl_pcpu->state = CPU_STATE_CONFIGURED; 970 lc->pcpu = (unsigned long)ipl_pcpu; 971 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); 972 smp_cpu_set_capacity(0, CPU_CAPACITY_HIGH); 973 } 974 975 void __init smp_setup_processor_id(void) 976 { 977 struct lowcore *lc = get_lowcore(); 978 979 lc->cpu_nr = 0; 980 per_cpu(pcpu_devices, 0).address = stap(); 981 lc->spinlock_lockval = arch_spin_lockval(0); 982 lc->spinlock_index = 0; 983 } 984 985 /* 986 * the frequency of the profiling timer can be changed 987 * by writing a multiplier value into /proc/profile. 988 * 989 * usually you want to run this on all CPUs ;) 990 */ 991 int setup_profiling_timer(unsigned int multiplier) 992 { 993 return 0; 994 } 995 996 static ssize_t cpu_configure_show(struct device *dev, 997 struct device_attribute *attr, char *buf) 998 { 999 ssize_t count; 1000 1001 mutex_lock(&smp_cpu_state_mutex); 1002 count = sysfs_emit(buf, "%d\n", per_cpu(pcpu_devices, dev->id).state); 1003 mutex_unlock(&smp_cpu_state_mutex); 1004 return count; 1005 } 1006 1007 static ssize_t cpu_configure_store(struct device *dev, 1008 struct device_attribute *attr, 1009 const char *buf, size_t count) 1010 { 1011 struct pcpu *pcpu; 1012 int cpu, val, rc, i; 1013 char delim; 1014 1015 if (sscanf(buf, "%d %c", &val, &delim) != 1) 1016 return -EINVAL; 1017 if (val != 0 && val != 1) 1018 return -EINVAL; 1019 cpus_read_lock(); 1020 mutex_lock(&smp_cpu_state_mutex); 1021 rc = -EBUSY; 1022 /* disallow configuration changes of online cpus */ 1023 cpu = dev->id; 1024 cpu = smp_get_base_cpu(cpu); 1025 for (i = 0; i <= smp_cpu_mtid; i++) 1026 if (cpu_online(cpu + i)) 1027 goto out; 1028 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 1029 rc = 0; 1030 switch (val) { 1031 case 0: 1032 if (pcpu->state != CPU_STATE_CONFIGURED) 1033 break; 1034 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); 1035 if (rc) 1036 break; 1037 for (i = 0; i <= smp_cpu_mtid; i++) { 1038 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1039 continue; 1040 per_cpu(pcpu_devices, cpu + i).state = CPU_STATE_STANDBY; 1041 smp_cpu_set_polarization(cpu + i, 1042 POLARIZATION_UNKNOWN); 1043 } 1044 topology_expect_change(); 1045 break; 1046 case 1: 1047 if (pcpu->state != CPU_STATE_STANDBY) 1048 break; 1049 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); 1050 if (rc) 1051 break; 1052 for (i = 0; i <= smp_cpu_mtid; i++) { 1053 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1054 continue; 1055 per_cpu(pcpu_devices, cpu + i).state = CPU_STATE_CONFIGURED; 1056 smp_cpu_set_polarization(cpu + i, 1057 POLARIZATION_UNKNOWN); 1058 } 1059 topology_expect_change(); 1060 break; 1061 default: 1062 break; 1063 } 1064 out: 1065 mutex_unlock(&smp_cpu_state_mutex); 1066 cpus_read_unlock(); 1067 return rc ? rc : count; 1068 } 1069 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); 1070 1071 static ssize_t show_cpu_address(struct device *dev, 1072 struct device_attribute *attr, char *buf) 1073 { 1074 return sysfs_emit(buf, "%d\n", per_cpu(pcpu_devices, dev->id).address); 1075 } 1076 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); 1077 1078 static struct attribute *cpu_common_attrs[] = { 1079 &dev_attr_configure.attr, 1080 &dev_attr_address.attr, 1081 NULL, 1082 }; 1083 1084 static struct attribute_group cpu_common_attr_group = { 1085 .attrs = cpu_common_attrs, 1086 }; 1087 1088 static struct attribute *cpu_online_attrs[] = { 1089 &dev_attr_idle_count.attr, 1090 &dev_attr_idle_time_us.attr, 1091 NULL, 1092 }; 1093 1094 static struct attribute_group cpu_online_attr_group = { 1095 .attrs = cpu_online_attrs, 1096 }; 1097 1098 static int smp_cpu_online(unsigned int cpu) 1099 { 1100 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1101 1102 return sysfs_create_group(&c->dev.kobj, &cpu_online_attr_group); 1103 } 1104 1105 static int smp_cpu_pre_down(unsigned int cpu) 1106 { 1107 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1108 1109 sysfs_remove_group(&c->dev.kobj, &cpu_online_attr_group); 1110 return 0; 1111 } 1112 1113 bool arch_cpu_is_hotpluggable(int cpu) 1114 { 1115 return !!cpu; 1116 } 1117 1118 int arch_register_cpu(int cpu) 1119 { 1120 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1121 int rc; 1122 1123 c->hotpluggable = arch_cpu_is_hotpluggable(cpu); 1124 rc = register_cpu(c, cpu); 1125 if (rc) 1126 goto out; 1127 rc = sysfs_create_group(&c->dev.kobj, &cpu_common_attr_group); 1128 if (rc) 1129 goto out_cpu; 1130 rc = topology_cpu_init(c); 1131 if (rc) 1132 goto out_topology; 1133 return 0; 1134 1135 out_topology: 1136 sysfs_remove_group(&c->dev.kobj, &cpu_common_attr_group); 1137 out_cpu: 1138 unregister_cpu(c); 1139 out: 1140 return rc; 1141 } 1142 1143 int __ref smp_rescan_cpus(bool early) 1144 { 1145 struct sclp_core_info *info; 1146 int nr; 1147 1148 info = kzalloc(sizeof(*info), GFP_KERNEL); 1149 if (!info) 1150 return -ENOMEM; 1151 smp_get_core_info(info, 0); 1152 nr = __smp_rescan_cpus(info, early); 1153 kfree(info); 1154 if (nr) 1155 topology_schedule_update(); 1156 return 0; 1157 } 1158 1159 static ssize_t __ref rescan_store(struct device *dev, 1160 struct device_attribute *attr, 1161 const char *buf, 1162 size_t count) 1163 { 1164 int rc; 1165 1166 rc = lock_device_hotplug_sysfs(); 1167 if (rc) 1168 return rc; 1169 rc = smp_rescan_cpus(false); 1170 unlock_device_hotplug(); 1171 return rc ? rc : count; 1172 } 1173 static DEVICE_ATTR_WO(rescan); 1174 1175 static int __init s390_smp_init(void) 1176 { 1177 struct device *dev_root; 1178 int rc; 1179 1180 dev_root = bus_get_dev_root(&cpu_subsys); 1181 if (dev_root) { 1182 rc = device_create_file(dev_root, &dev_attr_rescan); 1183 put_device(dev_root); 1184 if (rc) 1185 return rc; 1186 } 1187 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", 1188 smp_cpu_online, smp_cpu_pre_down); 1189 rc = rc <= 0 ? rc : 0; 1190 return rc; 1191 } 1192 subsys_initcall(s390_smp_init); 1193