1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp 2000, 2011 4 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, 5 * Denis Joseph Barrow, 6 */ 7 8#include <linux/linkage.h> 9#include <asm/asm-offsets.h> 10#include <asm/sigp.h> 11 12# 13# Issue "store status" for the current CPU to its prefix page 14# and call passed function afterwards 15# 16# r2 = Function to be called after store status 17# r3 = Parameter for function 18# 19ENTRY(store_status) 20 /* Save register one and load save area base */ 21 stg %r1,__LC_SAVE_AREA_RESTART 22 /* General purpose registers */ 23 lghi %r1,__LC_GPREGS_SAVE_AREA 24 stmg %r0,%r15,0(%r1) 25 mvc 8(8,%r1),__LC_SAVE_AREA_RESTART 26 /* Control registers */ 27 lghi %r1,__LC_CREGS_SAVE_AREA 28 stctg %c0,%c15,0(%r1) 29 /* Access registers */ 30 lghi %r1,__LC_AREGS_SAVE_AREA 31 stam %a0,%a15,0(%r1) 32 /* Floating point registers */ 33 lghi %r1,__LC_FPREGS_SAVE_AREA 34 std %f0, 0x00(%r1) 35 std %f1, 0x08(%r1) 36 std %f2, 0x10(%r1) 37 std %f3, 0x18(%r1) 38 std %f4, 0x20(%r1) 39 std %f5, 0x28(%r1) 40 std %f6, 0x30(%r1) 41 std %f7, 0x38(%r1) 42 std %f8, 0x40(%r1) 43 std %f9, 0x48(%r1) 44 std %f10,0x50(%r1) 45 std %f11,0x58(%r1) 46 std %f12,0x60(%r1) 47 std %f13,0x68(%r1) 48 std %f14,0x70(%r1) 49 std %f15,0x78(%r1) 50 /* Floating point control register */ 51 lghi %r1,__LC_FP_CREG_SAVE_AREA 52 stfpc 0(%r1) 53 /* CPU timer */ 54 lghi %r1,__LC_CPU_TIMER_SAVE_AREA 55 stpt 0(%r1) 56 /* Store prefix register */ 57 lghi %r1,__LC_PREFIX_SAVE_AREA 58 stpx 0(%r1) 59 /* Clock comparator - seven bytes */ 60 lghi %r1,__LC_CLOCK_COMP_SAVE_AREA 61 larl %r4,.Lclkcmp 62 stckc 0(%r4) 63 mvc 1(7,%r1),1(%r4) 64 /* Program status word */ 65 lghi %r1,__LC_PSW_SAVE_AREA 66 epsw %r4,%r5 67 st %r4,0(%r1) 68 st %r5,4(%r1) 69 stg %r2,8(%r1) 70 lgr %r1,%r2 71 lgr %r2,%r3 72 br %r1 73 74 .section .bss 75 .align 8 76.Lclkcmp: .quad 0x0000000000000000 77 .previous 78 79# 80# do_reipl_asm 81# Parameter: r2 = schid of reipl device 82# 83 84ENTRY(do_reipl_asm) 85 basr %r13,0 86.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13) 87.Lpg1: lgr %r3,%r2 88 larl %r2,.Lstatus 89 brasl %r14,store_status 90 91.Lstatus: lctlg %c6,%c6,.Lall-.Lpg0(%r13) 92 lgr %r1,%r2 93 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13) 94 stsch .Lschib-.Lpg0(%r13) 95 oi .Lschib+5-.Lpg0(%r13),0x84 96.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01 97 msch .Lschib-.Lpg0(%r13) 98 lghi %r0,5 99.Lssch: ssch .Liplorb-.Lpg0(%r13) 100 jz .L001 101 brct %r0,.Lssch 102 bas %r14,.Ldisab-.Lpg0(%r13) 103.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13) 104.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13) 105.Lcont: c %r1,__LC_SUBCHANNEL_ID 106 jnz .Ltpi 107 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13) 108 jnz .Ltpi 109 tsch .Liplirb-.Lpg0(%r13) 110 tm .Liplirb+9-.Lpg0(%r13),0xbf 111 jz .L002 112 bas %r14,.Ldisab-.Lpg0(%r13) 113.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3 114 jz .L003 115 bas %r14,.Ldisab-.Lpg0(%r13) 116.L003: st %r1,__LC_SUBCHANNEL_ID 117 lhi %r1,0 # mode 0 = esa 118 slr %r0,%r0 # set cpuid to zero 119 sigp %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode 120 lpsw 0 121.Ldisab: sll %r14,1 122 srl %r14,1 # need to kill hi bit to avoid specification exceptions. 123 st %r14,.Ldispsw+12-.Lpg0(%r13) 124 lpswe .Ldispsw-.Lpg0(%r13) 125 .align 8 126.Lall: .quad 0x00000000ff000000 127 .align 16 128/* 129 * These addresses have to be 31 bit otherwise 130 * the sigp will throw a specifcation exception 131 * when switching to ESA mode as bit 31 be set 132 * in the ESA psw. 133 * Bit 31 of the addresses has to be 0 for the 134 * 31bit lpswe instruction a fact they appear to have 135 * omitted from the pop. 136 */ 137.Lnewpsw: .quad 0x0000000080000000 138 .quad .Lpg1 139.Lpcnew: .quad 0x0000000080000000 140 .quad .Lecs 141.Lionew: .quad 0x0000000080000000 142 .quad .Lcont 143.Lwaitpsw: .quad 0x0202000080000000 144 .quad .Ltpi 145.Ldispsw: .quad 0x0002000080000000 146 .quad 0x0000000000000000 147.Liplccws: .long 0x02000000,0x60000018 148 .long 0x08000008,0x20000001 149.Liplorb: .long 0x0049504c,0x0040ff80 150 .long 0x00000000+.Liplccws 151.Lschib: .long 0x00000000,0x00000000 152 .long 0x00000000,0x00000000 153 .long 0x00000000,0x00000000 154 .long 0x00000000,0x00000000 155 .long 0x00000000,0x00000000 156 .long 0x00000000,0x00000000 157.Liplirb: .long 0x00000000,0x00000000 158 .long 0x00000000,0x00000000 159 .long 0x00000000,0x00000000 160 .long 0x00000000,0x00000000 161 .long 0x00000000,0x00000000 162 .long 0x00000000,0x00000000 163 .long 0x00000000,0x00000000 164 .long 0x00000000,0x00000000 165