1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/cpufeature.h> 13 #include <linux/interrupt.h> 14 #include <linux/seq_file.h> 15 #include <linux/proc_fs.h> 16 #include <linux/profile.h> 17 #include <linux/export.h> 18 #include <linux/kernel.h> 19 #include <linux/ftrace.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/init.h> 23 #include <linux/cpu.h> 24 #include <linux/irq.h> 25 #include <linux/entry-common.h> 26 #include <asm/irq_regs.h> 27 #include <asm/cputime.h> 28 #include <asm/lowcore.h> 29 #include <asm/machine.h> 30 #include <asm/irq.h> 31 #include <asm/hw_irq.h> 32 #include <asm/stacktrace.h> 33 #include <asm/softirq_stack.h> 34 #include <asm/vtime.h> 35 #include <asm/asm.h> 36 #include <asm/entry-percpu.h> 37 #include "entry.h" 38 39 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 40 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 41 42 struct irq_class { 43 int irq; 44 char *name; 45 char *desc; 46 }; 47 48 /* 49 * The list of "main" irq classes on s390. This is the list of interrupts 50 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 51 * Historically only external and I/O interrupts have been part of /proc/stat. 52 * We can't add the split external and I/O sub classes since the first field 53 * in the "intr" line in /proc/stat is supposed to be the sum of all other 54 * fields. 55 * Since the external and I/O interrupt fields are already sums we would end 56 * up with having a sum which accounts each interrupt twice. 57 */ 58 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 59 {.irq = EXT_INTERRUPT, .name = "EXT"}, 60 {.irq = IO_INTERRUPT, .name = "I/O"}, 61 {.irq = THIN_INTERRUPT, .name = "AIO"}, 62 }; 63 64 /* 65 * The list of split external and I/O interrupts that appear only in 66 * /proc/interrupts. 67 * In addition this list contains non external / I/O events like NMIs. 68 */ 69 static const struct irq_class irqclass_sub_desc[] = { 70 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 71 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 72 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 73 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 74 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 75 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 76 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 77 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 78 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 79 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 80 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 81 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 82 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 83 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"}, 84 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 85 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 86 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 87 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 88 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 89 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 90 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 91 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 92 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 93 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 94 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 95 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 96 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 97 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 98 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 99 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 100 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 101 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 102 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 103 }; 104 105 static void do_IRQ(struct pt_regs *regs, int irq) 106 { 107 struct lowcore *lc = get_lowcore(); 108 109 /* Serve timer interrupts first */ 110 if (tod_after_eq(lc->int_clock.tod, lc->clock_comparator)) 111 clock_comparator_work(); 112 generic_handle_irq(irq); 113 } 114 115 static int on_async_stack(void) 116 { 117 unsigned long frame = current_frame_address(); 118 119 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 120 } 121 122 static void do_irq_async(struct pt_regs *regs, int irq) 123 { 124 if (on_async_stack()) { 125 do_IRQ(regs, irq); 126 } else { 127 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ, 128 struct pt_regs *, regs, int, irq); 129 } 130 } 131 132 static int irq_pending(struct pt_regs *regs) 133 { 134 int cc; 135 136 asm volatile( 137 " tpi 0\n" 138 CC_IPM(cc) 139 : CC_OUT(cc, cc) 140 : 141 : CC_CLOBBER); 142 return CC_TRANSFORM(cc); 143 } 144 145 void noinstr do_io_irq(struct pt_regs *regs) 146 { 147 struct pt_regs *old_regs; 148 irqentry_state_t state; 149 bool from_idle; 150 151 percpu_entry(regs); 152 state = irqentry_enter(regs); 153 old_regs = set_irq_regs(regs); 154 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 155 if (from_idle) 156 update_timer_idle(); 157 158 irq_enter_rcu(); 159 160 if (user_mode(regs)) { 161 update_timer_sys(); 162 if (cpu_has_bear()) 163 current->thread.last_break = regs->last_break; 164 } 165 166 if (from_idle) 167 account_idle_time_irq(); 168 169 do { 170 regs->tpi_info = get_lowcore()->tpi_info; 171 if (get_lowcore()->tpi_info.adapter_IO) 172 do_irq_async(regs, THIN_INTERRUPT); 173 else 174 do_irq_async(regs, IO_INTERRUPT); 175 } while (machine_is_lpar() && irq_pending(regs)); 176 177 irq_exit_rcu(); 178 set_irq_regs(old_regs); 179 irqentry_exit(regs, state); 180 181 if (from_idle) 182 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 183 percpu_exit(regs); 184 } 185 186 void noinstr do_ext_irq(struct pt_regs *regs) 187 { 188 struct pt_regs *old_regs; 189 irqentry_state_t state; 190 bool from_idle; 191 192 percpu_entry(regs); 193 state = irqentry_enter(regs); 194 old_regs = set_irq_regs(regs); 195 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 196 if (from_idle) 197 update_timer_idle(); 198 199 irq_enter_rcu(); 200 201 if (user_mode(regs)) { 202 update_timer_sys(); 203 if (cpu_has_bear()) 204 current->thread.last_break = regs->last_break; 205 } 206 207 regs->int_code = get_lowcore()->ext_int_code_addr; 208 regs->int_parm = get_lowcore()->ext_params; 209 regs->int_parm_long = get_lowcore()->ext_params2; 210 211 if (from_idle) 212 account_idle_time_irq(); 213 214 do_irq_async(regs, EXT_INTERRUPT); 215 216 irq_exit_rcu(); 217 set_irq_regs(old_regs); 218 irqentry_exit(regs, state); 219 220 if (from_idle) 221 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 222 percpu_exit(regs); 223 } 224 225 static void show_msi_interrupt(struct seq_file *p, int irq) 226 { 227 struct irq_desc *desc; 228 unsigned long flags; 229 int cpu; 230 231 rcu_read_lock(); 232 desc = irq_to_desc(irq); 233 if (!desc) 234 goto out; 235 236 raw_spin_lock_irqsave(&desc->lock, flags); 237 seq_printf(p, "%3d: ", irq); 238 for_each_online_cpu(cpu) 239 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 240 241 if (desc->irq_data.chip) 242 seq_printf(p, " %8s", desc->irq_data.chip->name); 243 244 if (desc->action) 245 seq_printf(p, " %s", desc->action->name); 246 247 seq_putc(p, '\n'); 248 raw_spin_unlock_irqrestore(&desc->lock, flags); 249 out: 250 rcu_read_unlock(); 251 } 252 253 /* 254 * show_interrupts is needed by /proc/interrupts. 255 */ 256 int show_interrupts(struct seq_file *p, void *v) 257 { 258 int index = *(loff_t *) v; 259 int cpu, irq; 260 261 cpus_read_lock(); 262 if (index == 0) { 263 seq_puts(p, " "); 264 for_each_online_cpu(cpu) 265 seq_printf(p, "CPU%-8d", cpu); 266 seq_putc(p, '\n'); 267 } 268 if (index < NR_IRQS_BASE) { 269 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 270 irq = irqclass_main_desc[index].irq; 271 for_each_online_cpu(cpu) 272 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 273 seq_putc(p, '\n'); 274 goto out; 275 } 276 if (index < irq_get_nr_irqs()) { 277 show_msi_interrupt(p, index); 278 goto out; 279 } 280 for (index = 0; index < NR_ARCH_IRQS; index++) { 281 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 282 irq = irqclass_sub_desc[index].irq; 283 for_each_online_cpu(cpu) 284 seq_printf(p, "%10u ", 285 per_cpu(irq_stat, cpu).irqs[irq]); 286 if (irqclass_sub_desc[index].desc) 287 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 288 seq_putc(p, '\n'); 289 } 290 out: 291 cpus_read_unlock(); 292 return 0; 293 } 294 295 unsigned int arch_dynirq_lower_bound(unsigned int from) 296 { 297 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 298 } 299 300 /* 301 * ext_int_hash[index] is the list head for all external interrupts that hash 302 * to this index. 303 */ 304 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 305 306 struct ext_int_info { 307 ext_int_handler_t handler; 308 struct hlist_node entry; 309 struct rcu_head rcu; 310 u16 code; 311 }; 312 313 /* ext_int_hash_lock protects the handler lists for external interrupts */ 314 static DEFINE_SPINLOCK(ext_int_hash_lock); 315 316 static inline int ext_hash(u16 code) 317 { 318 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 319 320 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 321 } 322 323 int register_external_irq(u16 code, ext_int_handler_t handler) 324 { 325 struct ext_int_info *p; 326 unsigned long flags; 327 int index; 328 329 p = kmalloc_obj(*p, GFP_ATOMIC); 330 if (!p) 331 return -ENOMEM; 332 p->code = code; 333 p->handler = handler; 334 index = ext_hash(code); 335 336 spin_lock_irqsave(&ext_int_hash_lock, flags); 337 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 338 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 339 return 0; 340 } 341 EXPORT_SYMBOL(register_external_irq); 342 343 int unregister_external_irq(u16 code, ext_int_handler_t handler) 344 { 345 struct ext_int_info *p; 346 unsigned long flags; 347 int index = ext_hash(code); 348 349 spin_lock_irqsave(&ext_int_hash_lock, flags); 350 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 351 if (p->code == code && p->handler == handler) { 352 hlist_del_rcu(&p->entry); 353 kfree_rcu(p, rcu); 354 } 355 } 356 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 357 return 0; 358 } 359 EXPORT_SYMBOL(unregister_external_irq); 360 361 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 362 { 363 struct pt_regs *regs = get_irq_regs(); 364 struct ext_code ext_code; 365 struct ext_int_info *p; 366 int index; 367 368 ext_code.int_code = regs->int_code; 369 index = ext_hash(ext_code.code); 370 rcu_read_lock(); 371 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 372 if (unlikely(p->code != ext_code.code)) 373 continue; 374 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 375 } 376 rcu_read_unlock(); 377 return IRQ_HANDLED; 378 } 379 380 static void __init init_ext_interrupts(void) 381 { 382 int idx; 383 384 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 385 INIT_HLIST_HEAD(&ext_int_hash[idx]); 386 387 irq_set_chip_and_handler(EXT_INTERRUPT, 388 &dummy_irq_chip, handle_percpu_irq); 389 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 390 panic("Failed to register EXT interrupt\n"); 391 } 392 393 void __init init_IRQ(void) 394 { 395 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 396 init_cio_interrupts(); 397 init_airq_interrupts(); 398 init_ext_interrupts(); 399 } 400 401 static DEFINE_SPINLOCK(irq_subclass_lock); 402 static unsigned char irq_subclass_refcount[64]; 403 404 void irq_subclass_register(enum irq_subclass subclass) 405 { 406 spin_lock(&irq_subclass_lock); 407 if (!irq_subclass_refcount[subclass]) 408 system_ctl_set_bit(0, subclass); 409 irq_subclass_refcount[subclass]++; 410 spin_unlock(&irq_subclass_lock); 411 } 412 EXPORT_SYMBOL(irq_subclass_register); 413 414 void irq_subclass_unregister(enum irq_subclass subclass) 415 { 416 spin_lock(&irq_subclass_lock); 417 irq_subclass_refcount[subclass]--; 418 if (!irq_subclass_refcount[subclass]) 419 system_ctl_clear_bit(0, subclass); 420 spin_unlock(&irq_subclass_lock); 421 } 422 EXPORT_SYMBOL(irq_subclass_unregister); 423