1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/proc_fs.h> 15 #include <linux/profile.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/ftrace.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/init.h> 22 #include <linux/cpu.h> 23 #include <linux/irq.h> 24 #include <linux/entry-common.h> 25 #include <asm/irq_regs.h> 26 #include <asm/cputime.h> 27 #include <asm/lowcore.h> 28 #include <asm/irq.h> 29 #include <asm/hw_irq.h> 30 #include <asm/stacktrace.h> 31 #include <asm/softirq_stack.h> 32 #include "entry.h" 33 34 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 35 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 36 37 struct irq_class { 38 int irq; 39 char *name; 40 char *desc; 41 }; 42 43 /* 44 * The list of "main" irq classes on s390. This is the list of interrupts 45 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 46 * Historically only external and I/O interrupts have been part of /proc/stat. 47 * We can't add the split external and I/O sub classes since the first field 48 * in the "intr" line in /proc/stat is supposed to be the sum of all other 49 * fields. 50 * Since the external and I/O interrupt fields are already sums we would end 51 * up with having a sum which accounts each interrupt twice. 52 */ 53 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 54 {.irq = EXT_INTERRUPT, .name = "EXT"}, 55 {.irq = IO_INTERRUPT, .name = "I/O"}, 56 {.irq = THIN_INTERRUPT, .name = "AIO"}, 57 }; 58 59 /* 60 * The list of split external and I/O interrupts that appear only in 61 * /proc/interrupts. 62 * In addition this list contains non external / I/O events like NMIs. 63 */ 64 static const struct irq_class irqclass_sub_desc[] = { 65 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 66 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 67 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 68 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 69 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 70 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 71 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 72 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 73 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 74 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 75 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 76 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 77 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 78 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 79 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 80 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 81 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 82 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 83 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 84 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, 85 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 86 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 87 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 88 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 89 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 90 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 91 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 92 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 93 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 94 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 95 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 96 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 97 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 98 }; 99 100 static void do_IRQ(struct pt_regs *regs, int irq) 101 { 102 if (tod_after_eq(S390_lowcore.int_clock, 103 S390_lowcore.clock_comparator)) 104 /* Serve timer interrupts first. */ 105 clock_comparator_work(); 106 generic_handle_irq(irq); 107 } 108 109 static int on_async_stack(void) 110 { 111 unsigned long frame = current_frame_address(); 112 113 return ((S390_lowcore.async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 114 } 115 116 static void do_irq_async(struct pt_regs *regs, int irq) 117 { 118 if (on_async_stack()) { 119 do_IRQ(regs, irq); 120 } else { 121 call_on_stack(2, S390_lowcore.async_stack, void, do_IRQ, 122 struct pt_regs *, regs, int, irq); 123 } 124 } 125 126 static int irq_pending(struct pt_regs *regs) 127 { 128 int cc; 129 130 asm volatile("tpi 0\n" 131 "ipm %0" : "=d" (cc) : : "cc"); 132 return cc >> 28; 133 } 134 135 void noinstr do_io_irq(struct pt_regs *regs) 136 { 137 irqentry_state_t state = irqentry_enter(regs); 138 struct pt_regs *old_regs = set_irq_regs(regs); 139 int from_idle; 140 141 irq_enter(); 142 143 if (user_mode(regs)) { 144 update_timer_sys(); 145 if (static_branch_likely(&cpu_has_bear)) 146 current->thread.last_break = regs->last_break; 147 } 148 149 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 150 if (from_idle) 151 account_idle_time_irq(); 152 153 do { 154 regs->tpi_info = S390_lowcore.tpi_info; 155 if (S390_lowcore.tpi_info.adapter_IO) 156 do_irq_async(regs, THIN_INTERRUPT); 157 else 158 do_irq_async(regs, IO_INTERRUPT); 159 } while (MACHINE_IS_LPAR && irq_pending(regs)); 160 161 irq_exit(); 162 set_irq_regs(old_regs); 163 irqentry_exit(regs, state); 164 165 if (from_idle) 166 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 167 } 168 169 void noinstr do_ext_irq(struct pt_regs *regs) 170 { 171 irqentry_state_t state = irqentry_enter(regs); 172 struct pt_regs *old_regs = set_irq_regs(regs); 173 int from_idle; 174 175 irq_enter(); 176 177 if (user_mode(regs)) { 178 update_timer_sys(); 179 if (static_branch_likely(&cpu_has_bear)) 180 current->thread.last_break = regs->last_break; 181 } 182 183 regs->int_code = S390_lowcore.ext_int_code_addr; 184 regs->int_parm = S390_lowcore.ext_params; 185 regs->int_parm_long = S390_lowcore.ext_params2; 186 187 from_idle = !user_mode(regs) && regs->psw.addr == (unsigned long)psw_idle_exit; 188 if (from_idle) 189 account_idle_time_irq(); 190 191 do_irq_async(regs, EXT_INTERRUPT); 192 193 irq_exit(); 194 set_irq_regs(old_regs); 195 irqentry_exit(regs, state); 196 197 if (from_idle) 198 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 199 } 200 201 static void show_msi_interrupt(struct seq_file *p, int irq) 202 { 203 struct irq_desc *desc; 204 unsigned long flags; 205 int cpu; 206 207 irq_lock_sparse(); 208 desc = irq_to_desc(irq); 209 if (!desc) 210 goto out; 211 212 raw_spin_lock_irqsave(&desc->lock, flags); 213 seq_printf(p, "%3d: ", irq); 214 for_each_online_cpu(cpu) 215 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 216 217 if (desc->irq_data.chip) 218 seq_printf(p, " %8s", desc->irq_data.chip->name); 219 220 if (desc->action) 221 seq_printf(p, " %s", desc->action->name); 222 223 seq_putc(p, '\n'); 224 raw_spin_unlock_irqrestore(&desc->lock, flags); 225 out: 226 irq_unlock_sparse(); 227 } 228 229 /* 230 * show_interrupts is needed by /proc/interrupts. 231 */ 232 int show_interrupts(struct seq_file *p, void *v) 233 { 234 int index = *(loff_t *) v; 235 int cpu, irq; 236 237 cpus_read_lock(); 238 if (index == 0) { 239 seq_puts(p, " "); 240 for_each_online_cpu(cpu) 241 seq_printf(p, "CPU%-8d", cpu); 242 seq_putc(p, '\n'); 243 } 244 if (index < NR_IRQS_BASE) { 245 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 246 irq = irqclass_main_desc[index].irq; 247 for_each_online_cpu(cpu) 248 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 249 seq_putc(p, '\n'); 250 goto out; 251 } 252 if (index < nr_irqs) { 253 show_msi_interrupt(p, index); 254 goto out; 255 } 256 for (index = 0; index < NR_ARCH_IRQS; index++) { 257 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 258 irq = irqclass_sub_desc[index].irq; 259 for_each_online_cpu(cpu) 260 seq_printf(p, "%10u ", 261 per_cpu(irq_stat, cpu).irqs[irq]); 262 if (irqclass_sub_desc[index].desc) 263 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 264 seq_putc(p, '\n'); 265 } 266 out: 267 cpus_read_unlock(); 268 return 0; 269 } 270 271 unsigned int arch_dynirq_lower_bound(unsigned int from) 272 { 273 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 274 } 275 276 /* 277 * ext_int_hash[index] is the list head for all external interrupts that hash 278 * to this index. 279 */ 280 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 281 282 struct ext_int_info { 283 ext_int_handler_t handler; 284 struct hlist_node entry; 285 struct rcu_head rcu; 286 u16 code; 287 }; 288 289 /* ext_int_hash_lock protects the handler lists for external interrupts */ 290 static DEFINE_SPINLOCK(ext_int_hash_lock); 291 292 static inline int ext_hash(u16 code) 293 { 294 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 295 296 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 297 } 298 299 int register_external_irq(u16 code, ext_int_handler_t handler) 300 { 301 struct ext_int_info *p; 302 unsigned long flags; 303 int index; 304 305 p = kmalloc(sizeof(*p), GFP_ATOMIC); 306 if (!p) 307 return -ENOMEM; 308 p->code = code; 309 p->handler = handler; 310 index = ext_hash(code); 311 312 spin_lock_irqsave(&ext_int_hash_lock, flags); 313 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 314 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 315 return 0; 316 } 317 EXPORT_SYMBOL(register_external_irq); 318 319 int unregister_external_irq(u16 code, ext_int_handler_t handler) 320 { 321 struct ext_int_info *p; 322 unsigned long flags; 323 int index = ext_hash(code); 324 325 spin_lock_irqsave(&ext_int_hash_lock, flags); 326 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 327 if (p->code == code && p->handler == handler) { 328 hlist_del_rcu(&p->entry); 329 kfree_rcu(p, rcu); 330 } 331 } 332 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 333 return 0; 334 } 335 EXPORT_SYMBOL(unregister_external_irq); 336 337 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 338 { 339 struct pt_regs *regs = get_irq_regs(); 340 struct ext_code ext_code; 341 struct ext_int_info *p; 342 int index; 343 344 ext_code = *(struct ext_code *) ®s->int_code; 345 if (ext_code.code != EXT_IRQ_CLK_COMP) 346 set_cpu_flag(CIF_NOHZ_DELAY); 347 348 index = ext_hash(ext_code.code); 349 rcu_read_lock(); 350 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 351 if (unlikely(p->code != ext_code.code)) 352 continue; 353 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 354 } 355 rcu_read_unlock(); 356 return IRQ_HANDLED; 357 } 358 359 static void __init init_ext_interrupts(void) 360 { 361 int idx; 362 363 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 364 INIT_HLIST_HEAD(&ext_int_hash[idx]); 365 366 irq_set_chip_and_handler(EXT_INTERRUPT, 367 &dummy_irq_chip, handle_percpu_irq); 368 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 369 panic("Failed to register EXT interrupt\n"); 370 } 371 372 void __init init_IRQ(void) 373 { 374 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 375 init_cio_interrupts(); 376 init_airq_interrupts(); 377 init_ext_interrupts(); 378 } 379 380 static DEFINE_SPINLOCK(irq_subclass_lock); 381 static unsigned char irq_subclass_refcount[64]; 382 383 void irq_subclass_register(enum irq_subclass subclass) 384 { 385 spin_lock(&irq_subclass_lock); 386 if (!irq_subclass_refcount[subclass]) 387 ctl_set_bit(0, subclass); 388 irq_subclass_refcount[subclass]++; 389 spin_unlock(&irq_subclass_lock); 390 } 391 EXPORT_SYMBOL(irq_subclass_register); 392 393 void irq_subclass_unregister(enum irq_subclass subclass) 394 { 395 spin_lock(&irq_subclass_lock); 396 irq_subclass_refcount[subclass]--; 397 if (!irq_subclass_refcount[subclass]) 398 ctl_clear_bit(0, subclass); 399 spin_unlock(&irq_subclass_lock); 400 } 401 EXPORT_SYMBOL(irq_subclass_unregister); 402