1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/proc_fs.h> 15 #include <linux/profile.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/ftrace.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/init.h> 22 #include <linux/cpu.h> 23 #include <linux/irq.h> 24 #include <linux/entry-common.h> 25 #include <asm/irq_regs.h> 26 #include <asm/cputime.h> 27 #include <asm/lowcore.h> 28 #include <asm/irq.h> 29 #include <asm/hw_irq.h> 30 #include <asm/stacktrace.h> 31 #include <asm/softirq_stack.h> 32 #include <asm/vtime.h> 33 #include "entry.h" 34 35 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 36 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 37 38 struct irq_class { 39 int irq; 40 char *name; 41 char *desc; 42 }; 43 44 /* 45 * The list of "main" irq classes on s390. This is the list of interrupts 46 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 47 * Historically only external and I/O interrupts have been part of /proc/stat. 48 * We can't add the split external and I/O sub classes since the first field 49 * in the "intr" line in /proc/stat is supposed to be the sum of all other 50 * fields. 51 * Since the external and I/O interrupt fields are already sums we would end 52 * up with having a sum which accounts each interrupt twice. 53 */ 54 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 55 {.irq = EXT_INTERRUPT, .name = "EXT"}, 56 {.irq = IO_INTERRUPT, .name = "I/O"}, 57 {.irq = THIN_INTERRUPT, .name = "AIO"}, 58 }; 59 60 /* 61 * The list of split external and I/O interrupts that appear only in 62 * /proc/interrupts. 63 * In addition this list contains non external / I/O events like NMIs. 64 */ 65 static const struct irq_class irqclass_sub_desc[] = { 66 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 67 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 68 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 69 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 70 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 71 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 72 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 73 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 74 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 75 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 76 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 77 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 78 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 79 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 80 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 81 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 82 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 83 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 84 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 85 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"}, 86 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 87 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 88 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 89 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 90 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 91 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 92 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 93 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 94 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 95 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 96 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 97 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 98 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 99 }; 100 101 static void do_IRQ(struct pt_regs *regs, int irq) 102 { 103 if (tod_after_eq(S390_lowcore.int_clock, 104 S390_lowcore.clock_comparator)) 105 /* Serve timer interrupts first. */ 106 clock_comparator_work(); 107 generic_handle_irq(irq); 108 } 109 110 static int on_async_stack(void) 111 { 112 unsigned long frame = current_frame_address(); 113 114 return ((S390_lowcore.async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 115 } 116 117 static void do_irq_async(struct pt_regs *regs, int irq) 118 { 119 if (on_async_stack()) { 120 do_IRQ(regs, irq); 121 } else { 122 call_on_stack(2, S390_lowcore.async_stack, void, do_IRQ, 123 struct pt_regs *, regs, int, irq); 124 } 125 } 126 127 static int irq_pending(struct pt_regs *regs) 128 { 129 int cc; 130 131 asm volatile("tpi 0\n" 132 "ipm %0" : "=d" (cc) : : "cc"); 133 return cc >> 28; 134 } 135 136 void noinstr do_io_irq(struct pt_regs *regs) 137 { 138 irqentry_state_t state = irqentry_enter(regs); 139 struct pt_regs *old_regs = set_irq_regs(regs); 140 bool from_idle; 141 142 irq_enter_rcu(); 143 144 if (user_mode(regs)) { 145 update_timer_sys(); 146 if (static_branch_likely(&cpu_has_bear)) 147 current->thread.last_break = regs->last_break; 148 } 149 150 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 151 if (from_idle) 152 account_idle_time_irq(); 153 154 do { 155 regs->tpi_info = S390_lowcore.tpi_info; 156 if (S390_lowcore.tpi_info.adapter_IO) 157 do_irq_async(regs, THIN_INTERRUPT); 158 else 159 do_irq_async(regs, IO_INTERRUPT); 160 } while (MACHINE_IS_LPAR && irq_pending(regs)); 161 162 irq_exit_rcu(); 163 164 set_irq_regs(old_regs); 165 irqentry_exit(regs, state); 166 167 if (from_idle) 168 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 169 } 170 171 void noinstr do_ext_irq(struct pt_regs *regs) 172 { 173 irqentry_state_t state = irqentry_enter(regs); 174 struct pt_regs *old_regs = set_irq_regs(regs); 175 bool from_idle; 176 177 irq_enter_rcu(); 178 179 if (user_mode(regs)) { 180 update_timer_sys(); 181 if (static_branch_likely(&cpu_has_bear)) 182 current->thread.last_break = regs->last_break; 183 } 184 185 regs->int_code = S390_lowcore.ext_int_code_addr; 186 regs->int_parm = S390_lowcore.ext_params; 187 regs->int_parm_long = S390_lowcore.ext_params2; 188 189 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 190 if (from_idle) 191 account_idle_time_irq(); 192 193 do_irq_async(regs, EXT_INTERRUPT); 194 195 irq_exit_rcu(); 196 set_irq_regs(old_regs); 197 irqentry_exit(regs, state); 198 199 if (from_idle) 200 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 201 } 202 203 static void show_msi_interrupt(struct seq_file *p, int irq) 204 { 205 struct irq_desc *desc; 206 unsigned long flags; 207 int cpu; 208 209 rcu_read_lock(); 210 desc = irq_to_desc(irq); 211 if (!desc) 212 goto out; 213 214 raw_spin_lock_irqsave(&desc->lock, flags); 215 seq_printf(p, "%3d: ", irq); 216 for_each_online_cpu(cpu) 217 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 218 219 if (desc->irq_data.chip) 220 seq_printf(p, " %8s", desc->irq_data.chip->name); 221 222 if (desc->action) 223 seq_printf(p, " %s", desc->action->name); 224 225 seq_putc(p, '\n'); 226 raw_spin_unlock_irqrestore(&desc->lock, flags); 227 out: 228 rcu_read_unlock(); 229 } 230 231 /* 232 * show_interrupts is needed by /proc/interrupts. 233 */ 234 int show_interrupts(struct seq_file *p, void *v) 235 { 236 int index = *(loff_t *) v; 237 int cpu, irq; 238 239 cpus_read_lock(); 240 if (index == 0) { 241 seq_puts(p, " "); 242 for_each_online_cpu(cpu) 243 seq_printf(p, "CPU%-8d", cpu); 244 seq_putc(p, '\n'); 245 } 246 if (index < NR_IRQS_BASE) { 247 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 248 irq = irqclass_main_desc[index].irq; 249 for_each_online_cpu(cpu) 250 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 251 seq_putc(p, '\n'); 252 goto out; 253 } 254 if (index < nr_irqs) { 255 show_msi_interrupt(p, index); 256 goto out; 257 } 258 for (index = 0; index < NR_ARCH_IRQS; index++) { 259 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 260 irq = irqclass_sub_desc[index].irq; 261 for_each_online_cpu(cpu) 262 seq_printf(p, "%10u ", 263 per_cpu(irq_stat, cpu).irqs[irq]); 264 if (irqclass_sub_desc[index].desc) 265 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 266 seq_putc(p, '\n'); 267 } 268 out: 269 cpus_read_unlock(); 270 return 0; 271 } 272 273 unsigned int arch_dynirq_lower_bound(unsigned int from) 274 { 275 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 276 } 277 278 /* 279 * ext_int_hash[index] is the list head for all external interrupts that hash 280 * to this index. 281 */ 282 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 283 284 struct ext_int_info { 285 ext_int_handler_t handler; 286 struct hlist_node entry; 287 struct rcu_head rcu; 288 u16 code; 289 }; 290 291 /* ext_int_hash_lock protects the handler lists for external interrupts */ 292 static DEFINE_SPINLOCK(ext_int_hash_lock); 293 294 static inline int ext_hash(u16 code) 295 { 296 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 297 298 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 299 } 300 301 int register_external_irq(u16 code, ext_int_handler_t handler) 302 { 303 struct ext_int_info *p; 304 unsigned long flags; 305 int index; 306 307 p = kmalloc(sizeof(*p), GFP_ATOMIC); 308 if (!p) 309 return -ENOMEM; 310 p->code = code; 311 p->handler = handler; 312 index = ext_hash(code); 313 314 spin_lock_irqsave(&ext_int_hash_lock, flags); 315 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 316 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 317 return 0; 318 } 319 EXPORT_SYMBOL(register_external_irq); 320 321 int unregister_external_irq(u16 code, ext_int_handler_t handler) 322 { 323 struct ext_int_info *p; 324 unsigned long flags; 325 int index = ext_hash(code); 326 327 spin_lock_irqsave(&ext_int_hash_lock, flags); 328 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 329 if (p->code == code && p->handler == handler) { 330 hlist_del_rcu(&p->entry); 331 kfree_rcu(p, rcu); 332 } 333 } 334 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 335 return 0; 336 } 337 EXPORT_SYMBOL(unregister_external_irq); 338 339 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 340 { 341 struct pt_regs *regs = get_irq_regs(); 342 struct ext_code ext_code; 343 struct ext_int_info *p; 344 int index; 345 346 ext_code.int_code = regs->int_code; 347 if (ext_code.code != EXT_IRQ_CLK_COMP) 348 set_cpu_flag(CIF_NOHZ_DELAY); 349 350 index = ext_hash(ext_code.code); 351 rcu_read_lock(); 352 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 353 if (unlikely(p->code != ext_code.code)) 354 continue; 355 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 356 } 357 rcu_read_unlock(); 358 return IRQ_HANDLED; 359 } 360 361 static void __init init_ext_interrupts(void) 362 { 363 int idx; 364 365 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 366 INIT_HLIST_HEAD(&ext_int_hash[idx]); 367 368 irq_set_chip_and_handler(EXT_INTERRUPT, 369 &dummy_irq_chip, handle_percpu_irq); 370 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 371 panic("Failed to register EXT interrupt\n"); 372 } 373 374 void __init init_IRQ(void) 375 { 376 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 377 init_cio_interrupts(); 378 init_airq_interrupts(); 379 init_ext_interrupts(); 380 } 381 382 static DEFINE_SPINLOCK(irq_subclass_lock); 383 static unsigned char irq_subclass_refcount[64]; 384 385 void irq_subclass_register(enum irq_subclass subclass) 386 { 387 spin_lock(&irq_subclass_lock); 388 if (!irq_subclass_refcount[subclass]) 389 system_ctl_set_bit(0, subclass); 390 irq_subclass_refcount[subclass]++; 391 spin_unlock(&irq_subclass_lock); 392 } 393 EXPORT_SYMBOL(irq_subclass_register); 394 395 void irq_subclass_unregister(enum irq_subclass subclass) 396 { 397 spin_lock(&irq_subclass_lock); 398 irq_subclass_refcount[subclass]--; 399 if (!irq_subclass_refcount[subclass]) 400 system_ctl_clear_bit(0, subclass); 401 spin_unlock(&irq_subclass_lock); 402 } 403 EXPORT_SYMBOL(irq_subclass_unregister); 404