1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/interrupt.h> 13 #include <linux/seq_file.h> 14 #include <linux/proc_fs.h> 15 #include <linux/profile.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/ftrace.h> 19 #include <linux/errno.h> 20 #include <linux/slab.h> 21 #include <linux/init.h> 22 #include <linux/cpu.h> 23 #include <linux/irq.h> 24 #include <linux/entry-common.h> 25 #include <asm/irq_regs.h> 26 #include <asm/cputime.h> 27 #include <asm/lowcore.h> 28 #include <asm/irq.h> 29 #include <asm/hw_irq.h> 30 #include <asm/stacktrace.h> 31 #include <asm/softirq_stack.h> 32 #include <asm/vtime.h> 33 #include <asm/asm.h> 34 #include "entry.h" 35 36 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 37 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 38 39 struct irq_class { 40 int irq; 41 char *name; 42 char *desc; 43 }; 44 45 /* 46 * The list of "main" irq classes on s390. This is the list of interrupts 47 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 48 * Historically only external and I/O interrupts have been part of /proc/stat. 49 * We can't add the split external and I/O sub classes since the first field 50 * in the "intr" line in /proc/stat is supposed to be the sum of all other 51 * fields. 52 * Since the external and I/O interrupt fields are already sums we would end 53 * up with having a sum which accounts each interrupt twice. 54 */ 55 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 56 {.irq = EXT_INTERRUPT, .name = "EXT"}, 57 {.irq = IO_INTERRUPT, .name = "I/O"}, 58 {.irq = THIN_INTERRUPT, .name = "AIO"}, 59 }; 60 61 /* 62 * The list of split external and I/O interrupts that appear only in 63 * /proc/interrupts. 64 * In addition this list contains non external / I/O events like NMIs. 65 */ 66 static const struct irq_class irqclass_sub_desc[] = { 67 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 68 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 69 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 70 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 71 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 72 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 73 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 74 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 75 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 76 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 77 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 78 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 79 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 80 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"}, 81 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 82 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 83 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 84 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 85 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 86 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 87 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 88 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 89 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 90 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 91 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 92 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 93 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 94 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 95 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 96 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 97 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 98 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 99 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 100 }; 101 102 static void do_IRQ(struct pt_regs *regs, int irq) 103 { 104 if (tod_after_eq(get_lowcore()->int_clock, 105 get_lowcore()->clock_comparator)) 106 /* Serve timer interrupts first. */ 107 clock_comparator_work(); 108 generic_handle_irq(irq); 109 } 110 111 static int on_async_stack(void) 112 { 113 unsigned long frame = current_frame_address(); 114 115 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 116 } 117 118 static void do_irq_async(struct pt_regs *regs, int irq) 119 { 120 if (on_async_stack()) { 121 do_IRQ(regs, irq); 122 } else { 123 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ, 124 struct pt_regs *, regs, int, irq); 125 } 126 } 127 128 static int irq_pending(struct pt_regs *regs) 129 { 130 int cc; 131 132 asm volatile( 133 " tpi 0\n" 134 CC_IPM(cc) 135 : CC_OUT(cc, cc) 136 : 137 : CC_CLOBBER); 138 return CC_TRANSFORM(cc); 139 } 140 141 void noinstr do_io_irq(struct pt_regs *regs) 142 { 143 irqentry_state_t state = irqentry_enter(regs); 144 struct pt_regs *old_regs = set_irq_regs(regs); 145 bool from_idle; 146 147 irq_enter_rcu(); 148 149 if (user_mode(regs)) { 150 update_timer_sys(); 151 if (static_branch_likely(&cpu_has_bear)) 152 current->thread.last_break = regs->last_break; 153 } 154 155 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 156 if (from_idle) 157 account_idle_time_irq(); 158 159 set_cpu_flag(CIF_NOHZ_DELAY); 160 do { 161 regs->tpi_info = get_lowcore()->tpi_info; 162 if (get_lowcore()->tpi_info.adapter_IO) 163 do_irq_async(regs, THIN_INTERRUPT); 164 else 165 do_irq_async(regs, IO_INTERRUPT); 166 } while (MACHINE_IS_LPAR && irq_pending(regs)); 167 168 irq_exit_rcu(); 169 170 set_irq_regs(old_regs); 171 irqentry_exit(regs, state); 172 173 if (from_idle) 174 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 175 } 176 177 void noinstr do_ext_irq(struct pt_regs *regs) 178 { 179 irqentry_state_t state = irqentry_enter(regs); 180 struct pt_regs *old_regs = set_irq_regs(regs); 181 bool from_idle; 182 183 irq_enter_rcu(); 184 185 if (user_mode(regs)) { 186 update_timer_sys(); 187 if (static_branch_likely(&cpu_has_bear)) 188 current->thread.last_break = regs->last_break; 189 } 190 191 regs->int_code = get_lowcore()->ext_int_code_addr; 192 regs->int_parm = get_lowcore()->ext_params; 193 regs->int_parm_long = get_lowcore()->ext_params2; 194 195 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 196 if (from_idle) 197 account_idle_time_irq(); 198 199 do_irq_async(regs, EXT_INTERRUPT); 200 201 irq_exit_rcu(); 202 set_irq_regs(old_regs); 203 irqentry_exit(regs, state); 204 205 if (from_idle) 206 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 207 } 208 209 static void show_msi_interrupt(struct seq_file *p, int irq) 210 { 211 struct irq_desc *desc; 212 unsigned long flags; 213 int cpu; 214 215 rcu_read_lock(); 216 desc = irq_to_desc(irq); 217 if (!desc) 218 goto out; 219 220 raw_spin_lock_irqsave(&desc->lock, flags); 221 seq_printf(p, "%3d: ", irq); 222 for_each_online_cpu(cpu) 223 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 224 225 if (desc->irq_data.chip) 226 seq_printf(p, " %8s", desc->irq_data.chip->name); 227 228 if (desc->action) 229 seq_printf(p, " %s", desc->action->name); 230 231 seq_putc(p, '\n'); 232 raw_spin_unlock_irqrestore(&desc->lock, flags); 233 out: 234 rcu_read_unlock(); 235 } 236 237 /* 238 * show_interrupts is needed by /proc/interrupts. 239 */ 240 int show_interrupts(struct seq_file *p, void *v) 241 { 242 int index = *(loff_t *) v; 243 int cpu, irq; 244 245 cpus_read_lock(); 246 if (index == 0) { 247 seq_puts(p, " "); 248 for_each_online_cpu(cpu) 249 seq_printf(p, "CPU%-8d", cpu); 250 seq_putc(p, '\n'); 251 } 252 if (index < NR_IRQS_BASE) { 253 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 254 irq = irqclass_main_desc[index].irq; 255 for_each_online_cpu(cpu) 256 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 257 seq_putc(p, '\n'); 258 goto out; 259 } 260 if (index < irq_get_nr_irqs()) { 261 show_msi_interrupt(p, index); 262 goto out; 263 } 264 for (index = 0; index < NR_ARCH_IRQS; index++) { 265 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 266 irq = irqclass_sub_desc[index].irq; 267 for_each_online_cpu(cpu) 268 seq_printf(p, "%10u ", 269 per_cpu(irq_stat, cpu).irqs[irq]); 270 if (irqclass_sub_desc[index].desc) 271 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 272 seq_putc(p, '\n'); 273 } 274 out: 275 cpus_read_unlock(); 276 return 0; 277 } 278 279 unsigned int arch_dynirq_lower_bound(unsigned int from) 280 { 281 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 282 } 283 284 /* 285 * ext_int_hash[index] is the list head for all external interrupts that hash 286 * to this index. 287 */ 288 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 289 290 struct ext_int_info { 291 ext_int_handler_t handler; 292 struct hlist_node entry; 293 struct rcu_head rcu; 294 u16 code; 295 }; 296 297 /* ext_int_hash_lock protects the handler lists for external interrupts */ 298 static DEFINE_SPINLOCK(ext_int_hash_lock); 299 300 static inline int ext_hash(u16 code) 301 { 302 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 303 304 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 305 } 306 307 int register_external_irq(u16 code, ext_int_handler_t handler) 308 { 309 struct ext_int_info *p; 310 unsigned long flags; 311 int index; 312 313 p = kmalloc(sizeof(*p), GFP_ATOMIC); 314 if (!p) 315 return -ENOMEM; 316 p->code = code; 317 p->handler = handler; 318 index = ext_hash(code); 319 320 spin_lock_irqsave(&ext_int_hash_lock, flags); 321 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 322 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 323 return 0; 324 } 325 EXPORT_SYMBOL(register_external_irq); 326 327 int unregister_external_irq(u16 code, ext_int_handler_t handler) 328 { 329 struct ext_int_info *p; 330 unsigned long flags; 331 int index = ext_hash(code); 332 333 spin_lock_irqsave(&ext_int_hash_lock, flags); 334 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 335 if (p->code == code && p->handler == handler) { 336 hlist_del_rcu(&p->entry); 337 kfree_rcu(p, rcu); 338 } 339 } 340 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 341 return 0; 342 } 343 EXPORT_SYMBOL(unregister_external_irq); 344 345 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 346 { 347 struct pt_regs *regs = get_irq_regs(); 348 struct ext_code ext_code; 349 struct ext_int_info *p; 350 int index; 351 352 ext_code.int_code = regs->int_code; 353 if (ext_code.code != EXT_IRQ_CLK_COMP) 354 set_cpu_flag(CIF_NOHZ_DELAY); 355 356 index = ext_hash(ext_code.code); 357 rcu_read_lock(); 358 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 359 if (unlikely(p->code != ext_code.code)) 360 continue; 361 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 362 } 363 rcu_read_unlock(); 364 return IRQ_HANDLED; 365 } 366 367 static void __init init_ext_interrupts(void) 368 { 369 int idx; 370 371 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 372 INIT_HLIST_HEAD(&ext_int_hash[idx]); 373 374 irq_set_chip_and_handler(EXT_INTERRUPT, 375 &dummy_irq_chip, handle_percpu_irq); 376 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 377 panic("Failed to register EXT interrupt\n"); 378 } 379 380 void __init init_IRQ(void) 381 { 382 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 383 init_cio_interrupts(); 384 init_airq_interrupts(); 385 init_ext_interrupts(); 386 } 387 388 static DEFINE_SPINLOCK(irq_subclass_lock); 389 static unsigned char irq_subclass_refcount[64]; 390 391 void irq_subclass_register(enum irq_subclass subclass) 392 { 393 spin_lock(&irq_subclass_lock); 394 if (!irq_subclass_refcount[subclass]) 395 system_ctl_set_bit(0, subclass); 396 irq_subclass_refcount[subclass]++; 397 spin_unlock(&irq_subclass_lock); 398 } 399 EXPORT_SYMBOL(irq_subclass_register); 400 401 void irq_subclass_unregister(enum irq_subclass subclass) 402 { 403 spin_lock(&irq_subclass_lock); 404 irq_subclass_refcount[subclass]--; 405 if (!irq_subclass_refcount[subclass]) 406 system_ctl_clear_bit(0, subclass); 407 spin_unlock(&irq_subclass_lock); 408 } 409 EXPORT_SYMBOL(irq_subclass_unregister); 410