1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright IBM Corp. 2004, 2011 4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, 5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>, 6 * Thomas Spatzier <tspat@de.ibm.com>, 7 * 8 * This file contains interrupt related functions. 9 */ 10 11 #include <linux/kernel_stat.h> 12 #include <linux/cpufeature.h> 13 #include <linux/interrupt.h> 14 #include <linux/seq_file.h> 15 #include <linux/proc_fs.h> 16 #include <linux/profile.h> 17 #include <linux/export.h> 18 #include <linux/kernel.h> 19 #include <linux/ftrace.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/init.h> 23 #include <linux/cpu.h> 24 #include <linux/irq.h> 25 #include <linux/entry-common.h> 26 #include <asm/irq_regs.h> 27 #include <asm/cputime.h> 28 #include <asm/lowcore.h> 29 #include <asm/machine.h> 30 #include <asm/irq.h> 31 #include <asm/hw_irq.h> 32 #include <asm/stacktrace.h> 33 #include <asm/softirq_stack.h> 34 #include <asm/vtime.h> 35 #include <asm/asm.h> 36 #include "entry.h" 37 38 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); 39 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); 40 41 struct irq_class { 42 int irq; 43 char *name; 44 char *desc; 45 }; 46 47 /* 48 * The list of "main" irq classes on s390. This is the list of interrupts 49 * that appear both in /proc/stat ("intr" line) and /proc/interrupts. 50 * Historically only external and I/O interrupts have been part of /proc/stat. 51 * We can't add the split external and I/O sub classes since the first field 52 * in the "intr" line in /proc/stat is supposed to be the sum of all other 53 * fields. 54 * Since the external and I/O interrupt fields are already sums we would end 55 * up with having a sum which accounts each interrupt twice. 56 */ 57 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { 58 {.irq = EXT_INTERRUPT, .name = "EXT"}, 59 {.irq = IO_INTERRUPT, .name = "I/O"}, 60 {.irq = THIN_INTERRUPT, .name = "AIO"}, 61 }; 62 63 /* 64 * The list of split external and I/O interrupts that appear only in 65 * /proc/interrupts. 66 * In addition this list contains non external / I/O events like NMIs. 67 */ 68 static const struct irq_class irqclass_sub_desc[] = { 69 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"}, 70 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"}, 71 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"}, 72 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"}, 73 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"}, 74 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, 75 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"}, 76 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"}, 77 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"}, 78 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"}, 79 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, 80 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, 81 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"}, 82 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"}, 83 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, 84 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"}, 85 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"}, 86 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"}, 87 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"}, 88 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"}, 89 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"}, 90 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"}, 91 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"}, 92 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, 93 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"}, 94 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"}, 95 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"}, 96 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"}, 97 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"}, 98 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"}, 99 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"}, 100 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"}, 101 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"}, 102 }; 103 104 static void do_IRQ(struct pt_regs *regs, int irq) 105 { 106 if (tod_after_eq(get_lowcore()->int_clock, 107 get_lowcore()->clock_comparator)) 108 /* Serve timer interrupts first. */ 109 clock_comparator_work(); 110 generic_handle_irq(irq); 111 } 112 113 static int on_async_stack(void) 114 { 115 unsigned long frame = current_frame_address(); 116 117 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0; 118 } 119 120 static void do_irq_async(struct pt_regs *regs, int irq) 121 { 122 if (on_async_stack()) { 123 do_IRQ(regs, irq); 124 } else { 125 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ, 126 struct pt_regs *, regs, int, irq); 127 } 128 } 129 130 static int irq_pending(struct pt_regs *regs) 131 { 132 int cc; 133 134 asm volatile( 135 " tpi 0\n" 136 CC_IPM(cc) 137 : CC_OUT(cc, cc) 138 : 139 : CC_CLOBBER); 140 return CC_TRANSFORM(cc); 141 } 142 143 void noinstr do_io_irq(struct pt_regs *regs) 144 { 145 irqentry_state_t state = irqentry_enter(regs); 146 struct pt_regs *old_regs = set_irq_regs(regs); 147 bool from_idle; 148 149 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 150 if (from_idle) { 151 update_timer_idle(); 152 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 153 } 154 155 irq_enter_rcu(); 156 157 if (user_mode(regs)) { 158 update_timer_sys(); 159 if (cpu_has_bear()) 160 current->thread.last_break = regs->last_break; 161 } 162 163 if (from_idle) 164 account_idle_time_irq(); 165 166 set_cpu_flag(CIF_NOHZ_DELAY); 167 do { 168 regs->tpi_info = get_lowcore()->tpi_info; 169 if (get_lowcore()->tpi_info.adapter_IO) 170 do_irq_async(regs, THIN_INTERRUPT); 171 else 172 do_irq_async(regs, IO_INTERRUPT); 173 } while (machine_is_lpar() && irq_pending(regs)); 174 175 irq_exit_rcu(); 176 177 set_irq_regs(old_regs); 178 irqentry_exit(regs, state); 179 } 180 181 void noinstr do_ext_irq(struct pt_regs *regs) 182 { 183 irqentry_state_t state = irqentry_enter(regs); 184 struct pt_regs *old_regs = set_irq_regs(regs); 185 bool from_idle; 186 187 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT); 188 if (from_idle) { 189 update_timer_idle(); 190 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT); 191 } 192 193 irq_enter_rcu(); 194 195 if (user_mode(regs)) { 196 update_timer_sys(); 197 if (cpu_has_bear()) 198 current->thread.last_break = regs->last_break; 199 } 200 201 regs->int_code = get_lowcore()->ext_int_code_addr; 202 regs->int_parm = get_lowcore()->ext_params; 203 regs->int_parm_long = get_lowcore()->ext_params2; 204 205 if (from_idle) 206 account_idle_time_irq(); 207 208 do_irq_async(regs, EXT_INTERRUPT); 209 210 irq_exit_rcu(); 211 set_irq_regs(old_regs); 212 irqentry_exit(regs, state); 213 } 214 215 static void show_msi_interrupt(struct seq_file *p, int irq) 216 { 217 struct irq_desc *desc; 218 unsigned long flags; 219 int cpu; 220 221 rcu_read_lock(); 222 desc = irq_to_desc(irq); 223 if (!desc) 224 goto out; 225 226 raw_spin_lock_irqsave(&desc->lock, flags); 227 seq_printf(p, "%3d: ", irq); 228 for_each_online_cpu(cpu) 229 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu)); 230 231 if (desc->irq_data.chip) 232 seq_printf(p, " %8s", desc->irq_data.chip->name); 233 234 if (desc->action) 235 seq_printf(p, " %s", desc->action->name); 236 237 seq_putc(p, '\n'); 238 raw_spin_unlock_irqrestore(&desc->lock, flags); 239 out: 240 rcu_read_unlock(); 241 } 242 243 /* 244 * show_interrupts is needed by /proc/interrupts. 245 */ 246 int show_interrupts(struct seq_file *p, void *v) 247 { 248 int index = *(loff_t *) v; 249 int cpu, irq; 250 251 cpus_read_lock(); 252 if (index == 0) { 253 seq_puts(p, " "); 254 for_each_online_cpu(cpu) 255 seq_printf(p, "CPU%-8d", cpu); 256 seq_putc(p, '\n'); 257 } 258 if (index < NR_IRQS_BASE) { 259 seq_printf(p, "%s: ", irqclass_main_desc[index].name); 260 irq = irqclass_main_desc[index].irq; 261 for_each_online_cpu(cpu) 262 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); 263 seq_putc(p, '\n'); 264 goto out; 265 } 266 if (index < irq_get_nr_irqs()) { 267 show_msi_interrupt(p, index); 268 goto out; 269 } 270 for (index = 0; index < NR_ARCH_IRQS; index++) { 271 seq_printf(p, "%s: ", irqclass_sub_desc[index].name); 272 irq = irqclass_sub_desc[index].irq; 273 for_each_online_cpu(cpu) 274 seq_printf(p, "%10u ", 275 per_cpu(irq_stat, cpu).irqs[irq]); 276 if (irqclass_sub_desc[index].desc) 277 seq_printf(p, " %s", irqclass_sub_desc[index].desc); 278 seq_putc(p, '\n'); 279 } 280 out: 281 cpus_read_unlock(); 282 return 0; 283 } 284 285 unsigned int arch_dynirq_lower_bound(unsigned int from) 286 { 287 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from; 288 } 289 290 /* 291 * ext_int_hash[index] is the list head for all external interrupts that hash 292 * to this index. 293 */ 294 static struct hlist_head ext_int_hash[32] ____cacheline_aligned; 295 296 struct ext_int_info { 297 ext_int_handler_t handler; 298 struct hlist_node entry; 299 struct rcu_head rcu; 300 u16 code; 301 }; 302 303 /* ext_int_hash_lock protects the handler lists for external interrupts */ 304 static DEFINE_SPINLOCK(ext_int_hash_lock); 305 306 static inline int ext_hash(u16 code) 307 { 308 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); 309 310 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); 311 } 312 313 int register_external_irq(u16 code, ext_int_handler_t handler) 314 { 315 struct ext_int_info *p; 316 unsigned long flags; 317 int index; 318 319 p = kmalloc_obj(*p, GFP_ATOMIC); 320 if (!p) 321 return -ENOMEM; 322 p->code = code; 323 p->handler = handler; 324 index = ext_hash(code); 325 326 spin_lock_irqsave(&ext_int_hash_lock, flags); 327 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); 328 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 329 return 0; 330 } 331 EXPORT_SYMBOL(register_external_irq); 332 333 int unregister_external_irq(u16 code, ext_int_handler_t handler) 334 { 335 struct ext_int_info *p; 336 unsigned long flags; 337 int index = ext_hash(code); 338 339 spin_lock_irqsave(&ext_int_hash_lock, flags); 340 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 341 if (p->code == code && p->handler == handler) { 342 hlist_del_rcu(&p->entry); 343 kfree_rcu(p, rcu); 344 } 345 } 346 spin_unlock_irqrestore(&ext_int_hash_lock, flags); 347 return 0; 348 } 349 EXPORT_SYMBOL(unregister_external_irq); 350 351 static irqreturn_t do_ext_interrupt(int irq, void *dummy) 352 { 353 struct pt_regs *regs = get_irq_regs(); 354 struct ext_code ext_code; 355 struct ext_int_info *p; 356 int index; 357 358 ext_code.int_code = regs->int_code; 359 if (ext_code.code != EXT_IRQ_CLK_COMP) 360 set_cpu_flag(CIF_NOHZ_DELAY); 361 362 index = ext_hash(ext_code.code); 363 rcu_read_lock(); 364 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { 365 if (unlikely(p->code != ext_code.code)) 366 continue; 367 p->handler(ext_code, regs->int_parm, regs->int_parm_long); 368 } 369 rcu_read_unlock(); 370 return IRQ_HANDLED; 371 } 372 373 static void __init init_ext_interrupts(void) 374 { 375 int idx; 376 377 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) 378 INIT_HLIST_HEAD(&ext_int_hash[idx]); 379 380 irq_set_chip_and_handler(EXT_INTERRUPT, 381 &dummy_irq_chip, handle_percpu_irq); 382 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL)) 383 panic("Failed to register EXT interrupt\n"); 384 } 385 386 void __init init_IRQ(void) 387 { 388 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS); 389 init_cio_interrupts(); 390 init_airq_interrupts(); 391 init_ext_interrupts(); 392 } 393 394 static DEFINE_SPINLOCK(irq_subclass_lock); 395 static unsigned char irq_subclass_refcount[64]; 396 397 void irq_subclass_register(enum irq_subclass subclass) 398 { 399 spin_lock(&irq_subclass_lock); 400 if (!irq_subclass_refcount[subclass]) 401 system_ctl_set_bit(0, subclass); 402 irq_subclass_refcount[subclass]++; 403 spin_unlock(&irq_subclass_lock); 404 } 405 EXPORT_SYMBOL(irq_subclass_register); 406 407 void irq_subclass_unregister(enum irq_subclass subclass) 408 { 409 spin_lock(&irq_subclass_lock); 410 irq_subclass_refcount[subclass]--; 411 if (!irq_subclass_refcount[subclass]) 412 system_ctl_clear_bit(0, subclass); 413 spin_unlock(&irq_subclass_lock); 414 } 415 EXPORT_SYMBOL(irq_subclass_unregister); 416