1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * S390 low-level entry points. 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 7 * Hartmut Penner (hp@de.ibm.com), 8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), 9 */ 10 11#include <linux/export.h> 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/asm-extable.h> 15#include <asm/alternative.h> 16#include <asm/processor.h> 17#include <asm/cache.h> 18#include <asm/dwarf.h> 19#include <asm/errno.h> 20#include <asm/ptrace.h> 21#include <asm/thread_info.h> 22#include <asm/asm-offsets.h> 23#include <asm/unistd.h> 24#include <asm/page.h> 25#include <asm/sigp.h> 26#include <asm/irq.h> 27#include <asm/fpu-insn.h> 28#include <asm/setup.h> 29#include <asm/nmi.h> 30#include <asm/nospec-insn.h> 31#include <asm/lowcore.h> 32#include <asm/machine.h> 33 34_LPP_OFFSET = __LC_LPP 35 36 .macro STBEAR address 37 ALTERNATIVE "nop", ".insn s,0xb2010000,\address", ALT_FACILITY(193) 38 .endm 39 40 .macro LBEAR address 41 ALTERNATIVE "nop", ".insn s,0xb2000000,\address", ALT_FACILITY(193) 42 .endm 43 44 .macro LPSWEY address, lpswe 45 ALTERNATIVE_2 "b \lpswe;nopr", \ 46 ".insn siy,0xeb0000000071,\address,0", ALT_FACILITY(193), \ 47 __stringify(.insn siy,0xeb0000000071,LOWCORE_ALT_ADDRESS+\address,0), \ 48 ALT_FEATURE(MFEATURE_LOWCORE) 49 .endm 50 51 .macro MBEAR reg, lowcore 52 ALTERNATIVE "brcl 0,0", __stringify(mvc __PT_LAST_BREAK(8,\reg),__LC_LAST_BREAK(\lowcore)),\ 53 ALT_FACILITY(193) 54 .endm 55 56 .macro CHECK_VMAP_STACK savearea, lowcore, oklabel 57 lgr %r14,%r15 58 nill %r14,0x10000 - THREAD_SIZE 59 oill %r14,STACK_INIT_OFFSET 60 clg %r14,__LC_KERNEL_STACK(\lowcore) 61 je \oklabel 62 clg %r14,__LC_ASYNC_STACK(\lowcore) 63 je \oklabel 64 clg %r14,__LC_MCCK_STACK(\lowcore) 65 je \oklabel 66 clg %r14,__LC_NODAT_STACK(\lowcore) 67 je \oklabel 68 clg %r14,__LC_RESTART_STACK(\lowcore) 69 je \oklabel 70 la %r14,\savearea(\lowcore) 71 j stack_invalid 72 .endm 73 74 /* 75 * The TSTMSK macro generates a test-under-mask instruction by 76 * calculating the memory offset for the specified mask value. 77 * Mask value can be any constant. The macro shifts the mask 78 * value to calculate the memory offset for the test-under-mask 79 * instruction. 80 */ 81 .macro TSTMSK addr, mask, size=8, bytepos=0 82 .if (\bytepos < \size) && (\mask >> 8) 83 .if (\mask & 0xff) 84 .error "Mask exceeds byte boundary" 85 .endif 86 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)" 87 .exitm 88 .endif 89 .ifeq \mask 90 .error "Mask must not be zero" 91 .endif 92 off = \size - \bytepos - 1 93 tm off+\addr, \mask 94 .endm 95 96 .macro BPOFF 97 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,12,0", ALT_SPEC(82) 98 .endm 99 100 .macro BPON 101 ALTERNATIVE "nop", ".insn rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82) 102 .endm 103 104 .macro BPENTER tif_ptr,tif_mask 105 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .insn rrf,0xb2e80000,0,0,13,0", \ 106 "j .+12; nop; nop", ALT_SPEC(82) 107 .endm 108 109 .macro BPEXIT tif_ptr,tif_mask 110 TSTMSK \tif_ptr,\tif_mask 111 ALTERNATIVE "jz .+8; .insn rrf,0xb2e80000,0,0,12,0", \ 112 "jnz .+8; .insn rrf,0xb2e80000,0,0,13,0", ALT_SPEC(82) 113 .endm 114 115#if IS_ENABLED(CONFIG_KVM) 116 .macro SIEEXIT sie_control,lowcore 117 lg %r9,\sie_control # get control block pointer 118 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE 119 lctlg %c1,%c1,__LC_USER_ASCE(\lowcore) # load primary asce 120 lg %r9,__LC_CURRENT(\lowcore) 121 mvi __TI_sie(%r9),0 122 larl %r9,sie_exit # skip forward to sie_exit 123 .endm 124#endif 125 126 .macro STACKLEAK_ERASE 127#ifdef CONFIG_KSTACK_ERASE 128 brasl %r14,stackleak_erase_on_task_stack 129#endif 130 .endm 131 132 GEN_BR_THUNK %r14 133 134 .section .kprobes.text, "ax" 135.Ldummy: 136 /* 137 * The following nop exists only in order to avoid that the next 138 * symbol starts at the beginning of the kprobes text section. 139 * In that case there would be several symbols at the same address. 140 * E.g. objdump would take an arbitrary symbol when disassembling 141 * the code. 142 * With the added nop in between this cannot happen. 143 */ 144 nop 0 145 146/* 147 * Scheduler resume function, called by __switch_to 148 * gpr2 = (task_struct *)prev 149 * gpr3 = (task_struct *)next 150 * Returns: 151 * gpr2 = prev 152 */ 153SYM_FUNC_START(__switch_to_asm) 154 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task 155 lghi %r4,__TASK_stack 156 lghi %r1,__TASK_thread 157 llill %r5,STACK_INIT_OFFSET 158 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev 159 lg %r15,0(%r4,%r3) # start of kernel stack of next 160 agr %r15,%r5 # end of kernel stack of next 161 GET_LC %r13 162 stg %r3,__LC_CURRENT(%r13) # store task struct of next 163 stg %r15,__LC_KERNEL_STACK(%r13) # store end of kernel stack 164 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next 165 lay %r4,__TASK_pid(%r3) 166 mvc __LC_CURRENT_PID(4,%r13),0(%r4) # store pid of next 167 ALTERNATIVE "nop", "lpp _LPP_OFFSET(%r13)", ALT_FACILITY(40) 168#ifdef CONFIG_STACKPROTECTOR 169 lg %r3,__TASK_stack_canary(%r3) 170 stg %r3,__LC_STACK_CANARY(%r13) 171#endif 172 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task 173 BR_EX %r14 174SYM_FUNC_END(__switch_to_asm) 175 176#if IS_ENABLED(CONFIG_KVM) 177/* 178 * __sie64a calling convention: 179 * %r2 pointer to sie control block phys 180 * %r3 pointer to sie control block virt 181 * %r4 guest register save area 182 * %r5 guest asce 183 */ 184SYM_FUNC_START(__sie64a) 185 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers 186 GET_LC %r13 187 lg %r14,__LC_CURRENT(%r13) 188 stg %r2,__SF_SIE_CONTROL_PHYS(%r15) # save sie block physical.. 189 stg %r3,__SF_SIE_CONTROL(%r15) # ...and virtual addresses 190 stg %r4,__SF_SIE_SAVEAREA(%r15) # save guest register save area 191 stg %r5,__SF_SIE_GUEST_ASCE(%r15) # save guest asce 192 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0 193 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r14) # copy thread flags 194 lmg %r0,%r13,0(%r4) # load guest gprs 0-13 195 mvi __TI_sie(%r14),1 196 lctlg %c1,%c1,__SF_SIE_GUEST_ASCE(%r15) # load primary asce 197 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer 198 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now 199 tm __SIE_PROG20+3(%r14),3 # last exit... 200 jnz .Lsie_skip 201 lg %r14,__SF_SIE_CONTROL_PHYS(%r15) # get sie block phys addr 202 BPEXIT __SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST 203.Lsie_entry: 204 sie 0(%r14) 205# Let the next instruction be NOP to avoid triggering a machine check 206# and handling it in a guest as result of the instruction execution. 207 nopr 7 208.Lsie_leave: 209 BPOFF 210 BPENTER __SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST 211.Lsie_skip: 212 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer 213 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE 214 GET_LC %r14 215 lctlg %c1,%c1,__LC_USER_ASCE(%r14) # load primary asce 216 lg %r14,__LC_CURRENT(%r14) 217 mvi __TI_sie(%r14),0 218SYM_INNER_LABEL(sie_exit, SYM_L_GLOBAL) 219 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area 220 stmg %r0,%r13,0(%r14) # save guest gprs 0-13 221 xgr %r0,%r0 # clear guest registers to 222 xgr %r1,%r1 # prevent speculative use 223 xgr %r3,%r3 224 xgr %r4,%r4 225 xgr %r5,%r5 226 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers 227 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code 228 BR_EX %r14 229SYM_FUNC_END(__sie64a) 230EXPORT_SYMBOL(__sie64a) 231EXPORT_SYMBOL(sie_exit) 232#endif 233 234/* 235 * SVC interrupt handler routine. System calls are synchronous events and 236 * are entered with interrupts disabled. 237 */ 238 239SYM_CODE_START(system_call) 240 STMG_LC %r8,%r15,__LC_SAVE_AREA 241 GET_LC %r13 242 stpt __LC_SYS_ENTER_TIMER(%r13) 243 BPOFF 244 lghi %r14,0 245.Lsysc_per: 246 STBEAR __LC_LAST_BREAK(%r13) 247 lg %r15,__LC_KERNEL_STACK(%r13) 248 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 249 stmg %r0,%r7,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 250 # clear user controlled register to prevent speculative use 251 xgr %r0,%r0 252 xgr %r1,%r1 253 xgr %r4,%r4 254 xgr %r5,%r5 255 xgr %r6,%r6 256 xgr %r7,%r7 257 xgr %r8,%r8 258 xgr %r9,%r9 259 xgr %r10,%r10 260 xgr %r11,%r11 261 la %r2,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs 262 mvc __PT_R8(64,%r2),__LC_SAVE_AREA(%r13) 263 MBEAR %r2,%r13 264 lgr %r3,%r14 265 brasl %r14,__do_syscall 266 STACKLEAK_ERASE 267 mvc __LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15) 268 BPON 269 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15) 270 stpt __LC_EXIT_TIMER(%r13) 271 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 272 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE 273SYM_CODE_END(system_call) 274 275# 276# a new process exits the kernel with ret_from_fork 277# 278SYM_CODE_START(ret_from_fork) 279 lgr %r3,%r11 280 brasl %r14,__ret_from_fork 281 STACKLEAK_ERASE 282 GET_LC %r13 283 mvc __LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15) 284 BPON 285 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15) 286 stpt __LC_EXIT_TIMER(%r13) 287 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 288 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE 289SYM_CODE_END(ret_from_fork) 290 291/* 292 * Program check handler routine 293 */ 294 295SYM_CODE_START(pgm_check_handler) 296 STMG_LC %r8,%r15,__LC_SAVE_AREA 297 GET_LC %r13 298 stpt __LC_SYS_ENTER_TIMER(%r13) 299 BPOFF 300 lmg %r8,%r9,__LC_PGM_OLD_PSW(%r13) 301 xgr %r10,%r10 302 tmhh %r8,0x0001 # coming from user space? 303 jo 3f # -> fault in user space 304#if IS_ENABLED(CONFIG_KVM) 305 lg %r11,__LC_CURRENT(%r13) 306 tm __TI_sie(%r11),0xff 307 jz 1f 308 BPENTER __SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST 309 SIEEXIT __SF_SIE_CONTROL(%r15),%r13 310 lghi %r10,_PIF_GUEST_FAULT 311#endif 3121: tmhh %r8,0x4000 # PER bit set in old PSW ? 313 jnz 2f # -> enabled, can't be a double fault 314 tm __LC_PGM_ILC+3(%r13),0x80 # check for per exception 315 jnz .Lpgm_svcper # -> single stepped svc 3162: aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) 317 # CHECK_VMAP_STACK branches to stack_invalid or 4f 318 CHECK_VMAP_STACK __LC_SAVE_AREA,%r13,4f 3193: lg %r15,__LC_KERNEL_STACK(%r13) 3204: la %r11,STACK_FRAME_OVERHEAD(%r15) 321 stg %r10,__PT_FLAGS(%r11) 322 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 323 stmg %r0,%r7,__PT_R0(%r11) 324 mvc __PT_R8(64,%r11),__LC_SAVE_AREA(%r13) 325 mvc __PT_LAST_BREAK(8,%r11),__LC_PGM_LAST_BREAK(%r13) 326 stmg %r8,%r9,__PT_PSW(%r11) 327 # clear user controlled registers to prevent speculative use 328 xgr %r0,%r0 329 xgr %r1,%r1 330 xgr %r3,%r3 331 xgr %r4,%r4 332 xgr %r5,%r5 333 xgr %r6,%r6 334 xgr %r7,%r7 335 xgr %r12,%r12 336 lgr %r2,%r11 337 brasl %r14,__do_pgm_check 338 tmhh %r8,0x0001 # returning to user space? 339 jno .Lpgm_exit_kernel 340 STACKLEAK_ERASE 341 BPON 342 stpt __LC_EXIT_TIMER(%r13) 343.Lpgm_exit_kernel: 344 mvc __LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15) 345 LBEAR STACK_FRAME_OVERHEAD+__PT_LAST_BREAK(%r15) 346 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 347 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE 348 349# 350# single stepped system call 351# 352.Lpgm_svcper: 353 mvc __LC_RETURN_PSW(8,%r13),__LC_SVC_NEW_PSW(%r13) 354 larl %r14,.Lsysc_per 355 stg %r14,__LC_RETURN_PSW+8(%r13) 356 lghi %r14,1 357 LBEAR __LC_PGM_LAST_BREAK(%r13) 358 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE # branch to .Lsysc_per 359SYM_CODE_END(pgm_check_handler) 360 361/* 362 * Interrupt handler macro used for external and IO interrupts. 363 */ 364.macro INT_HANDLER name,lc_old_psw,handler 365SYM_CODE_START(\name) 366 STMG_LC %r8,%r15,__LC_SAVE_AREA 367 GET_LC %r13 368 stckf __LC_INT_CLOCK(%r13) 369 stpt __LC_SYS_ENTER_TIMER(%r13) 370 STBEAR __LC_LAST_BREAK(%r13) 371 BPOFF 372 lmg %r8,%r9,\lc_old_psw(%r13) 373 tmhh %r8,0x0001 # interrupting from user ? 374 jnz 1f 375#if IS_ENABLED(CONFIG_KVM) 376 lg %r10,__LC_CURRENT(%r13) 377 tm __TI_sie(%r10),0xff 378 jz 0f 379 BPENTER __SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST 380 SIEEXIT __SF_SIE_CONTROL(%r15),%r13 381#endif 3820: aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE) 383 j 2f 3841: lg %r15,__LC_KERNEL_STACK(%r13) 3852: xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 386 la %r11,STACK_FRAME_OVERHEAD(%r15) 387 stmg %r0,%r7,__PT_R0(%r11) 388 # clear user controlled registers to prevent speculative use 389 xgr %r0,%r0 390 xgr %r1,%r1 391 xgr %r3,%r3 392 xgr %r4,%r4 393 xgr %r5,%r5 394 xgr %r6,%r6 395 xgr %r7,%r7 396 xgr %r10,%r10 397 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) 398 mvc __PT_R8(64,%r11),__LC_SAVE_AREA(%r13) 399 MBEAR %r11,%r13 400 stmg %r8,%r9,__PT_PSW(%r11) 401 lgr %r2,%r11 # pass pointer to pt_regs 402 brasl %r14,\handler 403 mvc __LC_RETURN_PSW(16,%r13),__PT_PSW(%r11) 404 tmhh %r8,0x0001 # returning to user ? 405 jno 2f 406 STACKLEAK_ERASE 407 BPON 408 stpt __LC_EXIT_TIMER(%r13) 4092: LBEAR __PT_LAST_BREAK(%r11) 410 lmg %r0,%r15,__PT_R0(%r11) 411 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE 412SYM_CODE_END(\name) 413.endm 414 415 .section .irqentry.text, "ax" 416 417INT_HANDLER ext_int_handler,__LC_EXT_OLD_PSW,do_ext_irq 418INT_HANDLER io_int_handler,__LC_IO_OLD_PSW,do_io_irq 419 420 .section .kprobes.text, "ax" 421 422/* 423 * Machine check handler routines 424 */ 425SYM_CODE_START(mcck_int_handler) 426 BPOFF 427 GET_LC %r13 428 lmg %r8,%r9,__LC_MCK_OLD_PSW(%r13) 429 TSTMSK __LC_MCCK_CODE(%r13),MCCK_CODE_SYSTEM_DAMAGE 430 jo .Lmcck_panic # yes -> rest of mcck code invalid 431 TSTMSK __LC_MCCK_CODE(%r13),MCCK_CODE_CR_VALID 432 jno .Lmcck_panic # control registers invalid -> panic 433 ptlb 434 lay %r14,__LC_CPU_TIMER_SAVE_AREA(%r13) 435 mvc __LC_MCCK_ENTER_TIMER(8,%r13),0(%r14) 436 TSTMSK __LC_MCCK_CODE(%r13),MCCK_CODE_CPU_TIMER_VALID 437 jo 3f 438 la %r14,__LC_SYS_ENTER_TIMER(%r13) 439 clc 0(8,%r14),__LC_EXIT_TIMER(%r13) 440 jl 1f 441 la %r14,__LC_EXIT_TIMER(%r13) 4421: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER(%r13) 443 jl 2f 444 la %r14,__LC_LAST_UPDATE_TIMER(%r13) 4452: spt 0(%r14) 446 mvc __LC_MCCK_ENTER_TIMER(8,%r13),0(%r14) 4473: TSTMSK __LC_MCCK_CODE(%r13),MCCK_CODE_PSW_MWP_VALID 448 jno .Lmcck_panic 449 tmhh %r8,0x0001 # interrupting from user ? 450 jnz .Lmcck_user 451 TSTMSK __LC_MCCK_CODE(%r13),MCCK_CODE_PSW_IA_VALID 452 jno .Lmcck_panic 453#if IS_ENABLED(CONFIG_KVM) 454 lg %r10,__LC_CURRENT(%r13) 455 tm __TI_sie(%r10),0xff 456 jz .Lmcck_user 457 # Need to compare the address instead of __TI_SIE flag. 458 # Otherwise there would be a race between setting the flag 459 # and entering SIE (or leaving and clearing the flag). This 460 # would cause machine checks targeted at the guest to be 461 # handled by the host. 462 larl %r14,.Lsie_entry 463 clgrjl %r9,%r14, 4f 464 larl %r14,.Lsie_leave 465 clgrjhe %r9,%r14, 4f 466 lg %r10,__LC_PCPU(%r13) 467 oi __PCPU_FLAGS+7(%r10), _CIF_MCCK_GUEST 4684: BPENTER __SF_SIE_FLAGS(%r15),_TIF_ISOLATE_BP_GUEST 469 SIEEXIT __SF_SIE_CONTROL(%r15),%r13 470#endif 471.Lmcck_user: 472 lg %r15,__LC_MCCK_STACK(%r13) 473 la %r11,STACK_FRAME_OVERHEAD(%r15) 474 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 475 lay %r14,__LC_GPREGS_SAVE_AREA(%r13) 476 mvc __PT_R0(128,%r11),0(%r14) 477 # clear user controlled registers to prevent speculative use 478 xgr %r0,%r0 479 xgr %r1,%r1 480 xgr %r3,%r3 481 xgr %r4,%r4 482 xgr %r5,%r5 483 xgr %r6,%r6 484 xgr %r7,%r7 485 xgr %r10,%r10 486 stmg %r8,%r9,__PT_PSW(%r11) 487 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11) 488 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 489 lgr %r2,%r11 # pass pointer to pt_regs 490 brasl %r14,s390_do_machine_check 491 lmg %r0,%r10,__PT_R0(%r11) 492 mvc __LC_RETURN_MCCK_PSW(16,%r13),__PT_PSW(%r11) # move return PSW 493 tm __LC_RETURN_MCCK_PSW+1(%r13),0x01 # returning to user ? 494 jno 0f 495 BPON 496 stpt __LC_EXIT_TIMER(%r13) 4970: ALTERNATIVE "brcl 0,0", __stringify(lay %r12,__LC_LAST_BREAK_SAVE_AREA(%r13)),\ 498 ALT_FACILITY(193) 499 LBEAR 0(%r12) 500 lmg %r11,%r15,__PT_R11(%r11) 501 LPSWEY __LC_RETURN_MCCK_PSW,__LC_RETURN_MCCK_LPSWE 502 503.Lmcck_panic: 504 /* 505 * Iterate over all possible CPU addresses in the range 0..0xffff 506 * and stop each CPU using signal processor. Use compare and swap 507 * to allow just one CPU-stopper and prevent concurrent CPUs from 508 * stopping each other while leaving the others running. 509 */ 510 lhi %r5,0 511 lhi %r6,1 512 larl %r7,stop_lock 513 cs %r5,%r6,0(%r7) # single CPU-stopper only 514 jnz 4f 515 larl %r7,this_cpu 516 stap 0(%r7) # this CPU address 517 lh %r4,0(%r7) 518 nilh %r4,0 519 lhi %r0,1 520 sll %r0,16 # CPU counter 521 lhi %r3,0 # next CPU address 5220: cr %r3,%r4 523 je 2f 5241: sigp %r1,%r3,SIGP_STOP # stop next CPU 525 brc SIGP_CC_BUSY,1b 5262: ahi %r3,1 527 brct %r0,0b 5283: sigp %r1,%r4,SIGP_STOP # stop this CPU 529 brc SIGP_CC_BUSY,3b 5304: j 4b 531SYM_CODE_END(mcck_int_handler) 532 533SYM_CODE_START(restart_int_handler) 534 ALTERNATIVE "nop", "lpp _LPP_OFFSET", ALT_FACILITY(40) 535 stg %r15,__LC_SAVE_AREA_RESTART 536 TSTMSK __LC_RESTART_FLAGS,RESTART_FLAG_CTLREGS,4 537 jz 0f 538 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA 5390: larl %r15,daton_psw 540 lpswe 0(%r15) # turn dat on, keep irqs off 541.Ldaton: 542 GET_LC %r15 543 lg %r15,__LC_RESTART_STACK(%r15) 544 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15) 545 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 546 GET_LC %r13 547 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART(%r13) 548 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW(%r13) 549 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15) 550 lg %r1,__LC_RESTART_FN(%r13) # load fn, parm & source cpu 551 lg %r2,__LC_RESTART_DATA(%r13) 552 lgf %r3,__LC_RESTART_SOURCE(%r13) 553 ltgr %r3,%r3 # test source cpu address 554 jm 1f # negative -> skip source stop 5550: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu 556 brc 10,0b # wait for status stored 5571: basr %r14,%r1 # call function 558 stap __SF_EMPTY(%r15) # store cpu address 559 llgh %r3,__SF_EMPTY(%r15) 5602: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu 561 brc 2,2b 5623: j 3b 563SYM_CODE_END(restart_int_handler) 564 565 __INIT 566SYM_CODE_START(early_pgm_check_handler) 567 STMG_LC %r8,%r15,__LC_SAVE_AREA 568 GET_LC %r13 569 aghi %r15,-(STACK_FRAME_OVERHEAD+__PT_SIZE) 570 la %r11,STACK_FRAME_OVERHEAD(%r15) 571 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 572 stmg %r0,%r7,__PT_R0(%r11) 573 mvc __PT_PSW(16,%r11),__LC_PGM_OLD_PSW(%r13) 574 mvc __PT_R8(64,%r11),__LC_SAVE_AREA(%r13) 575 lgr %r2,%r11 576 brasl %r14,__do_early_pgm_check 577 mvc __LC_RETURN_PSW(16,%r13),STACK_FRAME_OVERHEAD+__PT_PSW(%r15) 578 lmg %r0,%r15,STACK_FRAME_OVERHEAD+__PT_R0(%r15) 579 LPSWEY __LC_RETURN_PSW,__LC_RETURN_LPSWE 580SYM_CODE_END(early_pgm_check_handler) 581 __FINIT 582 583 .section .kprobes.text, "ax" 584 585/* 586 * The synchronous or the asynchronous stack pointer is invalid. We are dead. 587 * No need to properly save the registers, we are going to panic anyway. 588 * Setup a pt_regs so that show_trace can provide a good call trace. 589 */ 590SYM_CODE_START(stack_invalid) 591 GET_LC %r15 592 lg %r15,__LC_NODAT_STACK(%r15) # change to panic stack 593 la %r11,STACK_FRAME_OVERHEAD(%r15) 594 stmg %r0,%r7,__PT_R0(%r11) 595 stmg %r8,%r9,__PT_PSW(%r11) 596 mvc __PT_R8(64,%r11),0(%r14) 597 GET_LC %r2 598 mvc __PT_ORIG_GPR2(8,%r11),__LC_PGM_LAST_BREAK(%r2) 599 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) 600 lgr %r2,%r11 # pass pointer to pt_regs 601 jg kernel_stack_invalid 602SYM_CODE_END(stack_invalid) 603 604 .section .data, "aw" 605 .balign 4 606SYM_DATA_LOCAL(stop_lock, .long 0) 607SYM_DATA_LOCAL(this_cpu, .short 0) 608 .balign 8 609SYM_DATA_START_LOCAL(daton_psw) 610 .quad PSW_KERNEL_BITS 611 .quad .Ldaton 612SYM_DATA_END(daton_psw) 613