1 /* 2 * arch/s390/kernel/dis.c 3 * 4 * Disassemble s390 instructions. 5 * 6 * Copyright IBM Corp. 2007 7 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 8 */ 9 10 #include <linux/sched.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/errno.h> 14 #include <linux/ptrace.h> 15 #include <linux/timer.h> 16 #include <linux/mm.h> 17 #include <linux/smp.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/module.h> 22 #include <linux/kallsyms.h> 23 #include <linux/reboot.h> 24 #include <linux/kprobes.h> 25 #include <linux/kdebug.h> 26 27 #include <asm/system.h> 28 #include <asm/uaccess.h> 29 #include <asm/io.h> 30 #include <asm/atomic.h> 31 #include <asm/mathemu.h> 32 #include <asm/cpcmd.h> 33 #include <asm/s390_ext.h> 34 #include <asm/lowcore.h> 35 #include <asm/debug.h> 36 37 #ifndef CONFIG_64BIT 38 #define ONELONG "%08lx: " 39 #else /* CONFIG_64BIT */ 40 #define ONELONG "%016lx: " 41 #endif /* CONFIG_64BIT */ 42 43 #define OPERAND_GPR 0x1 /* Operand printed as %rx */ 44 #define OPERAND_FPR 0x2 /* Operand printed as %fx */ 45 #define OPERAND_AR 0x4 /* Operand printed as %ax */ 46 #define OPERAND_CR 0x8 /* Operand printed as %cx */ 47 #define OPERAND_DISP 0x10 /* Operand printed as displacement */ 48 #define OPERAND_BASE 0x20 /* Operand printed as base register */ 49 #define OPERAND_INDEX 0x40 /* Operand printed as index register */ 50 #define OPERAND_PCREL 0x80 /* Operand printed as pc-relative symbol */ 51 #define OPERAND_SIGNED 0x100 /* Operand printed as signed value */ 52 #define OPERAND_LENGTH 0x200 /* Operand printed as length (+1) */ 53 54 enum { 55 UNUSED, /* Indicates the end of the operand list */ 56 R_8, /* GPR starting at position 8 */ 57 R_12, /* GPR starting at position 12 */ 58 R_16, /* GPR starting at position 16 */ 59 R_20, /* GPR starting at position 20 */ 60 R_24, /* GPR starting at position 24 */ 61 R_28, /* GPR starting at position 28 */ 62 R_32, /* GPR starting at position 32 */ 63 F_8, /* FPR starting at position 8 */ 64 F_12, /* FPR starting at position 12 */ 65 F_16, /* FPR starting at position 16 */ 66 F_20, /* FPR starting at position 16 */ 67 F_24, /* FPR starting at position 24 */ 68 F_28, /* FPR starting at position 28 */ 69 F_32, /* FPR starting at position 32 */ 70 A_8, /* Access reg. starting at position 8 */ 71 A_12, /* Access reg. starting at position 12 */ 72 A_24, /* Access reg. starting at position 24 */ 73 A_28, /* Access reg. starting at position 28 */ 74 C_8, /* Control reg. starting at position 8 */ 75 C_12, /* Control reg. starting at position 12 */ 76 B_16, /* Base register starting at position 16 */ 77 B_32, /* Base register starting at position 32 */ 78 X_12, /* Index register starting at position 12 */ 79 D_20, /* Displacement starting at position 20 */ 80 D_36, /* Displacement starting at position 36 */ 81 D20_20, /* 20 bit displacement starting at 20 */ 82 L4_8, /* 4 bit length starting at position 8 */ 83 L4_12, /* 4 bit length starting at position 12 */ 84 L8_8, /* 8 bit length starting at position 8 */ 85 U4_8, /* 4 bit unsigned value starting at 8 */ 86 U4_12, /* 4 bit unsigned value starting at 12 */ 87 U4_16, /* 4 bit unsigned value starting at 16 */ 88 U4_20, /* 4 bit unsigned value starting at 20 */ 89 U4_32, /* 4 bit unsigned value starting at 32 */ 90 U8_8, /* 8 bit unsigned value starting at 8 */ 91 U8_16, /* 8 bit unsigned value starting at 16 */ 92 U8_24, /* 8 bit unsigned value starting at 24 */ 93 U8_32, /* 8 bit unsigned value starting at 32 */ 94 I8_8, /* 8 bit signed value starting at 8 */ 95 I8_32, /* 8 bit signed value starting at 32 */ 96 I16_16, /* 16 bit signed value starting at 16 */ 97 I16_32, /* 32 bit signed value starting at 16 */ 98 U16_16, /* 16 bit unsigned value starting at 16 */ 99 U16_32, /* 32 bit unsigned value starting at 16 */ 100 J16_16, /* PC relative jump offset at 16 */ 101 J32_16, /* PC relative long offset at 16 */ 102 I32_16, /* 32 bit signed value starting at 16 */ 103 U32_16, /* 32 bit unsigned value starting at 16 */ 104 M_16, /* 4 bit optional mask starting at 16 */ 105 RO_28, /* optional GPR starting at position 28 */ 106 }; 107 108 /* 109 * Enumeration of the different instruction formats. 110 * For details consult the principles of operation. 111 */ 112 enum { 113 INSTR_INVALID, 114 INSTR_E, 115 INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, 116 INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, 117 INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, 118 INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, 119 INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 120 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 121 INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, 122 INSTR_RRE_RR, INSTR_RRE_RR_OPT, 123 INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, 124 INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR, 125 INSTR_RRF_R0RR2, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, 126 INSTR_RRF_U0RR, INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU, 127 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 128 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, 129 INSTR_RSI_RRP, 130 INSTR_RSL_R0RD, 131 INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, 132 INSTR_RSY_RDRM, 133 INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, 134 INSTR_RS_RURD, 135 INSTR_RXE_FRRD, INSTR_RXE_RRRD, 136 INSTR_RXF_FRRDF, 137 INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, 138 INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, 139 INSTR_SIL_RDI, INSTR_SIL_RDU, 140 INSTR_SIY_IRD, INSTR_SIY_URD, 141 INSTR_SI_URD, 142 INSTR_SSE_RDRD, 143 INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, 144 INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, 145 INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 146 INSTR_S_00, INSTR_S_RD, 147 }; 148 149 struct operand { 150 int bits; /* The number of bits in the operand. */ 151 int shift; /* The number of bits to shift. */ 152 int flags; /* One bit syntax flags. */ 153 }; 154 155 struct insn { 156 const char name[5]; 157 unsigned char opfrag; 158 unsigned char format; 159 }; 160 161 static const struct operand operands[] = 162 { 163 [UNUSED] = { 0, 0, 0 }, 164 [R_8] = { 4, 8, OPERAND_GPR }, 165 [R_12] = { 4, 12, OPERAND_GPR }, 166 [R_16] = { 4, 16, OPERAND_GPR }, 167 [R_20] = { 4, 20, OPERAND_GPR }, 168 [R_24] = { 4, 24, OPERAND_GPR }, 169 [R_28] = { 4, 28, OPERAND_GPR }, 170 [R_32] = { 4, 32, OPERAND_GPR }, 171 [F_8] = { 4, 8, OPERAND_FPR }, 172 [F_12] = { 4, 12, OPERAND_FPR }, 173 [F_16] = { 4, 16, OPERAND_FPR }, 174 [F_20] = { 4, 16, OPERAND_FPR }, 175 [F_24] = { 4, 24, OPERAND_FPR }, 176 [F_28] = { 4, 28, OPERAND_FPR }, 177 [F_32] = { 4, 32, OPERAND_FPR }, 178 [A_8] = { 4, 8, OPERAND_AR }, 179 [A_12] = { 4, 12, OPERAND_AR }, 180 [A_24] = { 4, 24, OPERAND_AR }, 181 [A_28] = { 4, 28, OPERAND_AR }, 182 [C_8] = { 4, 8, OPERAND_CR }, 183 [C_12] = { 4, 12, OPERAND_CR }, 184 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 185 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 186 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 187 [D_20] = { 12, 20, OPERAND_DISP }, 188 [D_36] = { 12, 36, OPERAND_DISP }, 189 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 190 [L4_8] = { 4, 8, OPERAND_LENGTH }, 191 [L4_12] = { 4, 12, OPERAND_LENGTH }, 192 [L8_8] = { 8, 8, OPERAND_LENGTH }, 193 [U4_8] = { 4, 8, 0 }, 194 [U4_12] = { 4, 12, 0 }, 195 [U4_16] = { 4, 16, 0 }, 196 [U4_20] = { 4, 20, 0 }, 197 [U4_32] = { 4, 32, 0 }, 198 [U8_8] = { 8, 8, 0 }, 199 [U8_16] = { 8, 16, 0 }, 200 [U8_24] = { 8, 24, 0 }, 201 [U8_32] = { 8, 32, 0 }, 202 [I16_16] = { 16, 16, OPERAND_SIGNED }, 203 [U16_16] = { 16, 16, 0 }, 204 [U16_32] = { 16, 32, 0 }, 205 [J16_16] = { 16, 16, OPERAND_PCREL }, 206 [I16_32] = { 16, 32, OPERAND_SIGNED }, 207 [J32_16] = { 32, 16, OPERAND_PCREL }, 208 [I32_16] = { 32, 16, OPERAND_SIGNED }, 209 [U32_16] = { 32, 16, 0 }, 210 [M_16] = { 4, 16, 0 }, 211 [RO_28] = { 4, 28, OPERAND_GPR } 212 }; 213 214 static const unsigned char formats[][7] = { 215 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, 216 [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, 217 [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, 218 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 219 [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, 220 [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, 221 [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, 222 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, 223 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, 224 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, 225 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, 226 [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, 227 [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, 228 [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, 229 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, 230 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, 231 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, 232 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, 233 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, 234 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, 235 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, 236 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, 237 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, 238 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, 239 [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, 240 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, 241 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, 242 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, 243 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, 244 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, 245 [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, 246 [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, 247 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, 248 [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, 249 [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, 250 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, 251 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, 252 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, 253 [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, 254 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, 255 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, 256 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, 257 [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, 258 [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, 259 [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, 260 [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, 261 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, 262 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, 263 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, 264 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, 265 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, 266 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 267 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 268 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 269 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 270 [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, 271 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, 272 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, 273 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, 274 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 275 [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 }, 276 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, 277 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 278 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, 279 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 280 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 281 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 282 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 283 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 284 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, 285 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, 286 [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, 287 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 288 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 289 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, 290 [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, 291 [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, 292 [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, 293 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, 294 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, 295 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, 296 [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 }, 297 [INSTR_SSF_RRDRD2]= { 0x00, R_8,D_20,B_16,D_36,B_32,0 }, 298 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 299 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 300 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 301 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 302 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 303 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 304 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, 305 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, 306 }; 307 308 enum { 309 LONG_INSN_ALGHSIK, 310 LONG_INSN_ALHSIK, 311 LONG_INSN_CLFHSI, 312 LONG_INSN_CLGFRL, 313 LONG_INSN_CLGHRL, 314 LONG_INSN_CLGHSI, 315 LONG_INSN_CLHHSI, 316 LONG_INSN_LLGFRL, 317 LONG_INSN_LLGHRL, 318 LONG_INSN_POPCNT, 319 LONG_INSN_RISBHG, 320 LONG_INSN_RISBLG, 321 }; 322 323 static char *long_insn_name[] = { 324 [LONG_INSN_ALGHSIK] = "alghsik", 325 [LONG_INSN_ALHSIK] = "alhsik", 326 [LONG_INSN_CLFHSI] = "clfhsi", 327 [LONG_INSN_CLGFRL] = "clgfrl", 328 [LONG_INSN_CLGHRL] = "clghrl", 329 [LONG_INSN_CLGHSI] = "clghsi", 330 [LONG_INSN_CLHHSI] = "clhhsi", 331 [LONG_INSN_LLGFRL] = "llgfrl", 332 [LONG_INSN_LLGHRL] = "llghrl", 333 [LONG_INSN_POPCNT] = "popcnt", 334 [LONG_INSN_RISBHG] = "risbhg", 335 [LONG_INSN_RISBLG] = "risblk", 336 }; 337 338 static struct insn opcode[] = { 339 #ifdef CONFIG_64BIT 340 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 341 #endif 342 { "spm", 0x04, INSTR_RR_R0 }, 343 { "balr", 0x05, INSTR_RR_RR }, 344 { "bctr", 0x06, INSTR_RR_RR }, 345 { "bcr", 0x07, INSTR_RR_UR }, 346 { "svc", 0x0a, INSTR_RR_U0 }, 347 { "bsm", 0x0b, INSTR_RR_RR }, 348 { "bassm", 0x0c, INSTR_RR_RR }, 349 { "basr", 0x0d, INSTR_RR_RR }, 350 { "mvcl", 0x0e, INSTR_RR_RR }, 351 { "clcl", 0x0f, INSTR_RR_RR }, 352 { "lpr", 0x10, INSTR_RR_RR }, 353 { "lnr", 0x11, INSTR_RR_RR }, 354 { "ltr", 0x12, INSTR_RR_RR }, 355 { "lcr", 0x13, INSTR_RR_RR }, 356 { "nr", 0x14, INSTR_RR_RR }, 357 { "clr", 0x15, INSTR_RR_RR }, 358 { "or", 0x16, INSTR_RR_RR }, 359 { "xr", 0x17, INSTR_RR_RR }, 360 { "lr", 0x18, INSTR_RR_RR }, 361 { "cr", 0x19, INSTR_RR_RR }, 362 { "ar", 0x1a, INSTR_RR_RR }, 363 { "sr", 0x1b, INSTR_RR_RR }, 364 { "mr", 0x1c, INSTR_RR_RR }, 365 { "dr", 0x1d, INSTR_RR_RR }, 366 { "alr", 0x1e, INSTR_RR_RR }, 367 { "slr", 0x1f, INSTR_RR_RR }, 368 { "lpdr", 0x20, INSTR_RR_FF }, 369 { "lndr", 0x21, INSTR_RR_FF }, 370 { "ltdr", 0x22, INSTR_RR_FF }, 371 { "lcdr", 0x23, INSTR_RR_FF }, 372 { "hdr", 0x24, INSTR_RR_FF }, 373 { "ldxr", 0x25, INSTR_RR_FF }, 374 { "lrdr", 0x25, INSTR_RR_FF }, 375 { "mxr", 0x26, INSTR_RR_FF }, 376 { "mxdr", 0x27, INSTR_RR_FF }, 377 { "ldr", 0x28, INSTR_RR_FF }, 378 { "cdr", 0x29, INSTR_RR_FF }, 379 { "adr", 0x2a, INSTR_RR_FF }, 380 { "sdr", 0x2b, INSTR_RR_FF }, 381 { "mdr", 0x2c, INSTR_RR_FF }, 382 { "ddr", 0x2d, INSTR_RR_FF }, 383 { "awr", 0x2e, INSTR_RR_FF }, 384 { "swr", 0x2f, INSTR_RR_FF }, 385 { "lper", 0x30, INSTR_RR_FF }, 386 { "lner", 0x31, INSTR_RR_FF }, 387 { "lter", 0x32, INSTR_RR_FF }, 388 { "lcer", 0x33, INSTR_RR_FF }, 389 { "her", 0x34, INSTR_RR_FF }, 390 { "ledr", 0x35, INSTR_RR_FF }, 391 { "lrer", 0x35, INSTR_RR_FF }, 392 { "axr", 0x36, INSTR_RR_FF }, 393 { "sxr", 0x37, INSTR_RR_FF }, 394 { "ler", 0x38, INSTR_RR_FF }, 395 { "cer", 0x39, INSTR_RR_FF }, 396 { "aer", 0x3a, INSTR_RR_FF }, 397 { "ser", 0x3b, INSTR_RR_FF }, 398 { "mder", 0x3c, INSTR_RR_FF }, 399 { "mer", 0x3c, INSTR_RR_FF }, 400 { "der", 0x3d, INSTR_RR_FF }, 401 { "aur", 0x3e, INSTR_RR_FF }, 402 { "sur", 0x3f, INSTR_RR_FF }, 403 { "sth", 0x40, INSTR_RX_RRRD }, 404 { "la", 0x41, INSTR_RX_RRRD }, 405 { "stc", 0x42, INSTR_RX_RRRD }, 406 { "ic", 0x43, INSTR_RX_RRRD }, 407 { "ex", 0x44, INSTR_RX_RRRD }, 408 { "bal", 0x45, INSTR_RX_RRRD }, 409 { "bct", 0x46, INSTR_RX_RRRD }, 410 { "bc", 0x47, INSTR_RX_URRD }, 411 { "lh", 0x48, INSTR_RX_RRRD }, 412 { "ch", 0x49, INSTR_RX_RRRD }, 413 { "ah", 0x4a, INSTR_RX_RRRD }, 414 { "sh", 0x4b, INSTR_RX_RRRD }, 415 { "mh", 0x4c, INSTR_RX_RRRD }, 416 { "bas", 0x4d, INSTR_RX_RRRD }, 417 { "cvd", 0x4e, INSTR_RX_RRRD }, 418 { "cvb", 0x4f, INSTR_RX_RRRD }, 419 { "st", 0x50, INSTR_RX_RRRD }, 420 { "lae", 0x51, INSTR_RX_RRRD }, 421 { "n", 0x54, INSTR_RX_RRRD }, 422 { "cl", 0x55, INSTR_RX_RRRD }, 423 { "o", 0x56, INSTR_RX_RRRD }, 424 { "x", 0x57, INSTR_RX_RRRD }, 425 { "l", 0x58, INSTR_RX_RRRD }, 426 { "c", 0x59, INSTR_RX_RRRD }, 427 { "a", 0x5a, INSTR_RX_RRRD }, 428 { "s", 0x5b, INSTR_RX_RRRD }, 429 { "m", 0x5c, INSTR_RX_RRRD }, 430 { "d", 0x5d, INSTR_RX_RRRD }, 431 { "al", 0x5e, INSTR_RX_RRRD }, 432 { "sl", 0x5f, INSTR_RX_RRRD }, 433 { "std", 0x60, INSTR_RX_FRRD }, 434 { "mxd", 0x67, INSTR_RX_FRRD }, 435 { "ld", 0x68, INSTR_RX_FRRD }, 436 { "cd", 0x69, INSTR_RX_FRRD }, 437 { "ad", 0x6a, INSTR_RX_FRRD }, 438 { "sd", 0x6b, INSTR_RX_FRRD }, 439 { "md", 0x6c, INSTR_RX_FRRD }, 440 { "dd", 0x6d, INSTR_RX_FRRD }, 441 { "aw", 0x6e, INSTR_RX_FRRD }, 442 { "sw", 0x6f, INSTR_RX_FRRD }, 443 { "ste", 0x70, INSTR_RX_FRRD }, 444 { "ms", 0x71, INSTR_RX_RRRD }, 445 { "le", 0x78, INSTR_RX_FRRD }, 446 { "ce", 0x79, INSTR_RX_FRRD }, 447 { "ae", 0x7a, INSTR_RX_FRRD }, 448 { "se", 0x7b, INSTR_RX_FRRD }, 449 { "mde", 0x7c, INSTR_RX_FRRD }, 450 { "me", 0x7c, INSTR_RX_FRRD }, 451 { "de", 0x7d, INSTR_RX_FRRD }, 452 { "au", 0x7e, INSTR_RX_FRRD }, 453 { "su", 0x7f, INSTR_RX_FRRD }, 454 { "ssm", 0x80, INSTR_S_RD }, 455 { "lpsw", 0x82, INSTR_S_RD }, 456 { "diag", 0x83, INSTR_RS_RRRD }, 457 { "brxh", 0x84, INSTR_RSI_RRP }, 458 { "brxle", 0x85, INSTR_RSI_RRP }, 459 { "bxh", 0x86, INSTR_RS_RRRD }, 460 { "bxle", 0x87, INSTR_RS_RRRD }, 461 { "srl", 0x88, INSTR_RS_R0RD }, 462 { "sll", 0x89, INSTR_RS_R0RD }, 463 { "sra", 0x8a, INSTR_RS_R0RD }, 464 { "sla", 0x8b, INSTR_RS_R0RD }, 465 { "srdl", 0x8c, INSTR_RS_R0RD }, 466 { "sldl", 0x8d, INSTR_RS_R0RD }, 467 { "srda", 0x8e, INSTR_RS_R0RD }, 468 { "slda", 0x8f, INSTR_RS_R0RD }, 469 { "stm", 0x90, INSTR_RS_RRRD }, 470 { "tm", 0x91, INSTR_SI_URD }, 471 { "mvi", 0x92, INSTR_SI_URD }, 472 { "ts", 0x93, INSTR_S_RD }, 473 { "ni", 0x94, INSTR_SI_URD }, 474 { "cli", 0x95, INSTR_SI_URD }, 475 { "oi", 0x96, INSTR_SI_URD }, 476 { "xi", 0x97, INSTR_SI_URD }, 477 { "lm", 0x98, INSTR_RS_RRRD }, 478 { "trace", 0x99, INSTR_RS_RRRD }, 479 { "lam", 0x9a, INSTR_RS_AARD }, 480 { "stam", 0x9b, INSTR_RS_AARD }, 481 { "mvcle", 0xa8, INSTR_RS_RRRD }, 482 { "clcle", 0xa9, INSTR_RS_RRRD }, 483 { "stnsm", 0xac, INSTR_SI_URD }, 484 { "stosm", 0xad, INSTR_SI_URD }, 485 { "sigp", 0xae, INSTR_RS_RRRD }, 486 { "mc", 0xaf, INSTR_SI_URD }, 487 { "lra", 0xb1, INSTR_RX_RRRD }, 488 { "stctl", 0xb6, INSTR_RS_CCRD }, 489 { "lctl", 0xb7, INSTR_RS_CCRD }, 490 { "cs", 0xba, INSTR_RS_RRRD }, 491 { "cds", 0xbb, INSTR_RS_RRRD }, 492 { "clm", 0xbd, INSTR_RS_RURD }, 493 { "stcm", 0xbe, INSTR_RS_RURD }, 494 { "icm", 0xbf, INSTR_RS_RURD }, 495 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 496 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 497 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 498 { "nc", 0xd4, INSTR_SS_L0RDRD }, 499 { "clc", 0xd5, INSTR_SS_L0RDRD }, 500 { "oc", 0xd6, INSTR_SS_L0RDRD }, 501 { "xc", 0xd7, INSTR_SS_L0RDRD }, 502 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 503 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 504 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 505 { "tr", 0xdc, INSTR_SS_L0RDRD }, 506 { "trt", 0xdd, INSTR_SS_L0RDRD }, 507 { "ed", 0xde, INSTR_SS_L0RDRD }, 508 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 509 { "pku", 0xe1, INSTR_SS_L0RDRD }, 510 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 511 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 512 { "pka", 0xe9, INSTR_SS_L0RDRD }, 513 { "unpka", 0xea, INSTR_SS_L0RDRD }, 514 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 515 { "srp", 0xf0, INSTR_SS_LIRDRD }, 516 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 517 { "pack", 0xf2, INSTR_SS_LLRDRD }, 518 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 519 { "zap", 0xf8, INSTR_SS_LLRDRD }, 520 { "cp", 0xf9, INSTR_SS_LLRDRD }, 521 { "ap", 0xfa, INSTR_SS_LLRDRD }, 522 { "sp", 0xfb, INSTR_SS_LLRDRD }, 523 { "mp", 0xfc, INSTR_SS_LLRDRD }, 524 { "dp", 0xfd, INSTR_SS_LLRDRD }, 525 { "", 0, INSTR_INVALID } 526 }; 527 528 static struct insn opcode_01[] = { 529 #ifdef CONFIG_64BIT 530 { "sam64", 0x0e, INSTR_E }, 531 { "pfpo", 0x0a, INSTR_E }, 532 { "ptff", 0x04, INSTR_E }, 533 #endif 534 { "pr", 0x01, INSTR_E }, 535 { "upt", 0x02, INSTR_E }, 536 { "sckpf", 0x07, INSTR_E }, 537 { "tam", 0x0b, INSTR_E }, 538 { "sam24", 0x0c, INSTR_E }, 539 { "sam31", 0x0d, INSTR_E }, 540 { "trap2", 0xff, INSTR_E }, 541 { "", 0, INSTR_INVALID } 542 }; 543 544 static struct insn opcode_a5[] = { 545 #ifdef CONFIG_64BIT 546 { "iihh", 0x00, INSTR_RI_RU }, 547 { "iihl", 0x01, INSTR_RI_RU }, 548 { "iilh", 0x02, INSTR_RI_RU }, 549 { "iill", 0x03, INSTR_RI_RU }, 550 { "nihh", 0x04, INSTR_RI_RU }, 551 { "nihl", 0x05, INSTR_RI_RU }, 552 { "nilh", 0x06, INSTR_RI_RU }, 553 { "nill", 0x07, INSTR_RI_RU }, 554 { "oihh", 0x08, INSTR_RI_RU }, 555 { "oihl", 0x09, INSTR_RI_RU }, 556 { "oilh", 0x0a, INSTR_RI_RU }, 557 { "oill", 0x0b, INSTR_RI_RU }, 558 { "llihh", 0x0c, INSTR_RI_RU }, 559 { "llihl", 0x0d, INSTR_RI_RU }, 560 { "llilh", 0x0e, INSTR_RI_RU }, 561 { "llill", 0x0f, INSTR_RI_RU }, 562 #endif 563 { "", 0, INSTR_INVALID } 564 }; 565 566 static struct insn opcode_a7[] = { 567 #ifdef CONFIG_64BIT 568 { "tmhh", 0x02, INSTR_RI_RU }, 569 { "tmhl", 0x03, INSTR_RI_RU }, 570 { "brctg", 0x07, INSTR_RI_RP }, 571 { "lghi", 0x09, INSTR_RI_RI }, 572 { "aghi", 0x0b, INSTR_RI_RI }, 573 { "mghi", 0x0d, INSTR_RI_RI }, 574 { "cghi", 0x0f, INSTR_RI_RI }, 575 #endif 576 { "tmlh", 0x00, INSTR_RI_RU }, 577 { "tmll", 0x01, INSTR_RI_RU }, 578 { "brc", 0x04, INSTR_RI_UP }, 579 { "bras", 0x05, INSTR_RI_RP }, 580 { "brct", 0x06, INSTR_RI_RP }, 581 { "lhi", 0x08, INSTR_RI_RI }, 582 { "ahi", 0x0a, INSTR_RI_RI }, 583 { "mhi", 0x0c, INSTR_RI_RI }, 584 { "chi", 0x0e, INSTR_RI_RI }, 585 { "", 0, INSTR_INVALID } 586 }; 587 588 static struct insn opcode_b2[] = { 589 #ifdef CONFIG_64BIT 590 { "sske", 0x2b, INSTR_RRF_M0RR }, 591 { "stckf", 0x7c, INSTR_S_RD }, 592 { "cu21", 0xa6, INSTR_RRF_M0RR }, 593 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 594 { "cu12", 0xa7, INSTR_RRF_M0RR }, 595 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 596 { "stfle", 0xb0, INSTR_S_RD }, 597 { "lpswe", 0xb2, INSTR_S_RD }, 598 { "srnmt", 0xb9, INSTR_S_RD }, 599 { "lfas", 0xbd, INSTR_S_RD }, 600 #endif 601 { "stidp", 0x02, INSTR_S_RD }, 602 { "sck", 0x04, INSTR_S_RD }, 603 { "stck", 0x05, INSTR_S_RD }, 604 { "sckc", 0x06, INSTR_S_RD }, 605 { "stckc", 0x07, INSTR_S_RD }, 606 { "spt", 0x08, INSTR_S_RD }, 607 { "stpt", 0x09, INSTR_S_RD }, 608 { "spka", 0x0a, INSTR_S_RD }, 609 { "ipk", 0x0b, INSTR_S_00 }, 610 { "ptlb", 0x0d, INSTR_S_00 }, 611 { "spx", 0x10, INSTR_S_RD }, 612 { "stpx", 0x11, INSTR_S_RD }, 613 { "stap", 0x12, INSTR_S_RD }, 614 { "sie", 0x14, INSTR_S_RD }, 615 { "pc", 0x18, INSTR_S_RD }, 616 { "sac", 0x19, INSTR_S_RD }, 617 { "cfc", 0x1a, INSTR_S_RD }, 618 { "ipte", 0x21, INSTR_RRE_RR }, 619 { "ipm", 0x22, INSTR_RRE_R0 }, 620 { "ivsk", 0x23, INSTR_RRE_RR }, 621 { "iac", 0x24, INSTR_RRE_R0 }, 622 { "ssar", 0x25, INSTR_RRE_R0 }, 623 { "epar", 0x26, INSTR_RRE_R0 }, 624 { "esar", 0x27, INSTR_RRE_R0 }, 625 { "pt", 0x28, INSTR_RRE_RR }, 626 { "iske", 0x29, INSTR_RRE_RR }, 627 { "rrbe", 0x2a, INSTR_RRE_RR }, 628 { "sske", 0x2b, INSTR_RRE_RR }, 629 { "tb", 0x2c, INSTR_RRE_0R }, 630 { "dxr", 0x2d, INSTR_RRE_F0 }, 631 { "pgin", 0x2e, INSTR_RRE_RR }, 632 { "pgout", 0x2f, INSTR_RRE_RR }, 633 { "csch", 0x30, INSTR_S_00 }, 634 { "hsch", 0x31, INSTR_S_00 }, 635 { "msch", 0x32, INSTR_S_RD }, 636 { "ssch", 0x33, INSTR_S_RD }, 637 { "stsch", 0x34, INSTR_S_RD }, 638 { "tsch", 0x35, INSTR_S_RD }, 639 { "tpi", 0x36, INSTR_S_RD }, 640 { "sal", 0x37, INSTR_S_00 }, 641 { "rsch", 0x38, INSTR_S_00 }, 642 { "stcrw", 0x39, INSTR_S_RD }, 643 { "stcps", 0x3a, INSTR_S_RD }, 644 { "rchp", 0x3b, INSTR_S_00 }, 645 { "schm", 0x3c, INSTR_S_00 }, 646 { "bakr", 0x40, INSTR_RRE_RR }, 647 { "cksm", 0x41, INSTR_RRE_RR }, 648 { "sqdr", 0x44, INSTR_RRE_F0 }, 649 { "sqer", 0x45, INSTR_RRE_F0 }, 650 { "stura", 0x46, INSTR_RRE_RR }, 651 { "msta", 0x47, INSTR_RRE_R0 }, 652 { "palb", 0x48, INSTR_RRE_00 }, 653 { "ereg", 0x49, INSTR_RRE_RR }, 654 { "esta", 0x4a, INSTR_RRE_RR }, 655 { "lura", 0x4b, INSTR_RRE_RR }, 656 { "tar", 0x4c, INSTR_RRE_AR }, 657 { "cpya", 0x4d, INSTR_RRE_AA }, 658 { "sar", 0x4e, INSTR_RRE_AR }, 659 { "ear", 0x4f, INSTR_RRE_RA }, 660 { "csp", 0x50, INSTR_RRE_RR }, 661 { "msr", 0x52, INSTR_RRE_RR }, 662 { "mvpg", 0x54, INSTR_RRE_RR }, 663 { "mvst", 0x55, INSTR_RRE_RR }, 664 { "cuse", 0x57, INSTR_RRE_RR }, 665 { "bsg", 0x58, INSTR_RRE_RR }, 666 { "bsa", 0x5a, INSTR_RRE_RR }, 667 { "clst", 0x5d, INSTR_RRE_RR }, 668 { "srst", 0x5e, INSTR_RRE_RR }, 669 { "cmpsc", 0x63, INSTR_RRE_RR }, 670 { "siga", 0x74, INSTR_S_RD }, 671 { "xsch", 0x76, INSTR_S_00 }, 672 { "rp", 0x77, INSTR_S_RD }, 673 { "stcke", 0x78, INSTR_S_RD }, 674 { "sacf", 0x79, INSTR_S_RD }, 675 { "stsi", 0x7d, INSTR_S_RD }, 676 { "srnm", 0x99, INSTR_S_RD }, 677 { "stfpc", 0x9c, INSTR_S_RD }, 678 { "lfpc", 0x9d, INSTR_S_RD }, 679 { "tre", 0xa5, INSTR_RRE_RR }, 680 { "cuutf", 0xa6, INSTR_RRE_RR }, 681 { "cutfu", 0xa7, INSTR_RRE_RR }, 682 { "stfl", 0xb1, INSTR_S_RD }, 683 { "trap4", 0xff, INSTR_S_RD }, 684 { "", 0, INSTR_INVALID } 685 }; 686 687 static struct insn opcode_b3[] = { 688 #ifdef CONFIG_64BIT 689 { "maylr", 0x38, INSTR_RRF_F0FF }, 690 { "mylr", 0x39, INSTR_RRF_F0FF }, 691 { "mayr", 0x3a, INSTR_RRF_F0FF }, 692 { "myr", 0x3b, INSTR_RRF_F0FF }, 693 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 694 { "myhr", 0x3d, INSTR_RRF_F0FF }, 695 { "cegbr", 0xa4, INSTR_RRE_RR }, 696 { "cdgbr", 0xa5, INSTR_RRE_RR }, 697 { "cxgbr", 0xa6, INSTR_RRE_RR }, 698 { "cgebr", 0xa8, INSTR_RRF_U0RF }, 699 { "cgdbr", 0xa9, INSTR_RRF_U0RF }, 700 { "cgxbr", 0xaa, INSTR_RRF_U0RF }, 701 { "cfer", 0xb8, INSTR_RRF_U0RF }, 702 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 703 { "cfxr", 0xba, INSTR_RRF_U0RF }, 704 { "cegr", 0xc4, INSTR_RRE_RR }, 705 { "cdgr", 0xc5, INSTR_RRE_RR }, 706 { "cxgr", 0xc6, INSTR_RRE_RR }, 707 { "cger", 0xc8, INSTR_RRF_U0RF }, 708 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 709 { "cgxr", 0xca, INSTR_RRF_U0RF }, 710 { "lpdfr", 0x70, INSTR_RRE_FF }, 711 { "lndfr", 0x71, INSTR_RRE_FF }, 712 { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, 713 { "lcdfr", 0x73, INSTR_RRE_FF }, 714 { "ldgr", 0xc1, INSTR_RRE_FR }, 715 { "lgdr", 0xcd, INSTR_RRE_RF }, 716 { "adtr", 0xd2, INSTR_RRR_F0FF }, 717 { "axtr", 0xda, INSTR_RRR_F0FF }, 718 { "cdtr", 0xe4, INSTR_RRE_FF }, 719 { "cxtr", 0xec, INSTR_RRE_FF }, 720 { "kdtr", 0xe0, INSTR_RRE_FF }, 721 { "kxtr", 0xe8, INSTR_RRE_FF }, 722 { "cedtr", 0xf4, INSTR_RRE_FF }, 723 { "cextr", 0xfc, INSTR_RRE_FF }, 724 { "cdgtr", 0xf1, INSTR_RRE_FR }, 725 { "cxgtr", 0xf9, INSTR_RRE_FR }, 726 { "cdstr", 0xf3, INSTR_RRE_FR }, 727 { "cxstr", 0xfb, INSTR_RRE_FR }, 728 { "cdutr", 0xf2, INSTR_RRE_FR }, 729 { "cxutr", 0xfa, INSTR_RRE_FR }, 730 { "cgdtr", 0xe1, INSTR_RRF_U0RF }, 731 { "cgxtr", 0xe9, INSTR_RRF_U0RF }, 732 { "csdtr", 0xe3, INSTR_RRE_RF }, 733 { "csxtr", 0xeb, INSTR_RRE_RF }, 734 { "cudtr", 0xe2, INSTR_RRE_RF }, 735 { "cuxtr", 0xea, INSTR_RRE_RF }, 736 { "ddtr", 0xd1, INSTR_RRR_F0FF }, 737 { "dxtr", 0xd9, INSTR_RRR_F0FF }, 738 { "eedtr", 0xe5, INSTR_RRE_RF }, 739 { "eextr", 0xed, INSTR_RRE_RF }, 740 { "esdtr", 0xe7, INSTR_RRE_RF }, 741 { "esxtr", 0xef, INSTR_RRE_RF }, 742 { "iedtr", 0xf6, INSTR_RRF_F0FR }, 743 { "iextr", 0xfe, INSTR_RRF_F0FR }, 744 { "ltdtr", 0xd6, INSTR_RRE_FF }, 745 { "ltxtr", 0xde, INSTR_RRE_FF }, 746 { "fidtr", 0xd7, INSTR_RRF_UUFF }, 747 { "fixtr", 0xdf, INSTR_RRF_UUFF }, 748 { "ldetr", 0xd4, INSTR_RRF_0UFF }, 749 { "lxdtr", 0xdc, INSTR_RRF_0UFF }, 750 { "ledtr", 0xd5, INSTR_RRF_UUFF }, 751 { "ldxtr", 0xdd, INSTR_RRF_UUFF }, 752 { "mdtr", 0xd0, INSTR_RRR_F0FF }, 753 { "mxtr", 0xd8, INSTR_RRR_F0FF }, 754 { "qadtr", 0xf5, INSTR_RRF_FUFF }, 755 { "qaxtr", 0xfd, INSTR_RRF_FUFF }, 756 { "rrdtr", 0xf7, INSTR_RRF_FFRU }, 757 { "rrxtr", 0xff, INSTR_RRF_FFRU }, 758 { "sfasr", 0x85, INSTR_RRE_R0 }, 759 { "sdtr", 0xd3, INSTR_RRR_F0FF }, 760 { "sxtr", 0xdb, INSTR_RRR_F0FF }, 761 #endif 762 { "lpebr", 0x00, INSTR_RRE_FF }, 763 { "lnebr", 0x01, INSTR_RRE_FF }, 764 { "ltebr", 0x02, INSTR_RRE_FF }, 765 { "lcebr", 0x03, INSTR_RRE_FF }, 766 { "ldebr", 0x04, INSTR_RRE_FF }, 767 { "lxdbr", 0x05, INSTR_RRE_FF }, 768 { "lxebr", 0x06, INSTR_RRE_FF }, 769 { "mxdbr", 0x07, INSTR_RRE_FF }, 770 { "kebr", 0x08, INSTR_RRE_FF }, 771 { "cebr", 0x09, INSTR_RRE_FF }, 772 { "aebr", 0x0a, INSTR_RRE_FF }, 773 { "sebr", 0x0b, INSTR_RRE_FF }, 774 { "mdebr", 0x0c, INSTR_RRE_FF }, 775 { "debr", 0x0d, INSTR_RRE_FF }, 776 { "maebr", 0x0e, INSTR_RRF_F0FF }, 777 { "msebr", 0x0f, INSTR_RRF_F0FF }, 778 { "lpdbr", 0x10, INSTR_RRE_FF }, 779 { "lndbr", 0x11, INSTR_RRE_FF }, 780 { "ltdbr", 0x12, INSTR_RRE_FF }, 781 { "lcdbr", 0x13, INSTR_RRE_FF }, 782 { "sqebr", 0x14, INSTR_RRE_FF }, 783 { "sqdbr", 0x15, INSTR_RRE_FF }, 784 { "sqxbr", 0x16, INSTR_RRE_FF }, 785 { "meebr", 0x17, INSTR_RRE_FF }, 786 { "kdbr", 0x18, INSTR_RRE_FF }, 787 { "cdbr", 0x19, INSTR_RRE_FF }, 788 { "adbr", 0x1a, INSTR_RRE_FF }, 789 { "sdbr", 0x1b, INSTR_RRE_FF }, 790 { "mdbr", 0x1c, INSTR_RRE_FF }, 791 { "ddbr", 0x1d, INSTR_RRE_FF }, 792 { "madbr", 0x1e, INSTR_RRF_F0FF }, 793 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 794 { "lder", 0x24, INSTR_RRE_FF }, 795 { "lxdr", 0x25, INSTR_RRE_FF }, 796 { "lxer", 0x26, INSTR_RRE_FF }, 797 { "maer", 0x2e, INSTR_RRF_F0FF }, 798 { "mser", 0x2f, INSTR_RRF_F0FF }, 799 { "sqxr", 0x36, INSTR_RRE_FF }, 800 { "meer", 0x37, INSTR_RRE_FF }, 801 { "madr", 0x3e, INSTR_RRF_F0FF }, 802 { "msdr", 0x3f, INSTR_RRF_F0FF }, 803 { "lpxbr", 0x40, INSTR_RRE_FF }, 804 { "lnxbr", 0x41, INSTR_RRE_FF }, 805 { "ltxbr", 0x42, INSTR_RRE_FF }, 806 { "lcxbr", 0x43, INSTR_RRE_FF }, 807 { "ledbr", 0x44, INSTR_RRE_FF }, 808 { "ldxbr", 0x45, INSTR_RRE_FF }, 809 { "lexbr", 0x46, INSTR_RRE_FF }, 810 { "fixbr", 0x47, INSTR_RRF_U0FF }, 811 { "kxbr", 0x48, INSTR_RRE_FF }, 812 { "cxbr", 0x49, INSTR_RRE_FF }, 813 { "axbr", 0x4a, INSTR_RRE_FF }, 814 { "sxbr", 0x4b, INSTR_RRE_FF }, 815 { "mxbr", 0x4c, INSTR_RRE_FF }, 816 { "dxbr", 0x4d, INSTR_RRE_FF }, 817 { "tbedr", 0x50, INSTR_RRF_U0FF }, 818 { "tbdr", 0x51, INSTR_RRF_U0FF }, 819 { "diebr", 0x53, INSTR_RRF_FUFF }, 820 { "fiebr", 0x57, INSTR_RRF_U0FF }, 821 { "thder", 0x58, INSTR_RRE_RR }, 822 { "thdr", 0x59, INSTR_RRE_RR }, 823 { "didbr", 0x5b, INSTR_RRF_FUFF }, 824 { "fidbr", 0x5f, INSTR_RRF_U0FF }, 825 { "lpxr", 0x60, INSTR_RRE_FF }, 826 { "lnxr", 0x61, INSTR_RRE_FF }, 827 { "ltxr", 0x62, INSTR_RRE_FF }, 828 { "lcxr", 0x63, INSTR_RRE_FF }, 829 { "lxr", 0x65, INSTR_RRE_RR }, 830 { "lexr", 0x66, INSTR_RRE_FF }, 831 { "fixr", 0x67, INSTR_RRF_U0FF }, 832 { "cxr", 0x69, INSTR_RRE_FF }, 833 { "lzer", 0x74, INSTR_RRE_R0 }, 834 { "lzdr", 0x75, INSTR_RRE_R0 }, 835 { "lzxr", 0x76, INSTR_RRE_R0 }, 836 { "fier", 0x77, INSTR_RRF_U0FF }, 837 { "fidr", 0x7f, INSTR_RRF_U0FF }, 838 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 839 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 840 { "cefbr", 0x94, INSTR_RRE_RF }, 841 { "cdfbr", 0x95, INSTR_RRE_RF }, 842 { "cxfbr", 0x96, INSTR_RRE_RF }, 843 { "cfebr", 0x98, INSTR_RRF_U0RF }, 844 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 845 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 846 { "cefr", 0xb4, INSTR_RRE_RF }, 847 { "cdfr", 0xb5, INSTR_RRE_RF }, 848 { "cxfr", 0xb6, INSTR_RRE_RF }, 849 { "", 0, INSTR_INVALID } 850 }; 851 852 static struct insn opcode_b9[] = { 853 #ifdef CONFIG_64BIT 854 { "lpgr", 0x00, INSTR_RRE_RR }, 855 { "lngr", 0x01, INSTR_RRE_RR }, 856 { "ltgr", 0x02, INSTR_RRE_RR }, 857 { "lcgr", 0x03, INSTR_RRE_RR }, 858 { "lgr", 0x04, INSTR_RRE_RR }, 859 { "lurag", 0x05, INSTR_RRE_RR }, 860 { "lgbr", 0x06, INSTR_RRE_RR }, 861 { "lghr", 0x07, INSTR_RRE_RR }, 862 { "agr", 0x08, INSTR_RRE_RR }, 863 { "sgr", 0x09, INSTR_RRE_RR }, 864 { "algr", 0x0a, INSTR_RRE_RR }, 865 { "slgr", 0x0b, INSTR_RRE_RR }, 866 { "msgr", 0x0c, INSTR_RRE_RR }, 867 { "dsgr", 0x0d, INSTR_RRE_RR }, 868 { "eregg", 0x0e, INSTR_RRE_RR }, 869 { "lrvgr", 0x0f, INSTR_RRE_RR }, 870 { "lpgfr", 0x10, INSTR_RRE_RR }, 871 { "lngfr", 0x11, INSTR_RRE_RR }, 872 { "ltgfr", 0x12, INSTR_RRE_RR }, 873 { "lcgfr", 0x13, INSTR_RRE_RR }, 874 { "lgfr", 0x14, INSTR_RRE_RR }, 875 { "llgfr", 0x16, INSTR_RRE_RR }, 876 { "llgtr", 0x17, INSTR_RRE_RR }, 877 { "agfr", 0x18, INSTR_RRE_RR }, 878 { "sgfr", 0x19, INSTR_RRE_RR }, 879 { "algfr", 0x1a, INSTR_RRE_RR }, 880 { "slgfr", 0x1b, INSTR_RRE_RR }, 881 { "msgfr", 0x1c, INSTR_RRE_RR }, 882 { "dsgfr", 0x1d, INSTR_RRE_RR }, 883 { "cgr", 0x20, INSTR_RRE_RR }, 884 { "clgr", 0x21, INSTR_RRE_RR }, 885 { "sturg", 0x25, INSTR_RRE_RR }, 886 { "lbr", 0x26, INSTR_RRE_RR }, 887 { "lhr", 0x27, INSTR_RRE_RR }, 888 { "cgfr", 0x30, INSTR_RRE_RR }, 889 { "clgfr", 0x31, INSTR_RRE_RR }, 890 { "bctgr", 0x46, INSTR_RRE_RR }, 891 { "ngr", 0x80, INSTR_RRE_RR }, 892 { "ogr", 0x81, INSTR_RRE_RR }, 893 { "xgr", 0x82, INSTR_RRE_RR }, 894 { "flogr", 0x83, INSTR_RRE_RR }, 895 { "llgcr", 0x84, INSTR_RRE_RR }, 896 { "llghr", 0x85, INSTR_RRE_RR }, 897 { "mlgr", 0x86, INSTR_RRE_RR }, 898 { "dlgr", 0x87, INSTR_RRE_RR }, 899 { "alcgr", 0x88, INSTR_RRE_RR }, 900 { "slbgr", 0x89, INSTR_RRE_RR }, 901 { "cspg", 0x8a, INSTR_RRE_RR }, 902 { "idte", 0x8e, INSTR_RRF_R0RR }, 903 { "llcr", 0x94, INSTR_RRE_RR }, 904 { "llhr", 0x95, INSTR_RRE_RR }, 905 { "esea", 0x9d, INSTR_RRE_R0 }, 906 { "lptea", 0xaa, INSTR_RRF_RURR }, 907 { "cu14", 0xb0, INSTR_RRF_M0RR }, 908 { "cu24", 0xb1, INSTR_RRF_M0RR }, 909 { "cu41", 0xb2, INSTR_RRF_M0RR }, 910 { "cu42", 0xb3, INSTR_RRF_M0RR }, 911 { "crt", 0x72, INSTR_RRF_U0RR }, 912 { "cgrt", 0x60, INSTR_RRF_U0RR }, 913 { "clrt", 0x73, INSTR_RRF_U0RR }, 914 { "clgrt", 0x61, INSTR_RRF_U0RR }, 915 { "ptf", 0xa2, INSTR_RRE_R0 }, 916 { "pfmf", 0xaf, INSTR_RRE_RR }, 917 { "trte", 0xbf, INSTR_RRF_M0RR }, 918 { "trtre", 0xbd, INSTR_RRF_M0RR }, 919 { "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, 920 { "shhhr", 0xc9, INSTR_RRF_R0RR2 }, 921 { "alhhh", 0xca, INSTR_RRF_R0RR2 }, 922 { "alhhl", 0xca, INSTR_RRF_R0RR2 }, 923 { "slhhh", 0xcb, INSTR_RRF_R0RR2 }, 924 { "chhr ", 0xcd, INSTR_RRE_RR }, 925 { "clhhr", 0xcf, INSTR_RRE_RR }, 926 { "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, 927 { "shhlr", 0xd9, INSTR_RRF_R0RR2 }, 928 { "slhhl", 0xdb, INSTR_RRF_R0RR2 }, 929 { "chlr", 0xdd, INSTR_RRE_RR }, 930 { "clhlr", 0xdf, INSTR_RRE_RR }, 931 { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, 932 { "locgr", 0xe2, INSTR_RRF_M0RR }, 933 { "ngrk", 0xe4, INSTR_RRF_R0RR2 }, 934 { "ogrk", 0xe6, INSTR_RRF_R0RR2 }, 935 { "xgrk", 0xe7, INSTR_RRF_R0RR2 }, 936 { "agrk", 0xe8, INSTR_RRF_R0RR2 }, 937 { "sgrk", 0xe9, INSTR_RRF_R0RR2 }, 938 { "algrk", 0xea, INSTR_RRF_R0RR2 }, 939 { "slgrk", 0xeb, INSTR_RRF_R0RR2 }, 940 { "locr", 0xf2, INSTR_RRF_M0RR }, 941 { "nrk", 0xf4, INSTR_RRF_R0RR2 }, 942 { "ork", 0xf6, INSTR_RRF_R0RR2 }, 943 { "xrk", 0xf7, INSTR_RRF_R0RR2 }, 944 { "ark", 0xf8, INSTR_RRF_R0RR2 }, 945 { "srk", 0xf9, INSTR_RRF_R0RR2 }, 946 { "alrk", 0xfa, INSTR_RRF_R0RR2 }, 947 { "slrk", 0xfb, INSTR_RRF_R0RR2 }, 948 #endif 949 { "kmac", 0x1e, INSTR_RRE_RR }, 950 { "lrvr", 0x1f, INSTR_RRE_RR }, 951 { "km", 0x2e, INSTR_RRE_RR }, 952 { "kmc", 0x2f, INSTR_RRE_RR }, 953 { "kimd", 0x3e, INSTR_RRE_RR }, 954 { "klmd", 0x3f, INSTR_RRE_RR }, 955 { "epsw", 0x8d, INSTR_RRE_RR }, 956 { "trtt", 0x90, INSTR_RRE_RR }, 957 { "trtt", 0x90, INSTR_RRF_M0RR }, 958 { "trto", 0x91, INSTR_RRE_RR }, 959 { "trto", 0x91, INSTR_RRF_M0RR }, 960 { "trot", 0x92, INSTR_RRE_RR }, 961 { "trot", 0x92, INSTR_RRF_M0RR }, 962 { "troo", 0x93, INSTR_RRE_RR }, 963 { "troo", 0x93, INSTR_RRF_M0RR }, 964 { "mlr", 0x96, INSTR_RRE_RR }, 965 { "dlr", 0x97, INSTR_RRE_RR }, 966 { "alcr", 0x98, INSTR_RRE_RR }, 967 { "slbr", 0x99, INSTR_RRE_RR }, 968 { "", 0, INSTR_INVALID } 969 }; 970 971 static struct insn opcode_c0[] = { 972 #ifdef CONFIG_64BIT 973 { "lgfi", 0x01, INSTR_RIL_RI }, 974 { "xihf", 0x06, INSTR_RIL_RU }, 975 { "xilf", 0x07, INSTR_RIL_RU }, 976 { "iihf", 0x08, INSTR_RIL_RU }, 977 { "iilf", 0x09, INSTR_RIL_RU }, 978 { "nihf", 0x0a, INSTR_RIL_RU }, 979 { "nilf", 0x0b, INSTR_RIL_RU }, 980 { "oihf", 0x0c, INSTR_RIL_RU }, 981 { "oilf", 0x0d, INSTR_RIL_RU }, 982 { "llihf", 0x0e, INSTR_RIL_RU }, 983 { "llilf", 0x0f, INSTR_RIL_RU }, 984 #endif 985 { "larl", 0x00, INSTR_RIL_RP }, 986 { "brcl", 0x04, INSTR_RIL_UP }, 987 { "brasl", 0x05, INSTR_RIL_RP }, 988 { "", 0, INSTR_INVALID } 989 }; 990 991 static struct insn opcode_c2[] = { 992 #ifdef CONFIG_64BIT 993 { "slgfi", 0x04, INSTR_RIL_RU }, 994 { "slfi", 0x05, INSTR_RIL_RU }, 995 { "agfi", 0x08, INSTR_RIL_RI }, 996 { "afi", 0x09, INSTR_RIL_RI }, 997 { "algfi", 0x0a, INSTR_RIL_RU }, 998 { "alfi", 0x0b, INSTR_RIL_RU }, 999 { "cgfi", 0x0c, INSTR_RIL_RI }, 1000 { "cfi", 0x0d, INSTR_RIL_RI }, 1001 { "clgfi", 0x0e, INSTR_RIL_RU }, 1002 { "clfi", 0x0f, INSTR_RIL_RU }, 1003 { "msfi", 0x01, INSTR_RIL_RI }, 1004 { "msgfi", 0x00, INSTR_RIL_RI }, 1005 #endif 1006 { "", 0, INSTR_INVALID } 1007 }; 1008 1009 static struct insn opcode_c4[] = { 1010 #ifdef CONFIG_64BIT 1011 { "lrl", 0x0d, INSTR_RIL_RP }, 1012 { "lgrl", 0x08, INSTR_RIL_RP }, 1013 { "lgfrl", 0x0c, INSTR_RIL_RP }, 1014 { "lhrl", 0x05, INSTR_RIL_RP }, 1015 { "lghrl", 0x04, INSTR_RIL_RP }, 1016 { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, 1017 { "llhrl", 0x02, INSTR_RIL_RP }, 1018 { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP }, 1019 { "strl", 0x0f, INSTR_RIL_RP }, 1020 { "stgrl", 0x0b, INSTR_RIL_RP }, 1021 { "sthrl", 0x07, INSTR_RIL_RP }, 1022 #endif 1023 { "", 0, INSTR_INVALID } 1024 }; 1025 1026 static struct insn opcode_c6[] = { 1027 #ifdef CONFIG_64BIT 1028 { "crl", 0x0d, INSTR_RIL_RP }, 1029 { "cgrl", 0x08, INSTR_RIL_RP }, 1030 { "cgfrl", 0x0c, INSTR_RIL_RP }, 1031 { "chrl", 0x05, INSTR_RIL_RP }, 1032 { "cghrl", 0x04, INSTR_RIL_RP }, 1033 { "clrl", 0x0f, INSTR_RIL_RP }, 1034 { "clgrl", 0x0a, INSTR_RIL_RP }, 1035 { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, 1036 { "clhrl", 0x07, INSTR_RIL_RP }, 1037 { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP }, 1038 { "pfdrl", 0x02, INSTR_RIL_UP }, 1039 { "exrl", 0x00, INSTR_RIL_RP }, 1040 #endif 1041 { "", 0, INSTR_INVALID } 1042 }; 1043 1044 static struct insn opcode_c8[] = { 1045 #ifdef CONFIG_64BIT 1046 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 1047 { "ectg", 0x01, INSTR_SSF_RRDRD }, 1048 { "csst", 0x02, INSTR_SSF_RRDRD }, 1049 { "lpd", 0x04, INSTR_SSF_RRDRD2 }, 1050 { "lpdg ", 0x05, INSTR_SSF_RRDRD2 }, 1051 #endif 1052 { "", 0, INSTR_INVALID } 1053 }; 1054 1055 static struct insn opcode_cc[] = { 1056 #ifdef CONFIG_64BIT 1057 { "brcth", 0x06, INSTR_RIL_RP }, 1058 { "aih", 0x08, INSTR_RIL_RI }, 1059 { "alsih", 0x0a, INSTR_RIL_RI }, 1060 { "alsih", 0x0b, INSTR_RIL_RI }, 1061 { "cih", 0x0d, INSTR_RIL_RI }, 1062 { "clih ", 0x0f, INSTR_RIL_RI }, 1063 #endif 1064 { "", 0, INSTR_INVALID } 1065 }; 1066 1067 static struct insn opcode_e3[] = { 1068 #ifdef CONFIG_64BIT 1069 { "ltg", 0x02, INSTR_RXY_RRRD }, 1070 { "lrag", 0x03, INSTR_RXY_RRRD }, 1071 { "lg", 0x04, INSTR_RXY_RRRD }, 1072 { "cvby", 0x06, INSTR_RXY_RRRD }, 1073 { "ag", 0x08, INSTR_RXY_RRRD }, 1074 { "sg", 0x09, INSTR_RXY_RRRD }, 1075 { "alg", 0x0a, INSTR_RXY_RRRD }, 1076 { "slg", 0x0b, INSTR_RXY_RRRD }, 1077 { "msg", 0x0c, INSTR_RXY_RRRD }, 1078 { "dsg", 0x0d, INSTR_RXY_RRRD }, 1079 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 1080 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 1081 { "lt", 0x12, INSTR_RXY_RRRD }, 1082 { "lray", 0x13, INSTR_RXY_RRRD }, 1083 { "lgf", 0x14, INSTR_RXY_RRRD }, 1084 { "lgh", 0x15, INSTR_RXY_RRRD }, 1085 { "llgf", 0x16, INSTR_RXY_RRRD }, 1086 { "llgt", 0x17, INSTR_RXY_RRRD }, 1087 { "agf", 0x18, INSTR_RXY_RRRD }, 1088 { "sgf", 0x19, INSTR_RXY_RRRD }, 1089 { "algf", 0x1a, INSTR_RXY_RRRD }, 1090 { "slgf", 0x1b, INSTR_RXY_RRRD }, 1091 { "msgf", 0x1c, INSTR_RXY_RRRD }, 1092 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 1093 { "cg", 0x20, INSTR_RXY_RRRD }, 1094 { "clg", 0x21, INSTR_RXY_RRRD }, 1095 { "stg", 0x24, INSTR_RXY_RRRD }, 1096 { "cvdy", 0x26, INSTR_RXY_RRRD }, 1097 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 1098 { "strvg", 0x2f, INSTR_RXY_RRRD }, 1099 { "cgf", 0x30, INSTR_RXY_RRRD }, 1100 { "clgf", 0x31, INSTR_RXY_RRRD }, 1101 { "strvh", 0x3f, INSTR_RXY_RRRD }, 1102 { "bctg", 0x46, INSTR_RXY_RRRD }, 1103 { "sty", 0x50, INSTR_RXY_RRRD }, 1104 { "msy", 0x51, INSTR_RXY_RRRD }, 1105 { "ny", 0x54, INSTR_RXY_RRRD }, 1106 { "cly", 0x55, INSTR_RXY_RRRD }, 1107 { "oy", 0x56, INSTR_RXY_RRRD }, 1108 { "xy", 0x57, INSTR_RXY_RRRD }, 1109 { "ly", 0x58, INSTR_RXY_RRRD }, 1110 { "cy", 0x59, INSTR_RXY_RRRD }, 1111 { "ay", 0x5a, INSTR_RXY_RRRD }, 1112 { "sy", 0x5b, INSTR_RXY_RRRD }, 1113 { "aly", 0x5e, INSTR_RXY_RRRD }, 1114 { "sly", 0x5f, INSTR_RXY_RRRD }, 1115 { "sthy", 0x70, INSTR_RXY_RRRD }, 1116 { "lay", 0x71, INSTR_RXY_RRRD }, 1117 { "stcy", 0x72, INSTR_RXY_RRRD }, 1118 { "icy", 0x73, INSTR_RXY_RRRD }, 1119 { "lb", 0x76, INSTR_RXY_RRRD }, 1120 { "lgb", 0x77, INSTR_RXY_RRRD }, 1121 { "lhy", 0x78, INSTR_RXY_RRRD }, 1122 { "chy", 0x79, INSTR_RXY_RRRD }, 1123 { "ahy", 0x7a, INSTR_RXY_RRRD }, 1124 { "shy", 0x7b, INSTR_RXY_RRRD }, 1125 { "ng", 0x80, INSTR_RXY_RRRD }, 1126 { "og", 0x81, INSTR_RXY_RRRD }, 1127 { "xg", 0x82, INSTR_RXY_RRRD }, 1128 { "mlg", 0x86, INSTR_RXY_RRRD }, 1129 { "dlg", 0x87, INSTR_RXY_RRRD }, 1130 { "alcg", 0x88, INSTR_RXY_RRRD }, 1131 { "slbg", 0x89, INSTR_RXY_RRRD }, 1132 { "stpq", 0x8e, INSTR_RXY_RRRD }, 1133 { "lpq", 0x8f, INSTR_RXY_RRRD }, 1134 { "llgc", 0x90, INSTR_RXY_RRRD }, 1135 { "llgh", 0x91, INSTR_RXY_RRRD }, 1136 { "llc", 0x94, INSTR_RXY_RRRD }, 1137 { "llh", 0x95, INSTR_RXY_RRRD }, 1138 { "cgh", 0x34, INSTR_RXY_RRRD }, 1139 { "laey", 0x75, INSTR_RXY_RRRD }, 1140 { "ltgf", 0x32, INSTR_RXY_RRRD }, 1141 { "mfy", 0x5c, INSTR_RXY_RRRD }, 1142 { "mhy", 0x7c, INSTR_RXY_RRRD }, 1143 { "pfd", 0x36, INSTR_RXY_URRD }, 1144 { "lbh", 0xc0, INSTR_RXY_RRRD }, 1145 { "llch", 0xc2, INSTR_RXY_RRRD }, 1146 { "stch", 0xc3, INSTR_RXY_RRRD }, 1147 { "lhh", 0xc4, INSTR_RXY_RRRD }, 1148 { "llhh", 0xc6, INSTR_RXY_RRRD }, 1149 { "sthh", 0xc7, INSTR_RXY_RRRD }, 1150 { "lfh", 0xca, INSTR_RXY_RRRD }, 1151 { "stfh", 0xcb, INSTR_RXY_RRRD }, 1152 { "chf", 0xcd, INSTR_RXY_RRRD }, 1153 { "clhf", 0xcf, INSTR_RXY_RRRD }, 1154 #endif 1155 { "lrv", 0x1e, INSTR_RXY_RRRD }, 1156 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 1157 { "strv", 0x3e, INSTR_RXY_RRRD }, 1158 { "ml", 0x96, INSTR_RXY_RRRD }, 1159 { "dl", 0x97, INSTR_RXY_RRRD }, 1160 { "alc", 0x98, INSTR_RXY_RRRD }, 1161 { "slb", 0x99, INSTR_RXY_RRRD }, 1162 { "", 0, INSTR_INVALID } 1163 }; 1164 1165 static struct insn opcode_e5[] = { 1166 #ifdef CONFIG_64BIT 1167 { "strag", 0x02, INSTR_SSE_RDRD }, 1168 { "chhsi", 0x54, INSTR_SIL_RDI }, 1169 { "chsi", 0x5c, INSTR_SIL_RDI }, 1170 { "cghsi", 0x58, INSTR_SIL_RDI }, 1171 { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, 1172 { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, 1173 { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, 1174 { "mvhhi", 0x44, INSTR_SIL_RDI }, 1175 { "mvhi", 0x4c, INSTR_SIL_RDI }, 1176 { "mvghi", 0x48, INSTR_SIL_RDI }, 1177 #endif 1178 { "lasp", 0x00, INSTR_SSE_RDRD }, 1179 { "tprot", 0x01, INSTR_SSE_RDRD }, 1180 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 1181 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 1182 { "", 0, INSTR_INVALID } 1183 }; 1184 1185 static struct insn opcode_eb[] = { 1186 #ifdef CONFIG_64BIT 1187 { "lmg", 0x04, INSTR_RSY_RRRD }, 1188 { "srag", 0x0a, INSTR_RSY_RRRD }, 1189 { "slag", 0x0b, INSTR_RSY_RRRD }, 1190 { "srlg", 0x0c, INSTR_RSY_RRRD }, 1191 { "sllg", 0x0d, INSTR_RSY_RRRD }, 1192 { "tracg", 0x0f, INSTR_RSY_RRRD }, 1193 { "csy", 0x14, INSTR_RSY_RRRD }, 1194 { "rllg", 0x1c, INSTR_RSY_RRRD }, 1195 { "clmh", 0x20, INSTR_RSY_RURD }, 1196 { "clmy", 0x21, INSTR_RSY_RURD }, 1197 { "stmg", 0x24, INSTR_RSY_RRRD }, 1198 { "stctg", 0x25, INSTR_RSY_CCRD }, 1199 { "stmh", 0x26, INSTR_RSY_RRRD }, 1200 { "stcmh", 0x2c, INSTR_RSY_RURD }, 1201 { "stcmy", 0x2d, INSTR_RSY_RURD }, 1202 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 1203 { "csg", 0x30, INSTR_RSY_RRRD }, 1204 { "cdsy", 0x31, INSTR_RSY_RRRD }, 1205 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 1206 { "bxhg", 0x44, INSTR_RSY_RRRD }, 1207 { "bxleg", 0x45, INSTR_RSY_RRRD }, 1208 { "tmy", 0x51, INSTR_SIY_URD }, 1209 { "mviy", 0x52, INSTR_SIY_URD }, 1210 { "niy", 0x54, INSTR_SIY_URD }, 1211 { "cliy", 0x55, INSTR_SIY_URD }, 1212 { "oiy", 0x56, INSTR_SIY_URD }, 1213 { "xiy", 0x57, INSTR_SIY_URD }, 1214 { "icmh", 0x80, INSTR_RSE_RURD }, 1215 { "icmh", 0x80, INSTR_RSY_RURD }, 1216 { "icmy", 0x81, INSTR_RSY_RURD }, 1217 { "clclu", 0x8f, INSTR_RSY_RRRD }, 1218 { "stmy", 0x90, INSTR_RSY_RRRD }, 1219 { "lmh", 0x96, INSTR_RSY_RRRD }, 1220 { "lmy", 0x98, INSTR_RSY_RRRD }, 1221 { "lamy", 0x9a, INSTR_RSY_AARD }, 1222 { "stamy", 0x9b, INSTR_RSY_AARD }, 1223 { "asi", 0x6a, INSTR_SIY_IRD }, 1224 { "agsi", 0x7a, INSTR_SIY_IRD }, 1225 { "alsi", 0x6e, INSTR_SIY_IRD }, 1226 { "algsi", 0x7e, INSTR_SIY_IRD }, 1227 { "ecag", 0x4c, INSTR_RSY_RRRD }, 1228 { "srak", 0xdc, INSTR_RSY_RRRD }, 1229 { "slak", 0xdd, INSTR_RSY_RRRD }, 1230 { "srlk", 0xde, INSTR_RSY_RRRD }, 1231 { "sllk", 0xdf, INSTR_RSY_RRRD }, 1232 { "locg", 0xe2, INSTR_RSY_RDRM }, 1233 { "stocg", 0xe3, INSTR_RSY_RDRM }, 1234 { "lang", 0xe4, INSTR_RSY_RRRD }, 1235 { "laog", 0xe6, INSTR_RSY_RRRD }, 1236 { "laxg", 0xe7, INSTR_RSY_RRRD }, 1237 { "laag", 0xe8, INSTR_RSY_RRRD }, 1238 { "laalg", 0xea, INSTR_RSY_RRRD }, 1239 { "loc", 0xf2, INSTR_RSY_RDRM }, 1240 { "stoc", 0xf3, INSTR_RSY_RDRM }, 1241 { "lan", 0xf4, INSTR_RSY_RRRD }, 1242 { "lao", 0xf6, INSTR_RSY_RRRD }, 1243 { "lax", 0xf7, INSTR_RSY_RRRD }, 1244 { "laa", 0xf8, INSTR_RSY_RRRD }, 1245 { "laal", 0xfa, INSTR_RSY_RRRD }, 1246 #endif 1247 { "rll", 0x1d, INSTR_RSY_RRRD }, 1248 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 1249 { "tp", 0xc0, INSTR_RSL_R0RD }, 1250 { "", 0, INSTR_INVALID } 1251 }; 1252 1253 static struct insn opcode_ec[] = { 1254 #ifdef CONFIG_64BIT 1255 { "brxhg", 0x44, INSTR_RIE_RRP }, 1256 { "brxlg", 0x45, INSTR_RIE_RRP }, 1257 { "crb", 0xf6, INSTR_RRS_RRRDU }, 1258 { "cgrb", 0xe4, INSTR_RRS_RRRDU }, 1259 { "crj", 0x76, INSTR_RIE_RRPU }, 1260 { "cgrj", 0x64, INSTR_RIE_RRPU }, 1261 { "cib", 0xfe, INSTR_RIS_RURDI }, 1262 { "cgib", 0xfc, INSTR_RIS_RURDI }, 1263 { "cij", 0x7e, INSTR_RIE_RUPI }, 1264 { "cgij", 0x7c, INSTR_RIE_RUPI }, 1265 { "cit", 0x72, INSTR_RIE_R0IU }, 1266 { "cgit", 0x70, INSTR_RIE_R0IU }, 1267 { "clrb", 0xf7, INSTR_RRS_RRRDU }, 1268 { "clgrb", 0xe5, INSTR_RRS_RRRDU }, 1269 { "clrj", 0x77, INSTR_RIE_RRPU }, 1270 { "clgrj", 0x65, INSTR_RIE_RRPU }, 1271 { "clib", 0xff, INSTR_RIS_RURDU }, 1272 { "clgib", 0xfd, INSTR_RIS_RURDU }, 1273 { "clij", 0x7f, INSTR_RIE_RUPU }, 1274 { "clgij", 0x7d, INSTR_RIE_RUPU }, 1275 { "clfit", 0x73, INSTR_RIE_R0UU }, 1276 { "clgit", 0x71, INSTR_RIE_R0UU }, 1277 { "rnsbg", 0x54, INSTR_RIE_RRUUU }, 1278 { "rxsbg", 0x57, INSTR_RIE_RRUUU }, 1279 { "rosbg", 0x56, INSTR_RIE_RRUUU }, 1280 { "risbg", 0x55, INSTR_RIE_RRUUU }, 1281 { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU }, 1282 { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU }, 1283 { "ahik", 0xd8, INSTR_RIE_RRI0 }, 1284 { "aghik", 0xd9, INSTR_RIE_RRI0 }, 1285 { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, 1286 { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, 1287 #endif 1288 { "", 0, INSTR_INVALID } 1289 }; 1290 1291 static struct insn opcode_ed[] = { 1292 #ifdef CONFIG_64BIT 1293 { "mayl", 0x38, INSTR_RXF_FRRDF }, 1294 { "myl", 0x39, INSTR_RXF_FRRDF }, 1295 { "may", 0x3a, INSTR_RXF_FRRDF }, 1296 { "my", 0x3b, INSTR_RXF_FRRDF }, 1297 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1298 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1299 { "ley", 0x64, INSTR_RXY_FRRD }, 1300 { "ldy", 0x65, INSTR_RXY_FRRD }, 1301 { "stey", 0x66, INSTR_RXY_FRRD }, 1302 { "stdy", 0x67, INSTR_RXY_FRRD }, 1303 { "sldt", 0x40, INSTR_RXF_FRRDF }, 1304 { "slxt", 0x48, INSTR_RXF_FRRDF }, 1305 { "srdt", 0x41, INSTR_RXF_FRRDF }, 1306 { "srxt", 0x49, INSTR_RXF_FRRDF }, 1307 { "tdcet", 0x50, INSTR_RXE_FRRD }, 1308 { "tdcdt", 0x54, INSTR_RXE_FRRD }, 1309 { "tdcxt", 0x58, INSTR_RXE_FRRD }, 1310 { "tdget", 0x51, INSTR_RXE_FRRD }, 1311 { "tdgdt", 0x55, INSTR_RXE_FRRD }, 1312 { "tdgxt", 0x59, INSTR_RXE_FRRD }, 1313 #endif 1314 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1315 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1316 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1317 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1318 { "keb", 0x08, INSTR_RXE_FRRD }, 1319 { "ceb", 0x09, INSTR_RXE_FRRD }, 1320 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1321 { "seb", 0x0b, INSTR_RXE_FRRD }, 1322 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1323 { "deb", 0x0d, INSTR_RXE_FRRD }, 1324 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1325 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1326 { "tceb", 0x10, INSTR_RXE_FRRD }, 1327 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1328 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1329 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1330 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1331 { "meeb", 0x17, INSTR_RXE_FRRD }, 1332 { "kdb", 0x18, INSTR_RXE_FRRD }, 1333 { "cdb", 0x19, INSTR_RXE_FRRD }, 1334 { "adb", 0x1a, INSTR_RXE_FRRD }, 1335 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1336 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1337 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1338 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1339 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1340 { "lde", 0x24, INSTR_RXE_FRRD }, 1341 { "lxd", 0x25, INSTR_RXE_FRRD }, 1342 { "lxe", 0x26, INSTR_RXE_FRRD }, 1343 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1344 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1345 { "sqe", 0x34, INSTR_RXE_FRRD }, 1346 { "sqd", 0x35, INSTR_RXE_FRRD }, 1347 { "mee", 0x37, INSTR_RXE_FRRD }, 1348 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1349 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1350 { "", 0, INSTR_INVALID } 1351 }; 1352 1353 /* Extracts an operand value from an instruction. */ 1354 static unsigned int extract_operand(unsigned char *code, 1355 const struct operand *operand) 1356 { 1357 unsigned int val; 1358 int bits; 1359 1360 /* Extract fragments of the operand byte for byte. */ 1361 code += operand->shift / 8; 1362 bits = (operand->shift & 7) + operand->bits; 1363 val = 0; 1364 do { 1365 val <<= 8; 1366 val |= (unsigned int) *code++; 1367 bits -= 8; 1368 } while (bits > 0); 1369 val >>= -bits; 1370 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1371 1372 /* Check for special long displacement case. */ 1373 if (operand->bits == 20 && operand->shift == 20) 1374 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1375 1376 /* Sign extend value if the operand is signed or pc relative. */ 1377 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1378 (val & (1U << (operand->bits - 1)))) 1379 val |= (-1U << (operand->bits - 1)) << 1; 1380 1381 /* Double value if the operand is pc relative. */ 1382 if (operand->flags & OPERAND_PCREL) 1383 val <<= 1; 1384 1385 /* Length x in an instructions has real length x + 1. */ 1386 if (operand->flags & OPERAND_LENGTH) 1387 val++; 1388 return val; 1389 } 1390 1391 static inline int insn_length(unsigned char code) 1392 { 1393 return ((((int) code + 64) >> 7) + 1) << 1; 1394 } 1395 1396 static struct insn *find_insn(unsigned char *code) 1397 { 1398 unsigned char opfrag = code[1]; 1399 unsigned char opmask; 1400 struct insn *table; 1401 1402 switch (code[0]) { 1403 case 0x01: 1404 table = opcode_01; 1405 break; 1406 case 0xa5: 1407 table = opcode_a5; 1408 break; 1409 case 0xa7: 1410 table = opcode_a7; 1411 break; 1412 case 0xb2: 1413 table = opcode_b2; 1414 break; 1415 case 0xb3: 1416 table = opcode_b3; 1417 break; 1418 case 0xb9: 1419 table = opcode_b9; 1420 break; 1421 case 0xc0: 1422 table = opcode_c0; 1423 break; 1424 case 0xc2: 1425 table = opcode_c2; 1426 break; 1427 case 0xc4: 1428 table = opcode_c4; 1429 break; 1430 case 0xc6: 1431 table = opcode_c6; 1432 break; 1433 case 0xc8: 1434 table = opcode_c8; 1435 break; 1436 case 0xcc: 1437 table = opcode_cc; 1438 break; 1439 case 0xe3: 1440 table = opcode_e3; 1441 opfrag = code[5]; 1442 break; 1443 case 0xe5: 1444 table = opcode_e5; 1445 break; 1446 case 0xeb: 1447 table = opcode_eb; 1448 opfrag = code[5]; 1449 break; 1450 case 0xec: 1451 table = opcode_ec; 1452 opfrag = code[5]; 1453 break; 1454 case 0xed: 1455 table = opcode_ed; 1456 opfrag = code[5]; 1457 break; 1458 default: 1459 table = opcode; 1460 opfrag = code[0]; 1461 break; 1462 } 1463 while (table->format != INSTR_INVALID) { 1464 opmask = formats[table->format][0]; 1465 if (table->opfrag == (opfrag & opmask)) 1466 return table; 1467 table++; 1468 } 1469 return NULL; 1470 } 1471 1472 static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1473 { 1474 struct insn *insn; 1475 const unsigned char *ops; 1476 const struct operand *operand; 1477 unsigned int value; 1478 char separator; 1479 char *ptr; 1480 int i; 1481 1482 ptr = buffer; 1483 insn = find_insn(code); 1484 if (insn) { 1485 if (insn->name[0] == '\0') 1486 ptr += sprintf(ptr, "%s\t", 1487 long_insn_name[(int) insn->name[1]]); 1488 else 1489 ptr += sprintf(ptr, "%.5s\t", insn->name); 1490 /* Extract the operands. */ 1491 separator = 0; 1492 for (ops = formats[insn->format] + 1, i = 0; 1493 *ops != 0 && i < 6; ops++, i++) { 1494 operand = operands + *ops; 1495 value = extract_operand(code, operand); 1496 if ((operand->flags & OPERAND_INDEX) && value == 0) 1497 continue; 1498 if ((operand->flags & OPERAND_BASE) && 1499 value == 0 && separator == '(') { 1500 separator = ','; 1501 continue; 1502 } 1503 if (separator) 1504 ptr += sprintf(ptr, "%c", separator); 1505 if (operand->flags & OPERAND_GPR) 1506 ptr += sprintf(ptr, "%%r%i", value); 1507 else if (operand->flags & OPERAND_FPR) 1508 ptr += sprintf(ptr, "%%f%i", value); 1509 else if (operand->flags & OPERAND_AR) 1510 ptr += sprintf(ptr, "%%a%i", value); 1511 else if (operand->flags & OPERAND_CR) 1512 ptr += sprintf(ptr, "%%c%i", value); 1513 else if (operand->flags & OPERAND_PCREL) 1514 ptr += sprintf(ptr, "%lx", (signed int) value 1515 + addr); 1516 else if (operand->flags & OPERAND_SIGNED) 1517 ptr += sprintf(ptr, "%i", value); 1518 else 1519 ptr += sprintf(ptr, "%u", value); 1520 if (operand->flags & OPERAND_DISP) 1521 separator = '('; 1522 else if (operand->flags & OPERAND_BASE) { 1523 ptr += sprintf(ptr, ")"); 1524 separator = ','; 1525 } else 1526 separator = ','; 1527 } 1528 } else 1529 ptr += sprintf(ptr, "unknown"); 1530 return (int) (ptr - buffer); 1531 } 1532 1533 void show_code(struct pt_regs *regs) 1534 { 1535 char *mode = (regs->psw.mask & PSW_MASK_PSTATE) ? "User" : "Krnl"; 1536 unsigned char code[64]; 1537 char buffer[64], *ptr; 1538 mm_segment_t old_fs; 1539 unsigned long addr; 1540 int start, end, opsize, hops, i; 1541 1542 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 1543 old_fs = get_fs(); 1544 set_fs((regs->psw.mask & PSW_MASK_PSTATE) ? USER_DS : KERNEL_DS); 1545 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 1546 addr = regs->psw.addr - 34 + start; 1547 if (__copy_from_user(code + start - 2, 1548 (char __user *) addr, 2)) 1549 break; 1550 } 1551 for (end = 32; end < 64; end += 2) { 1552 addr = regs->psw.addr + end - 32; 1553 if (__copy_from_user(code + end, 1554 (char __user *) addr, 2)) 1555 break; 1556 } 1557 set_fs(old_fs); 1558 /* Code snapshot useable ? */ 1559 if ((regs->psw.addr & 1) || start >= end) { 1560 printk("%s Code: Bad PSW.\n", mode); 1561 return; 1562 } 1563 /* Find a starting point for the disassembly. */ 1564 while (start < 32) { 1565 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 1566 if (!find_insn(code + start + i)) 1567 break; 1568 i += insn_length(code[start + i]); 1569 } 1570 if (start + i == 32) 1571 /* Looks good, sequence ends at PSW. */ 1572 break; 1573 start += 2; 1574 } 1575 /* Decode the instructions. */ 1576 ptr = buffer; 1577 ptr += sprintf(ptr, "%s Code:", mode); 1578 hops = 0; 1579 while (start < end && hops < 8) { 1580 *ptr++ = (start == 32) ? '>' : ' '; 1581 addr = regs->psw.addr + start - 32; 1582 ptr += sprintf(ptr, ONELONG, addr); 1583 opsize = insn_length(code[start]); 1584 if (start + opsize >= end) 1585 break; 1586 for (i = 0; i < opsize; i++) 1587 ptr += sprintf(ptr, "%02x", code[start + i]); 1588 *ptr++ = '\t'; 1589 if (i < 6) 1590 *ptr++ = '\t'; 1591 ptr += print_insn(ptr, code + start, addr); 1592 start += opsize; 1593 printk(buffer); 1594 ptr = buffer; 1595 ptr += sprintf(ptr, "\n "); 1596 hops++; 1597 } 1598 printk("\n"); 1599 } 1600