1 /* 2 * Disassemble s390 instructions. 3 * 4 * Copyright IBM Corp. 2007 5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), 6 */ 7 8 #include <linux/sched.h> 9 #include <linux/kernel.h> 10 #include <linux/string.h> 11 #include <linux/errno.h> 12 #include <linux/ptrace.h> 13 #include <linux/timer.h> 14 #include <linux/mm.h> 15 #include <linux/smp.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/module.h> 20 #include <linux/kallsyms.h> 21 #include <linux/reboot.h> 22 #include <linux/kprobes.h> 23 #include <linux/kdebug.h> 24 25 #include <asm/uaccess.h> 26 #include <asm/io.h> 27 #include <linux/atomic.h> 28 #include <asm/mathemu.h> 29 #include <asm/cpcmd.h> 30 #include <asm/lowcore.h> 31 #include <asm/debug.h> 32 #include <asm/irq.h> 33 34 #ifndef CONFIG_64BIT 35 #define ONELONG "%08lx: " 36 #else /* CONFIG_64BIT */ 37 #define ONELONG "%016lx: " 38 #endif /* CONFIG_64BIT */ 39 40 #define OPERAND_GPR 0x1 /* Operand printed as %rx */ 41 #define OPERAND_FPR 0x2 /* Operand printed as %fx */ 42 #define OPERAND_AR 0x4 /* Operand printed as %ax */ 43 #define OPERAND_CR 0x8 /* Operand printed as %cx */ 44 #define OPERAND_DISP 0x10 /* Operand printed as displacement */ 45 #define OPERAND_BASE 0x20 /* Operand printed as base register */ 46 #define OPERAND_INDEX 0x40 /* Operand printed as index register */ 47 #define OPERAND_PCREL 0x80 /* Operand printed as pc-relative symbol */ 48 #define OPERAND_SIGNED 0x100 /* Operand printed as signed value */ 49 #define OPERAND_LENGTH 0x200 /* Operand printed as length (+1) */ 50 51 enum { 52 UNUSED, /* Indicates the end of the operand list */ 53 R_8, /* GPR starting at position 8 */ 54 R_12, /* GPR starting at position 12 */ 55 R_16, /* GPR starting at position 16 */ 56 R_20, /* GPR starting at position 20 */ 57 R_24, /* GPR starting at position 24 */ 58 R_28, /* GPR starting at position 28 */ 59 R_32, /* GPR starting at position 32 */ 60 F_8, /* FPR starting at position 8 */ 61 F_12, /* FPR starting at position 12 */ 62 F_16, /* FPR starting at position 16 */ 63 F_20, /* FPR starting at position 16 */ 64 F_24, /* FPR starting at position 24 */ 65 F_28, /* FPR starting at position 28 */ 66 F_32, /* FPR starting at position 32 */ 67 A_8, /* Access reg. starting at position 8 */ 68 A_12, /* Access reg. starting at position 12 */ 69 A_24, /* Access reg. starting at position 24 */ 70 A_28, /* Access reg. starting at position 28 */ 71 C_8, /* Control reg. starting at position 8 */ 72 C_12, /* Control reg. starting at position 12 */ 73 B_16, /* Base register starting at position 16 */ 74 B_32, /* Base register starting at position 32 */ 75 X_12, /* Index register starting at position 12 */ 76 D_20, /* Displacement starting at position 20 */ 77 D_36, /* Displacement starting at position 36 */ 78 D20_20, /* 20 bit displacement starting at 20 */ 79 L4_8, /* 4 bit length starting at position 8 */ 80 L4_12, /* 4 bit length starting at position 12 */ 81 L8_8, /* 8 bit length starting at position 8 */ 82 U4_8, /* 4 bit unsigned value starting at 8 */ 83 U4_12, /* 4 bit unsigned value starting at 12 */ 84 U4_16, /* 4 bit unsigned value starting at 16 */ 85 U4_20, /* 4 bit unsigned value starting at 20 */ 86 U4_24, /* 4 bit unsigned value starting at 24 */ 87 U4_28, /* 4 bit unsigned value starting at 28 */ 88 U4_32, /* 4 bit unsigned value starting at 32 */ 89 U4_36, /* 4 bit unsigned value starting at 36 */ 90 U8_8, /* 8 bit unsigned value starting at 8 */ 91 U8_16, /* 8 bit unsigned value starting at 16 */ 92 U8_24, /* 8 bit unsigned value starting at 24 */ 93 U8_32, /* 8 bit unsigned value starting at 32 */ 94 I8_8, /* 8 bit signed value starting at 8 */ 95 I8_32, /* 8 bit signed value starting at 32 */ 96 J12_12, /* PC relative offset at 12 */ 97 I16_16, /* 16 bit signed value starting at 16 */ 98 I16_32, /* 32 bit signed value starting at 16 */ 99 U16_16, /* 16 bit unsigned value starting at 16 */ 100 U16_32, /* 32 bit unsigned value starting at 16 */ 101 J16_16, /* PC relative jump offset at 16 */ 102 J16_32, /* PC relative offset at 16 */ 103 I24_24, /* 24 bit signed value starting at 24 */ 104 J32_16, /* PC relative long offset at 16 */ 105 I32_16, /* 32 bit signed value starting at 16 */ 106 U32_16, /* 32 bit unsigned value starting at 16 */ 107 M_16, /* 4 bit optional mask starting at 16 */ 108 M_20, /* 4 bit optional mask starting at 20 */ 109 RO_28, /* optional GPR starting at position 28 */ 110 }; 111 112 /* 113 * Enumeration of the different instruction formats. 114 * For details consult the principles of operation. 115 */ 116 enum { 117 INSTR_INVALID, 118 INSTR_E, 119 INSTR_IE_UU, 120 INSTR_MII_UPI, 121 INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU, 122 INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU, INSTR_RIE_RRI0, 123 INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP, 124 INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU, 125 INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP, 126 INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0, 127 INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, 128 INSTR_RRE_RR, INSTR_RRE_RR_OPT, 129 INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, 130 INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_FUFF2, INSTR_RRF_M0RR, 131 INSTR_RRF_R0RR, INSTR_RRF_R0RR2, INSTR_RRF_RMRR, INSTR_RRF_RURR, 132 INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR, INSTR_RRF_UUFF, 133 INSTR_RRF_UUFR, INSTR_RRF_UURF, 134 INSTR_RRR_F0FF, INSTR_RRS_RRRDU, 135 INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR, 136 INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, 137 INSTR_RSI_RRP, 138 INSTR_RSL_LRDFU, INSTR_RSL_R0RD, 139 INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD, 140 INSTR_RSY_RDRM, 141 INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD, 142 INSTR_RS_RURD, 143 INSTR_RXE_FRRD, INSTR_RXE_RRRD, 144 INSTR_RXF_FRRDF, 145 INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD, 146 INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD, 147 INSTR_SIL_RDI, INSTR_SIL_RDU, 148 INSTR_SIY_IRD, INSTR_SIY_URD, 149 INSTR_SI_URD, 150 INSTR_SMI_U0RDP, 151 INSTR_SSE_RDRD, 152 INSTR_SSF_RRDRD, INSTR_SSF_RRDRD2, 153 INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, 154 INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3, 155 INSTR_S_00, INSTR_S_RD, 156 }; 157 158 struct operand { 159 int bits; /* The number of bits in the operand. */ 160 int shift; /* The number of bits to shift. */ 161 int flags; /* One bit syntax flags. */ 162 }; 163 164 struct insn { 165 const char name[5]; 166 unsigned char opfrag; 167 unsigned char format; 168 }; 169 170 static const struct operand operands[] = 171 { 172 [UNUSED] = { 0, 0, 0 }, 173 [R_8] = { 4, 8, OPERAND_GPR }, 174 [R_12] = { 4, 12, OPERAND_GPR }, 175 [R_16] = { 4, 16, OPERAND_GPR }, 176 [R_20] = { 4, 20, OPERAND_GPR }, 177 [R_24] = { 4, 24, OPERAND_GPR }, 178 [R_28] = { 4, 28, OPERAND_GPR }, 179 [R_32] = { 4, 32, OPERAND_GPR }, 180 [F_8] = { 4, 8, OPERAND_FPR }, 181 [F_12] = { 4, 12, OPERAND_FPR }, 182 [F_16] = { 4, 16, OPERAND_FPR }, 183 [F_20] = { 4, 16, OPERAND_FPR }, 184 [F_24] = { 4, 24, OPERAND_FPR }, 185 [F_28] = { 4, 28, OPERAND_FPR }, 186 [F_32] = { 4, 32, OPERAND_FPR }, 187 [A_8] = { 4, 8, OPERAND_AR }, 188 [A_12] = { 4, 12, OPERAND_AR }, 189 [A_24] = { 4, 24, OPERAND_AR }, 190 [A_28] = { 4, 28, OPERAND_AR }, 191 [C_8] = { 4, 8, OPERAND_CR }, 192 [C_12] = { 4, 12, OPERAND_CR }, 193 [B_16] = { 4, 16, OPERAND_BASE | OPERAND_GPR }, 194 [B_32] = { 4, 32, OPERAND_BASE | OPERAND_GPR }, 195 [X_12] = { 4, 12, OPERAND_INDEX | OPERAND_GPR }, 196 [D_20] = { 12, 20, OPERAND_DISP }, 197 [D_36] = { 12, 36, OPERAND_DISP }, 198 [D20_20] = { 20, 20, OPERAND_DISP | OPERAND_SIGNED }, 199 [L4_8] = { 4, 8, OPERAND_LENGTH }, 200 [L4_12] = { 4, 12, OPERAND_LENGTH }, 201 [L8_8] = { 8, 8, OPERAND_LENGTH }, 202 [U4_8] = { 4, 8, 0 }, 203 [U4_12] = { 4, 12, 0 }, 204 [U4_16] = { 4, 16, 0 }, 205 [U4_20] = { 4, 20, 0 }, 206 [U4_24] = { 4, 24, 0 }, 207 [U4_28] = { 4, 28, 0 }, 208 [U4_32] = { 4, 32, 0 }, 209 [U4_36] = { 4, 36, 0 }, 210 [U8_8] = { 8, 8, 0 }, 211 [U8_16] = { 8, 16, 0 }, 212 [U8_24] = { 8, 24, 0 }, 213 [U8_32] = { 8, 32, 0 }, 214 [J12_12] = { 12, 12, OPERAND_PCREL }, 215 [I16_16] = { 16, 16, OPERAND_SIGNED }, 216 [U16_16] = { 16, 16, 0 }, 217 [U16_32] = { 16, 32, 0 }, 218 [J16_16] = { 16, 16, OPERAND_PCREL }, 219 [J16_32] = { 16, 32, OPERAND_PCREL }, 220 [I16_32] = { 16, 32, OPERAND_SIGNED }, 221 [I24_24] = { 24, 24, OPERAND_SIGNED }, 222 [J32_16] = { 32, 16, OPERAND_PCREL }, 223 [I32_16] = { 32, 16, OPERAND_SIGNED }, 224 [U32_16] = { 32, 16, 0 }, 225 [M_16] = { 4, 16, 0 }, 226 [M_20] = { 4, 20, 0 }, 227 [RO_28] = { 4, 28, OPERAND_GPR } 228 }; 229 230 static const unsigned char formats[][7] = { 231 [INSTR_E] = { 0xff, 0,0,0,0,0,0 }, 232 [INSTR_IE_UU] = { 0xff, U4_24,U4_28,0,0,0,0 }, 233 [INSTR_MII_UPI] = { 0xff, U4_8,J12_12,I24_24 }, 234 [INSTR_RIE_R0IU] = { 0xff, R_8,I16_16,U4_32,0,0,0 }, 235 [INSTR_RIE_R0UU] = { 0xff, R_8,U16_16,U4_32,0,0,0 }, 236 [INSTR_RIE_RRI0] = { 0xff, R_8,R_12,I16_16,0,0,0 }, 237 [INSTR_RIE_RRPU] = { 0xff, R_8,R_12,U4_32,J16_16,0,0 }, 238 [INSTR_RIE_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 239 [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 }, 240 [INSTR_RIE_RUPI] = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 }, 241 [INSTR_RIE_RUPU] = { 0xff, R_8,U8_32,U4_12,J16_16,0,0 }, 242 [INSTR_RIL_RI] = { 0x0f, R_8,I32_16,0,0,0,0 }, 243 [INSTR_RIL_RP] = { 0x0f, R_8,J32_16,0,0,0,0 }, 244 [INSTR_RIL_RU] = { 0x0f, R_8,U32_16,0,0,0,0 }, 245 [INSTR_RIL_UP] = { 0x0f, U4_8,J32_16,0,0,0,0 }, 246 [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 }, 247 [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 }, 248 [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 }, 249 [INSTR_RI_RI] = { 0x0f, R_8,I16_16,0,0,0,0 }, 250 [INSTR_RI_RP] = { 0x0f, R_8,J16_16,0,0,0,0 }, 251 [INSTR_RI_RU] = { 0x0f, R_8,U16_16,0,0,0,0 }, 252 [INSTR_RI_UP] = { 0x0f, U4_8,J16_16,0,0,0,0 }, 253 [INSTR_RRE_00] = { 0xff, 0,0,0,0,0,0 }, 254 [INSTR_RRE_0R] = { 0xff, R_28,0,0,0,0,0 }, 255 [INSTR_RRE_AA] = { 0xff, A_24,A_28,0,0,0,0 }, 256 [INSTR_RRE_AR] = { 0xff, A_24,R_28,0,0,0,0 }, 257 [INSTR_RRE_F0] = { 0xff, F_24,0,0,0,0,0 }, 258 [INSTR_RRE_FF] = { 0xff, F_24,F_28,0,0,0,0 }, 259 [INSTR_RRE_FR] = { 0xff, F_24,R_28,0,0,0,0 }, 260 [INSTR_RRE_R0] = { 0xff, R_24,0,0,0,0,0 }, 261 [INSTR_RRE_RA] = { 0xff, R_24,A_28,0,0,0,0 }, 262 [INSTR_RRE_RF] = { 0xff, R_24,F_28,0,0,0,0 }, 263 [INSTR_RRE_RR] = { 0xff, R_24,R_28,0,0,0,0 }, 264 [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 }, 265 [INSTR_RRF_0UFF] = { 0xff, F_24,F_28,U4_20,0,0,0 }, 266 [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 }, 267 [INSTR_RRF_F0FF] = { 0xff, F_16,F_24,F_28,0,0,0 }, 268 [INSTR_RRF_F0FR] = { 0xff, F_24,F_16,R_28,0,0,0 }, 269 [INSTR_RRF_FFRU] = { 0xff, F_24,F_16,R_28,U4_20,0,0 }, 270 [INSTR_RRF_FUFF] = { 0xff, F_24,F_16,F_28,U4_20,0,0 }, 271 [INSTR_RRF_FUFF2] = { 0xff, F_24,F_28,F_16,U4_20,0,0 }, 272 [INSTR_RRF_M0RR] = { 0xff, R_24,R_28,M_16,0,0,0 }, 273 [INSTR_RRF_R0RR] = { 0xff, R_24,R_16,R_28,0,0,0 }, 274 [INSTR_RRF_R0RR2] = { 0xff, R_24,R_28,R_16,0,0,0 }, 275 [INSTR_RRF_RMRR] = { 0xff, R_24,R_16,R_28,M_20,0,0 }, 276 [INSTR_RRF_RURR] = { 0xff, R_24,R_28,R_16,U4_20,0,0 }, 277 [INSTR_RRF_U0FF] = { 0xff, F_24,U4_16,F_28,0,0,0 }, 278 [INSTR_RRF_U0RF] = { 0xff, R_24,U4_16,F_28,0,0,0 }, 279 [INSTR_RRF_U0RR] = { 0xff, R_24,R_28,U4_16,0,0,0 }, 280 [INSTR_RRF_UUFF] = { 0xff, F_24,U4_16,F_28,U4_20,0,0 }, 281 [INSTR_RRF_UUFR] = { 0xff, F_24,U4_16,R_28,U4_20,0,0 }, 282 [INSTR_RRF_UURF] = { 0xff, R_24,U4_16,F_28,U4_20,0,0 }, 283 [INSTR_RRR_F0FF] = { 0xff, F_24,F_28,F_16,0,0,0 }, 284 [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 }, 285 [INSTR_RR_FF] = { 0xff, F_8,F_12,0,0,0,0 }, 286 [INSTR_RR_R0] = { 0xff, R_8, 0,0,0,0,0 }, 287 [INSTR_RR_RR] = { 0xff, R_8,R_12,0,0,0,0 }, 288 [INSTR_RR_U0] = { 0xff, U8_8, 0,0,0,0,0 }, 289 [INSTR_RR_UR] = { 0xff, U4_8,R_12,0,0,0,0 }, 290 [INSTR_RSE_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 291 [INSTR_RSE_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 292 [INSTR_RSE_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 293 [INSTR_RSI_RRP] = { 0xff, R_8,R_12,J16_16,0,0,0 }, 294 [INSTR_RSL_LRDFU] = { 0xff, F_32,D_20,L4_8,B_16,U4_36,0 }, 295 [INSTR_RSL_R0RD] = { 0xff, D_20,L4_8,B_16,0,0,0 }, 296 [INSTR_RSY_AARD] = { 0xff, A_8,A_12,D20_20,B_16,0,0 }, 297 [INSTR_RSY_CCRD] = { 0xff, C_8,C_12,D20_20,B_16,0,0 }, 298 [INSTR_RSY_RDRM] = { 0xff, R_8,D20_20,B_16,U4_12,0,0 }, 299 [INSTR_RSY_RRRD] = { 0xff, R_8,R_12,D20_20,B_16,0,0 }, 300 [INSTR_RSY_RURD] = { 0xff, R_8,U4_12,D20_20,B_16,0,0 }, 301 [INSTR_RS_AARD] = { 0xff, A_8,A_12,D_20,B_16,0,0 }, 302 [INSTR_RS_CCRD] = { 0xff, C_8,C_12,D_20,B_16,0,0 }, 303 [INSTR_RS_R0RD] = { 0xff, R_8,D_20,B_16,0,0,0 }, 304 [INSTR_RS_RRRD] = { 0xff, R_8,R_12,D_20,B_16,0,0 }, 305 [INSTR_RS_RURD] = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, 306 [INSTR_RXE_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 307 [INSTR_RXE_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 308 [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 }, 309 [INSTR_RXY_FRRD] = { 0xff, F_8,D20_20,X_12,B_16,0,0 }, 310 [INSTR_RXY_RRRD] = { 0xff, R_8,D20_20,X_12,B_16,0,0 }, 311 [INSTR_RXY_URRD] = { 0xff, U4_8,D20_20,X_12,B_16,0,0 }, 312 [INSTR_RX_FRRD] = { 0xff, F_8,D_20,X_12,B_16,0,0 }, 313 [INSTR_RX_RRRD] = { 0xff, R_8,D_20,X_12,B_16,0,0 }, 314 [INSTR_RX_URRD] = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, 315 [INSTR_SIL_RDI] = { 0xff, D_20,B_16,I16_32,0,0,0 }, 316 [INSTR_SIL_RDU] = { 0xff, D_20,B_16,U16_32,0,0,0 }, 317 [INSTR_SIY_IRD] = { 0xff, D20_20,B_16,I8_8,0,0,0 }, 318 [INSTR_SIY_URD] = { 0xff, D20_20,B_16,U8_8,0,0,0 }, 319 [INSTR_SI_URD] = { 0xff, D_20,B_16,U8_8,0,0,0 }, 320 [INSTR_SMI_U0RDP] = { 0xff, U4_8,J16_32,D_20,B_16,0,0 }, 321 [INSTR_SSE_RDRD] = { 0xff, D_20,B_16,D_36,B_32,0,0 }, 322 [INSTR_SSF_RRDRD] = { 0x0f, D_20,B_16,D_36,B_32,R_8,0 }, 323 [INSTR_SSF_RRDRD2]= { 0x0f, R_8,D_20,B_16,D_36,B_32,0 }, 324 [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 }, 325 [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 }, 326 [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 }, 327 [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 }, 328 [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 }, 329 [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 }, 330 [INSTR_S_00] = { 0xff, 0,0,0,0,0,0 }, 331 [INSTR_S_RD] = { 0xff, D_20,B_16,0,0,0,0 }, 332 }; 333 334 enum { 335 LONG_INSN_ALGHSIK, 336 LONG_INSN_ALHHHR, 337 LONG_INSN_ALHHLR, 338 LONG_INSN_ALHSIK, 339 LONG_INSN_ALSIHN, 340 LONG_INSN_CDFBRA, 341 LONG_INSN_CDGBRA, 342 LONG_INSN_CDGTRA, 343 LONG_INSN_CDLFBR, 344 LONG_INSN_CDLFTR, 345 LONG_INSN_CDLGBR, 346 LONG_INSN_CDLGTR, 347 LONG_INSN_CEFBRA, 348 LONG_INSN_CEGBRA, 349 LONG_INSN_CELFBR, 350 LONG_INSN_CELGBR, 351 LONG_INSN_CFDBRA, 352 LONG_INSN_CFEBRA, 353 LONG_INSN_CFXBRA, 354 LONG_INSN_CGDBRA, 355 LONG_INSN_CGDTRA, 356 LONG_INSN_CGEBRA, 357 LONG_INSN_CGXBRA, 358 LONG_INSN_CGXTRA, 359 LONG_INSN_CLFDBR, 360 LONG_INSN_CLFDTR, 361 LONG_INSN_CLFEBR, 362 LONG_INSN_CLFHSI, 363 LONG_INSN_CLFXBR, 364 LONG_INSN_CLFXTR, 365 LONG_INSN_CLGDBR, 366 LONG_INSN_CLGDTR, 367 LONG_INSN_CLGEBR, 368 LONG_INSN_CLGFRL, 369 LONG_INSN_CLGHRL, 370 LONG_INSN_CLGHSI, 371 LONG_INSN_CLGXBR, 372 LONG_INSN_CLGXTR, 373 LONG_INSN_CLHHSI, 374 LONG_INSN_CXFBRA, 375 LONG_INSN_CXGBRA, 376 LONG_INSN_CXGTRA, 377 LONG_INSN_CXLFBR, 378 LONG_INSN_CXLFTR, 379 LONG_INSN_CXLGBR, 380 LONG_INSN_CXLGTR, 381 LONG_INSN_FIDBRA, 382 LONG_INSN_FIEBRA, 383 LONG_INSN_FIXBRA, 384 LONG_INSN_LDXBRA, 385 LONG_INSN_LEDBRA, 386 LONG_INSN_LEXBRA, 387 LONG_INSN_LLGFAT, 388 LONG_INSN_LLGFRL, 389 LONG_INSN_LLGHRL, 390 LONG_INSN_LLGTAT, 391 LONG_INSN_POPCNT, 392 LONG_INSN_RIEMIT, 393 LONG_INSN_RINEXT, 394 LONG_INSN_RISBGN, 395 LONG_INSN_RISBHG, 396 LONG_INSN_RISBLG, 397 LONG_INSN_SLHHHR, 398 LONG_INSN_SLHHLR, 399 LONG_INSN_TABORT, 400 LONG_INSN_TBEGIN, 401 LONG_INSN_TBEGINC, 402 LONG_INSN_PCISTG, 403 LONG_INSN_MPCIFC, 404 LONG_INSN_STPCIFC, 405 LONG_INSN_PCISTB, 406 }; 407 408 static char *long_insn_name[] = { 409 [LONG_INSN_ALGHSIK] = "alghsik", 410 [LONG_INSN_ALHHHR] = "alhhhr", 411 [LONG_INSN_ALHHLR] = "alhhlr", 412 [LONG_INSN_ALHSIK] = "alhsik", 413 [LONG_INSN_ALSIHN] = "alsihn", 414 [LONG_INSN_CDFBRA] = "cdfbra", 415 [LONG_INSN_CDGBRA] = "cdgbra", 416 [LONG_INSN_CDGTRA] = "cdgtra", 417 [LONG_INSN_CDLFBR] = "cdlfbr", 418 [LONG_INSN_CDLFTR] = "cdlftr", 419 [LONG_INSN_CDLGBR] = "cdlgbr", 420 [LONG_INSN_CDLGTR] = "cdlgtr", 421 [LONG_INSN_CEFBRA] = "cefbra", 422 [LONG_INSN_CEGBRA] = "cegbra", 423 [LONG_INSN_CELFBR] = "celfbr", 424 [LONG_INSN_CELGBR] = "celgbr", 425 [LONG_INSN_CFDBRA] = "cfdbra", 426 [LONG_INSN_CFEBRA] = "cfebra", 427 [LONG_INSN_CFXBRA] = "cfxbra", 428 [LONG_INSN_CGDBRA] = "cgdbra", 429 [LONG_INSN_CGDTRA] = "cgdtra", 430 [LONG_INSN_CGEBRA] = "cgebra", 431 [LONG_INSN_CGXBRA] = "cgxbra", 432 [LONG_INSN_CGXTRA] = "cgxtra", 433 [LONG_INSN_CLFDBR] = "clfdbr", 434 [LONG_INSN_CLFDTR] = "clfdtr", 435 [LONG_INSN_CLFEBR] = "clfebr", 436 [LONG_INSN_CLFHSI] = "clfhsi", 437 [LONG_INSN_CLFXBR] = "clfxbr", 438 [LONG_INSN_CLFXTR] = "clfxtr", 439 [LONG_INSN_CLGDBR] = "clgdbr", 440 [LONG_INSN_CLGDTR] = "clgdtr", 441 [LONG_INSN_CLGEBR] = "clgebr", 442 [LONG_INSN_CLGFRL] = "clgfrl", 443 [LONG_INSN_CLGHRL] = "clghrl", 444 [LONG_INSN_CLGHSI] = "clghsi", 445 [LONG_INSN_CLGXBR] = "clgxbr", 446 [LONG_INSN_CLGXTR] = "clgxtr", 447 [LONG_INSN_CLHHSI] = "clhhsi", 448 [LONG_INSN_CXFBRA] = "cxfbra", 449 [LONG_INSN_CXGBRA] = "cxgbra", 450 [LONG_INSN_CXGTRA] = "cxgtra", 451 [LONG_INSN_CXLFBR] = "cxlfbr", 452 [LONG_INSN_CXLFTR] = "cxlftr", 453 [LONG_INSN_CXLGBR] = "cxlgbr", 454 [LONG_INSN_CXLGTR] = "cxlgtr", 455 [LONG_INSN_FIDBRA] = "fidbra", 456 [LONG_INSN_FIEBRA] = "fiebra", 457 [LONG_INSN_FIXBRA] = "fixbra", 458 [LONG_INSN_LDXBRA] = "ldxbra", 459 [LONG_INSN_LEDBRA] = "ledbra", 460 [LONG_INSN_LEXBRA] = "lexbra", 461 [LONG_INSN_LLGFAT] = "llgfat", 462 [LONG_INSN_LLGFRL] = "llgfrl", 463 [LONG_INSN_LLGHRL] = "llghrl", 464 [LONG_INSN_LLGTAT] = "llgtat", 465 [LONG_INSN_POPCNT] = "popcnt", 466 [LONG_INSN_RIEMIT] = "riemit", 467 [LONG_INSN_RINEXT] = "rinext", 468 [LONG_INSN_RISBGN] = "risbgn", 469 [LONG_INSN_RISBHG] = "risbhg", 470 [LONG_INSN_RISBLG] = "risblg", 471 [LONG_INSN_SLHHHR] = "slhhhr", 472 [LONG_INSN_SLHHLR] = "slhhlr", 473 [LONG_INSN_TABORT] = "tabort", 474 [LONG_INSN_TBEGIN] = "tbegin", 475 [LONG_INSN_TBEGINC] = "tbeginc", 476 [LONG_INSN_PCISTG] = "pcistg", 477 [LONG_INSN_MPCIFC] = "mpcifc", 478 [LONG_INSN_STPCIFC] = "stpcifc", 479 [LONG_INSN_PCISTB] = "pcistb", 480 }; 481 482 static struct insn opcode[] = { 483 #ifdef CONFIG_64BIT 484 { "bprp", 0xc5, INSTR_MII_UPI }, 485 { "bpp", 0xc7, INSTR_SMI_U0RDP }, 486 { "trtr", 0xd0, INSTR_SS_L0RDRD }, 487 { "lmd", 0xef, INSTR_SS_RRRDRD3 }, 488 #endif 489 { "spm", 0x04, INSTR_RR_R0 }, 490 { "balr", 0x05, INSTR_RR_RR }, 491 { "bctr", 0x06, INSTR_RR_RR }, 492 { "bcr", 0x07, INSTR_RR_UR }, 493 { "svc", 0x0a, INSTR_RR_U0 }, 494 { "bsm", 0x0b, INSTR_RR_RR }, 495 { "bassm", 0x0c, INSTR_RR_RR }, 496 { "basr", 0x0d, INSTR_RR_RR }, 497 { "mvcl", 0x0e, INSTR_RR_RR }, 498 { "clcl", 0x0f, INSTR_RR_RR }, 499 { "lpr", 0x10, INSTR_RR_RR }, 500 { "lnr", 0x11, INSTR_RR_RR }, 501 { "ltr", 0x12, INSTR_RR_RR }, 502 { "lcr", 0x13, INSTR_RR_RR }, 503 { "nr", 0x14, INSTR_RR_RR }, 504 { "clr", 0x15, INSTR_RR_RR }, 505 { "or", 0x16, INSTR_RR_RR }, 506 { "xr", 0x17, INSTR_RR_RR }, 507 { "lr", 0x18, INSTR_RR_RR }, 508 { "cr", 0x19, INSTR_RR_RR }, 509 { "ar", 0x1a, INSTR_RR_RR }, 510 { "sr", 0x1b, INSTR_RR_RR }, 511 { "mr", 0x1c, INSTR_RR_RR }, 512 { "dr", 0x1d, INSTR_RR_RR }, 513 { "alr", 0x1e, INSTR_RR_RR }, 514 { "slr", 0x1f, INSTR_RR_RR }, 515 { "lpdr", 0x20, INSTR_RR_FF }, 516 { "lndr", 0x21, INSTR_RR_FF }, 517 { "ltdr", 0x22, INSTR_RR_FF }, 518 { "lcdr", 0x23, INSTR_RR_FF }, 519 { "hdr", 0x24, INSTR_RR_FF }, 520 { "ldxr", 0x25, INSTR_RR_FF }, 521 { "mxr", 0x26, INSTR_RR_FF }, 522 { "mxdr", 0x27, INSTR_RR_FF }, 523 { "ldr", 0x28, INSTR_RR_FF }, 524 { "cdr", 0x29, INSTR_RR_FF }, 525 { "adr", 0x2a, INSTR_RR_FF }, 526 { "sdr", 0x2b, INSTR_RR_FF }, 527 { "mdr", 0x2c, INSTR_RR_FF }, 528 { "ddr", 0x2d, INSTR_RR_FF }, 529 { "awr", 0x2e, INSTR_RR_FF }, 530 { "swr", 0x2f, INSTR_RR_FF }, 531 { "lper", 0x30, INSTR_RR_FF }, 532 { "lner", 0x31, INSTR_RR_FF }, 533 { "lter", 0x32, INSTR_RR_FF }, 534 { "lcer", 0x33, INSTR_RR_FF }, 535 { "her", 0x34, INSTR_RR_FF }, 536 { "ledr", 0x35, INSTR_RR_FF }, 537 { "axr", 0x36, INSTR_RR_FF }, 538 { "sxr", 0x37, INSTR_RR_FF }, 539 { "ler", 0x38, INSTR_RR_FF }, 540 { "cer", 0x39, INSTR_RR_FF }, 541 { "aer", 0x3a, INSTR_RR_FF }, 542 { "ser", 0x3b, INSTR_RR_FF }, 543 { "mder", 0x3c, INSTR_RR_FF }, 544 { "der", 0x3d, INSTR_RR_FF }, 545 { "aur", 0x3e, INSTR_RR_FF }, 546 { "sur", 0x3f, INSTR_RR_FF }, 547 { "sth", 0x40, INSTR_RX_RRRD }, 548 { "la", 0x41, INSTR_RX_RRRD }, 549 { "stc", 0x42, INSTR_RX_RRRD }, 550 { "ic", 0x43, INSTR_RX_RRRD }, 551 { "ex", 0x44, INSTR_RX_RRRD }, 552 { "bal", 0x45, INSTR_RX_RRRD }, 553 { "bct", 0x46, INSTR_RX_RRRD }, 554 { "bc", 0x47, INSTR_RX_URRD }, 555 { "lh", 0x48, INSTR_RX_RRRD }, 556 { "ch", 0x49, INSTR_RX_RRRD }, 557 { "ah", 0x4a, INSTR_RX_RRRD }, 558 { "sh", 0x4b, INSTR_RX_RRRD }, 559 { "mh", 0x4c, INSTR_RX_RRRD }, 560 { "bas", 0x4d, INSTR_RX_RRRD }, 561 { "cvd", 0x4e, INSTR_RX_RRRD }, 562 { "cvb", 0x4f, INSTR_RX_RRRD }, 563 { "st", 0x50, INSTR_RX_RRRD }, 564 { "lae", 0x51, INSTR_RX_RRRD }, 565 { "n", 0x54, INSTR_RX_RRRD }, 566 { "cl", 0x55, INSTR_RX_RRRD }, 567 { "o", 0x56, INSTR_RX_RRRD }, 568 { "x", 0x57, INSTR_RX_RRRD }, 569 { "l", 0x58, INSTR_RX_RRRD }, 570 { "c", 0x59, INSTR_RX_RRRD }, 571 { "a", 0x5a, INSTR_RX_RRRD }, 572 { "s", 0x5b, INSTR_RX_RRRD }, 573 { "m", 0x5c, INSTR_RX_RRRD }, 574 { "d", 0x5d, INSTR_RX_RRRD }, 575 { "al", 0x5e, INSTR_RX_RRRD }, 576 { "sl", 0x5f, INSTR_RX_RRRD }, 577 { "std", 0x60, INSTR_RX_FRRD }, 578 { "mxd", 0x67, INSTR_RX_FRRD }, 579 { "ld", 0x68, INSTR_RX_FRRD }, 580 { "cd", 0x69, INSTR_RX_FRRD }, 581 { "ad", 0x6a, INSTR_RX_FRRD }, 582 { "sd", 0x6b, INSTR_RX_FRRD }, 583 { "md", 0x6c, INSTR_RX_FRRD }, 584 { "dd", 0x6d, INSTR_RX_FRRD }, 585 { "aw", 0x6e, INSTR_RX_FRRD }, 586 { "sw", 0x6f, INSTR_RX_FRRD }, 587 { "ste", 0x70, INSTR_RX_FRRD }, 588 { "ms", 0x71, INSTR_RX_RRRD }, 589 { "le", 0x78, INSTR_RX_FRRD }, 590 { "ce", 0x79, INSTR_RX_FRRD }, 591 { "ae", 0x7a, INSTR_RX_FRRD }, 592 { "se", 0x7b, INSTR_RX_FRRD }, 593 { "mde", 0x7c, INSTR_RX_FRRD }, 594 { "de", 0x7d, INSTR_RX_FRRD }, 595 { "au", 0x7e, INSTR_RX_FRRD }, 596 { "su", 0x7f, INSTR_RX_FRRD }, 597 { "ssm", 0x80, INSTR_S_RD }, 598 { "lpsw", 0x82, INSTR_S_RD }, 599 { "diag", 0x83, INSTR_RS_RRRD }, 600 { "brxh", 0x84, INSTR_RSI_RRP }, 601 { "brxle", 0x85, INSTR_RSI_RRP }, 602 { "bxh", 0x86, INSTR_RS_RRRD }, 603 { "bxle", 0x87, INSTR_RS_RRRD }, 604 { "srl", 0x88, INSTR_RS_R0RD }, 605 { "sll", 0x89, INSTR_RS_R0RD }, 606 { "sra", 0x8a, INSTR_RS_R0RD }, 607 { "sla", 0x8b, INSTR_RS_R0RD }, 608 { "srdl", 0x8c, INSTR_RS_R0RD }, 609 { "sldl", 0x8d, INSTR_RS_R0RD }, 610 { "srda", 0x8e, INSTR_RS_R0RD }, 611 { "slda", 0x8f, INSTR_RS_R0RD }, 612 { "stm", 0x90, INSTR_RS_RRRD }, 613 { "tm", 0x91, INSTR_SI_URD }, 614 { "mvi", 0x92, INSTR_SI_URD }, 615 { "ts", 0x93, INSTR_S_RD }, 616 { "ni", 0x94, INSTR_SI_URD }, 617 { "cli", 0x95, INSTR_SI_URD }, 618 { "oi", 0x96, INSTR_SI_URD }, 619 { "xi", 0x97, INSTR_SI_URD }, 620 { "lm", 0x98, INSTR_RS_RRRD }, 621 { "trace", 0x99, INSTR_RS_RRRD }, 622 { "lam", 0x9a, INSTR_RS_AARD }, 623 { "stam", 0x9b, INSTR_RS_AARD }, 624 { "mvcle", 0xa8, INSTR_RS_RRRD }, 625 { "clcle", 0xa9, INSTR_RS_RRRD }, 626 { "stnsm", 0xac, INSTR_SI_URD }, 627 { "stosm", 0xad, INSTR_SI_URD }, 628 { "sigp", 0xae, INSTR_RS_RRRD }, 629 { "mc", 0xaf, INSTR_SI_URD }, 630 { "lra", 0xb1, INSTR_RX_RRRD }, 631 { "stctl", 0xb6, INSTR_RS_CCRD }, 632 { "lctl", 0xb7, INSTR_RS_CCRD }, 633 { "cs", 0xba, INSTR_RS_RRRD }, 634 { "cds", 0xbb, INSTR_RS_RRRD }, 635 { "clm", 0xbd, INSTR_RS_RURD }, 636 { "stcm", 0xbe, INSTR_RS_RURD }, 637 { "icm", 0xbf, INSTR_RS_RURD }, 638 { "mvn", 0xd1, INSTR_SS_L0RDRD }, 639 { "mvc", 0xd2, INSTR_SS_L0RDRD }, 640 { "mvz", 0xd3, INSTR_SS_L0RDRD }, 641 { "nc", 0xd4, INSTR_SS_L0RDRD }, 642 { "clc", 0xd5, INSTR_SS_L0RDRD }, 643 { "oc", 0xd6, INSTR_SS_L0RDRD }, 644 { "xc", 0xd7, INSTR_SS_L0RDRD }, 645 { "mvck", 0xd9, INSTR_SS_RRRDRD }, 646 { "mvcp", 0xda, INSTR_SS_RRRDRD }, 647 { "mvcs", 0xdb, INSTR_SS_RRRDRD }, 648 { "tr", 0xdc, INSTR_SS_L0RDRD }, 649 { "trt", 0xdd, INSTR_SS_L0RDRD }, 650 { "ed", 0xde, INSTR_SS_L0RDRD }, 651 { "edmk", 0xdf, INSTR_SS_L0RDRD }, 652 { "pku", 0xe1, INSTR_SS_L0RDRD }, 653 { "unpku", 0xe2, INSTR_SS_L0RDRD }, 654 { "mvcin", 0xe8, INSTR_SS_L0RDRD }, 655 { "pka", 0xe9, INSTR_SS_L0RDRD }, 656 { "unpka", 0xea, INSTR_SS_L0RDRD }, 657 { "plo", 0xee, INSTR_SS_RRRDRD2 }, 658 { "srp", 0xf0, INSTR_SS_LIRDRD }, 659 { "mvo", 0xf1, INSTR_SS_LLRDRD }, 660 { "pack", 0xf2, INSTR_SS_LLRDRD }, 661 { "unpk", 0xf3, INSTR_SS_LLRDRD }, 662 { "zap", 0xf8, INSTR_SS_LLRDRD }, 663 { "cp", 0xf9, INSTR_SS_LLRDRD }, 664 { "ap", 0xfa, INSTR_SS_LLRDRD }, 665 { "sp", 0xfb, INSTR_SS_LLRDRD }, 666 { "mp", 0xfc, INSTR_SS_LLRDRD }, 667 { "dp", 0xfd, INSTR_SS_LLRDRD }, 668 { "", 0, INSTR_INVALID } 669 }; 670 671 static struct insn opcode_01[] = { 672 #ifdef CONFIG_64BIT 673 { "ptff", 0x04, INSTR_E }, 674 { "pfpo", 0x0a, INSTR_E }, 675 { "sam64", 0x0e, INSTR_E }, 676 #endif 677 { "pr", 0x01, INSTR_E }, 678 { "upt", 0x02, INSTR_E }, 679 { "sckpf", 0x07, INSTR_E }, 680 { "tam", 0x0b, INSTR_E }, 681 { "sam24", 0x0c, INSTR_E }, 682 { "sam31", 0x0d, INSTR_E }, 683 { "trap2", 0xff, INSTR_E }, 684 { "", 0, INSTR_INVALID } 685 }; 686 687 static struct insn opcode_a5[] = { 688 #ifdef CONFIG_64BIT 689 { "iihh", 0x00, INSTR_RI_RU }, 690 { "iihl", 0x01, INSTR_RI_RU }, 691 { "iilh", 0x02, INSTR_RI_RU }, 692 { "iill", 0x03, INSTR_RI_RU }, 693 { "nihh", 0x04, INSTR_RI_RU }, 694 { "nihl", 0x05, INSTR_RI_RU }, 695 { "nilh", 0x06, INSTR_RI_RU }, 696 { "nill", 0x07, INSTR_RI_RU }, 697 { "oihh", 0x08, INSTR_RI_RU }, 698 { "oihl", 0x09, INSTR_RI_RU }, 699 { "oilh", 0x0a, INSTR_RI_RU }, 700 { "oill", 0x0b, INSTR_RI_RU }, 701 { "llihh", 0x0c, INSTR_RI_RU }, 702 { "llihl", 0x0d, INSTR_RI_RU }, 703 { "llilh", 0x0e, INSTR_RI_RU }, 704 { "llill", 0x0f, INSTR_RI_RU }, 705 #endif 706 { "", 0, INSTR_INVALID } 707 }; 708 709 static struct insn opcode_a7[] = { 710 #ifdef CONFIG_64BIT 711 { "tmhh", 0x02, INSTR_RI_RU }, 712 { "tmhl", 0x03, INSTR_RI_RU }, 713 { "brctg", 0x07, INSTR_RI_RP }, 714 { "lghi", 0x09, INSTR_RI_RI }, 715 { "aghi", 0x0b, INSTR_RI_RI }, 716 { "mghi", 0x0d, INSTR_RI_RI }, 717 { "cghi", 0x0f, INSTR_RI_RI }, 718 #endif 719 { "tmlh", 0x00, INSTR_RI_RU }, 720 { "tmll", 0x01, INSTR_RI_RU }, 721 { "brc", 0x04, INSTR_RI_UP }, 722 { "bras", 0x05, INSTR_RI_RP }, 723 { "brct", 0x06, INSTR_RI_RP }, 724 { "lhi", 0x08, INSTR_RI_RI }, 725 { "ahi", 0x0a, INSTR_RI_RI }, 726 { "mhi", 0x0c, INSTR_RI_RI }, 727 { "chi", 0x0e, INSTR_RI_RI }, 728 { "", 0, INSTR_INVALID } 729 }; 730 731 static struct insn opcode_aa[] = { 732 #ifdef CONFIG_64BIT 733 { { 0, LONG_INSN_RINEXT }, 0x00, INSTR_RI_RI }, 734 { "rion", 0x01, INSTR_RI_RI }, 735 { "tric", 0x02, INSTR_RI_RI }, 736 { "rioff", 0x03, INSTR_RI_RI }, 737 { { 0, LONG_INSN_RIEMIT }, 0x04, INSTR_RI_RI }, 738 #endif 739 { "", 0, INSTR_INVALID } 740 }; 741 742 static struct insn opcode_b2[] = { 743 #ifdef CONFIG_64BIT 744 { "stckf", 0x7c, INSTR_S_RD }, 745 { "lpp", 0x80, INSTR_S_RD }, 746 { "lcctl", 0x84, INSTR_S_RD }, 747 { "lpctl", 0x85, INSTR_S_RD }, 748 { "qsi", 0x86, INSTR_S_RD }, 749 { "lsctl", 0x87, INSTR_S_RD }, 750 { "qctri", 0x8e, INSTR_S_RD }, 751 { "stfle", 0xb0, INSTR_S_RD }, 752 { "lpswe", 0xb2, INSTR_S_RD }, 753 { "srnmb", 0xb8, INSTR_S_RD }, 754 { "srnmt", 0xb9, INSTR_S_RD }, 755 { "lfas", 0xbd, INSTR_S_RD }, 756 { "scctr", 0xe0, INSTR_RRE_RR }, 757 { "spctr", 0xe1, INSTR_RRE_RR }, 758 { "ecctr", 0xe4, INSTR_RRE_RR }, 759 { "epctr", 0xe5, INSTR_RRE_RR }, 760 { "ppa", 0xe8, INSTR_RRF_U0RR }, 761 { "etnd", 0xec, INSTR_RRE_R0 }, 762 { "ecpga", 0xed, INSTR_RRE_RR }, 763 { "tend", 0xf8, INSTR_S_00 }, 764 { "niai", 0xfa, INSTR_IE_UU }, 765 { { 0, LONG_INSN_TABORT }, 0xfc, INSTR_S_RD }, 766 #endif 767 { "stidp", 0x02, INSTR_S_RD }, 768 { "sck", 0x04, INSTR_S_RD }, 769 { "stck", 0x05, INSTR_S_RD }, 770 { "sckc", 0x06, INSTR_S_RD }, 771 { "stckc", 0x07, INSTR_S_RD }, 772 { "spt", 0x08, INSTR_S_RD }, 773 { "stpt", 0x09, INSTR_S_RD }, 774 { "spka", 0x0a, INSTR_S_RD }, 775 { "ipk", 0x0b, INSTR_S_00 }, 776 { "ptlb", 0x0d, INSTR_S_00 }, 777 { "spx", 0x10, INSTR_S_RD }, 778 { "stpx", 0x11, INSTR_S_RD }, 779 { "stap", 0x12, INSTR_S_RD }, 780 { "sie", 0x14, INSTR_S_RD }, 781 { "pc", 0x18, INSTR_S_RD }, 782 { "sac", 0x19, INSTR_S_RD }, 783 { "cfc", 0x1a, INSTR_S_RD }, 784 { "servc", 0x20, INSTR_RRE_RR }, 785 { "ipte", 0x21, INSTR_RRE_RR }, 786 { "ipm", 0x22, INSTR_RRE_R0 }, 787 { "ivsk", 0x23, INSTR_RRE_RR }, 788 { "iac", 0x24, INSTR_RRE_R0 }, 789 { "ssar", 0x25, INSTR_RRE_R0 }, 790 { "epar", 0x26, INSTR_RRE_R0 }, 791 { "esar", 0x27, INSTR_RRE_R0 }, 792 { "pt", 0x28, INSTR_RRE_RR }, 793 { "iske", 0x29, INSTR_RRE_RR }, 794 { "rrbe", 0x2a, INSTR_RRE_RR }, 795 { "sske", 0x2b, INSTR_RRF_M0RR }, 796 { "tb", 0x2c, INSTR_RRE_0R }, 797 { "dxr", 0x2d, INSTR_RRE_FF }, 798 { "pgin", 0x2e, INSTR_RRE_RR }, 799 { "pgout", 0x2f, INSTR_RRE_RR }, 800 { "csch", 0x30, INSTR_S_00 }, 801 { "hsch", 0x31, INSTR_S_00 }, 802 { "msch", 0x32, INSTR_S_RD }, 803 { "ssch", 0x33, INSTR_S_RD }, 804 { "stsch", 0x34, INSTR_S_RD }, 805 { "tsch", 0x35, INSTR_S_RD }, 806 { "tpi", 0x36, INSTR_S_RD }, 807 { "sal", 0x37, INSTR_S_00 }, 808 { "rsch", 0x38, INSTR_S_00 }, 809 { "stcrw", 0x39, INSTR_S_RD }, 810 { "stcps", 0x3a, INSTR_S_RD }, 811 { "rchp", 0x3b, INSTR_S_00 }, 812 { "schm", 0x3c, INSTR_S_00 }, 813 { "bakr", 0x40, INSTR_RRE_RR }, 814 { "cksm", 0x41, INSTR_RRE_RR }, 815 { "sqdr", 0x44, INSTR_RRE_FF }, 816 { "sqer", 0x45, INSTR_RRE_FF }, 817 { "stura", 0x46, INSTR_RRE_RR }, 818 { "msta", 0x47, INSTR_RRE_R0 }, 819 { "palb", 0x48, INSTR_RRE_00 }, 820 { "ereg", 0x49, INSTR_RRE_RR }, 821 { "esta", 0x4a, INSTR_RRE_RR }, 822 { "lura", 0x4b, INSTR_RRE_RR }, 823 { "tar", 0x4c, INSTR_RRE_AR }, 824 { "cpya", 0x4d, INSTR_RRE_AA }, 825 { "sar", 0x4e, INSTR_RRE_AR }, 826 { "ear", 0x4f, INSTR_RRE_RA }, 827 { "csp", 0x50, INSTR_RRE_RR }, 828 { "msr", 0x52, INSTR_RRE_RR }, 829 { "mvpg", 0x54, INSTR_RRE_RR }, 830 { "mvst", 0x55, INSTR_RRE_RR }, 831 { "cuse", 0x57, INSTR_RRE_RR }, 832 { "bsg", 0x58, INSTR_RRE_RR }, 833 { "bsa", 0x5a, INSTR_RRE_RR }, 834 { "clst", 0x5d, INSTR_RRE_RR }, 835 { "srst", 0x5e, INSTR_RRE_RR }, 836 { "cmpsc", 0x63, INSTR_RRE_RR }, 837 { "siga", 0x74, INSTR_S_RD }, 838 { "xsch", 0x76, INSTR_S_00 }, 839 { "rp", 0x77, INSTR_S_RD }, 840 { "stcke", 0x78, INSTR_S_RD }, 841 { "sacf", 0x79, INSTR_S_RD }, 842 { "stsi", 0x7d, INSTR_S_RD }, 843 { "spp", 0x80, INSTR_S_RD }, 844 { "srnm", 0x99, INSTR_S_RD }, 845 { "stfpc", 0x9c, INSTR_S_RD }, 846 { "lfpc", 0x9d, INSTR_S_RD }, 847 { "tre", 0xa5, INSTR_RRE_RR }, 848 { "cuutf", 0xa6, INSTR_RRF_M0RR }, 849 { "cutfu", 0xa7, INSTR_RRF_M0RR }, 850 { "stfl", 0xb1, INSTR_S_RD }, 851 { "trap4", 0xff, INSTR_S_RD }, 852 { "", 0, INSTR_INVALID } 853 }; 854 855 static struct insn opcode_b3[] = { 856 #ifdef CONFIG_64BIT 857 { "maylr", 0x38, INSTR_RRF_F0FF }, 858 { "mylr", 0x39, INSTR_RRF_F0FF }, 859 { "mayr", 0x3a, INSTR_RRF_F0FF }, 860 { "myr", 0x3b, INSTR_RRF_F0FF }, 861 { "mayhr", 0x3c, INSTR_RRF_F0FF }, 862 { "myhr", 0x3d, INSTR_RRF_F0FF }, 863 { "lpdfr", 0x70, INSTR_RRE_FF }, 864 { "lndfr", 0x71, INSTR_RRE_FF }, 865 { "cpsdr", 0x72, INSTR_RRF_F0FF2 }, 866 { "lcdfr", 0x73, INSTR_RRE_FF }, 867 { "sfasr", 0x85, INSTR_RRE_R0 }, 868 { { 0, LONG_INSN_CELFBR }, 0x90, INSTR_RRF_UUFR }, 869 { { 0, LONG_INSN_CDLFBR }, 0x91, INSTR_RRF_UUFR }, 870 { { 0, LONG_INSN_CXLFBR }, 0x92, INSTR_RRF_UURF }, 871 { { 0, LONG_INSN_CEFBRA }, 0x94, INSTR_RRF_UUFR }, 872 { { 0, LONG_INSN_CDFBRA }, 0x95, INSTR_RRF_UUFR }, 873 { { 0, LONG_INSN_CXFBRA }, 0x96, INSTR_RRF_UURF }, 874 { { 0, LONG_INSN_CFEBRA }, 0x98, INSTR_RRF_UURF }, 875 { { 0, LONG_INSN_CFDBRA }, 0x99, INSTR_RRF_UURF }, 876 { { 0, LONG_INSN_CFXBRA }, 0x9a, INSTR_RRF_UUFR }, 877 { { 0, LONG_INSN_CLFEBR }, 0x9c, INSTR_RRF_UURF }, 878 { { 0, LONG_INSN_CLFDBR }, 0x9d, INSTR_RRF_UURF }, 879 { { 0, LONG_INSN_CLFXBR }, 0x9e, INSTR_RRF_UUFR }, 880 { { 0, LONG_INSN_CELGBR }, 0xa0, INSTR_RRF_UUFR }, 881 { { 0, LONG_INSN_CDLGBR }, 0xa1, INSTR_RRF_UUFR }, 882 { { 0, LONG_INSN_CXLGBR }, 0xa2, INSTR_RRF_UURF }, 883 { { 0, LONG_INSN_CEGBRA }, 0xa4, INSTR_RRF_UUFR }, 884 { { 0, LONG_INSN_CDGBRA }, 0xa5, INSTR_RRF_UUFR }, 885 { { 0, LONG_INSN_CXGBRA }, 0xa6, INSTR_RRF_UURF }, 886 { { 0, LONG_INSN_CGEBRA }, 0xa8, INSTR_RRF_UURF }, 887 { { 0, LONG_INSN_CGDBRA }, 0xa9, INSTR_RRF_UURF }, 888 { { 0, LONG_INSN_CGXBRA }, 0xaa, INSTR_RRF_UUFR }, 889 { { 0, LONG_INSN_CLGEBR }, 0xac, INSTR_RRF_UURF }, 890 { { 0, LONG_INSN_CLGDBR }, 0xad, INSTR_RRF_UURF }, 891 { { 0, LONG_INSN_CLGXBR }, 0xae, INSTR_RRF_UUFR }, 892 { "ldgr", 0xc1, INSTR_RRE_FR }, 893 { "cegr", 0xc4, INSTR_RRE_FR }, 894 { "cdgr", 0xc5, INSTR_RRE_FR }, 895 { "cxgr", 0xc6, INSTR_RRE_FR }, 896 { "cger", 0xc8, INSTR_RRF_U0RF }, 897 { "cgdr", 0xc9, INSTR_RRF_U0RF }, 898 { "cgxr", 0xca, INSTR_RRF_U0RF }, 899 { "lgdr", 0xcd, INSTR_RRE_RF }, 900 { "mdtra", 0xd0, INSTR_RRF_FUFF2 }, 901 { "ddtra", 0xd1, INSTR_RRF_FUFF2 }, 902 { "adtra", 0xd2, INSTR_RRF_FUFF2 }, 903 { "sdtra", 0xd3, INSTR_RRF_FUFF2 }, 904 { "ldetr", 0xd4, INSTR_RRF_0UFF }, 905 { "ledtr", 0xd5, INSTR_RRF_UUFF }, 906 { "ltdtr", 0xd6, INSTR_RRE_FF }, 907 { "fidtr", 0xd7, INSTR_RRF_UUFF }, 908 { "mxtra", 0xd8, INSTR_RRF_FUFF2 }, 909 { "dxtra", 0xd9, INSTR_RRF_FUFF2 }, 910 { "axtra", 0xda, INSTR_RRF_FUFF2 }, 911 { "sxtra", 0xdb, INSTR_RRF_FUFF2 }, 912 { "lxdtr", 0xdc, INSTR_RRF_0UFF }, 913 { "ldxtr", 0xdd, INSTR_RRF_UUFF }, 914 { "ltxtr", 0xde, INSTR_RRE_FF }, 915 { "fixtr", 0xdf, INSTR_RRF_UUFF }, 916 { "kdtr", 0xe0, INSTR_RRE_FF }, 917 { { 0, LONG_INSN_CGDTRA }, 0xe1, INSTR_RRF_UURF }, 918 { "cudtr", 0xe2, INSTR_RRE_RF }, 919 { "csdtr", 0xe3, INSTR_RRE_RF }, 920 { "cdtr", 0xe4, INSTR_RRE_FF }, 921 { "eedtr", 0xe5, INSTR_RRE_RF }, 922 { "esdtr", 0xe7, INSTR_RRE_RF }, 923 { "kxtr", 0xe8, INSTR_RRE_FF }, 924 { { 0, LONG_INSN_CGXTRA }, 0xe9, INSTR_RRF_UUFR }, 925 { "cuxtr", 0xea, INSTR_RRE_RF }, 926 { "csxtr", 0xeb, INSTR_RRE_RF }, 927 { "cxtr", 0xec, INSTR_RRE_FF }, 928 { "eextr", 0xed, INSTR_RRE_RF }, 929 { "esxtr", 0xef, INSTR_RRE_RF }, 930 { { 0, LONG_INSN_CDGTRA }, 0xf1, INSTR_RRF_UUFR }, 931 { "cdutr", 0xf2, INSTR_RRE_FR }, 932 { "cdstr", 0xf3, INSTR_RRE_FR }, 933 { "cedtr", 0xf4, INSTR_RRE_FF }, 934 { "qadtr", 0xf5, INSTR_RRF_FUFF }, 935 { "iedtr", 0xf6, INSTR_RRF_F0FR }, 936 { "rrdtr", 0xf7, INSTR_RRF_FFRU }, 937 { { 0, LONG_INSN_CXGTRA }, 0xf9, INSTR_RRF_UURF }, 938 { "cxutr", 0xfa, INSTR_RRE_FR }, 939 { "cxstr", 0xfb, INSTR_RRE_FR }, 940 { "cextr", 0xfc, INSTR_RRE_FF }, 941 { "qaxtr", 0xfd, INSTR_RRF_FUFF }, 942 { "iextr", 0xfe, INSTR_RRF_F0FR }, 943 { "rrxtr", 0xff, INSTR_RRF_FFRU }, 944 #endif 945 { "lpebr", 0x00, INSTR_RRE_FF }, 946 { "lnebr", 0x01, INSTR_RRE_FF }, 947 { "ltebr", 0x02, INSTR_RRE_FF }, 948 { "lcebr", 0x03, INSTR_RRE_FF }, 949 { "ldebr", 0x04, INSTR_RRE_FF }, 950 { "lxdbr", 0x05, INSTR_RRE_FF }, 951 { "lxebr", 0x06, INSTR_RRE_FF }, 952 { "mxdbr", 0x07, INSTR_RRE_FF }, 953 { "kebr", 0x08, INSTR_RRE_FF }, 954 { "cebr", 0x09, INSTR_RRE_FF }, 955 { "aebr", 0x0a, INSTR_RRE_FF }, 956 { "sebr", 0x0b, INSTR_RRE_FF }, 957 { "mdebr", 0x0c, INSTR_RRE_FF }, 958 { "debr", 0x0d, INSTR_RRE_FF }, 959 { "maebr", 0x0e, INSTR_RRF_F0FF }, 960 { "msebr", 0x0f, INSTR_RRF_F0FF }, 961 { "lpdbr", 0x10, INSTR_RRE_FF }, 962 { "lndbr", 0x11, INSTR_RRE_FF }, 963 { "ltdbr", 0x12, INSTR_RRE_FF }, 964 { "lcdbr", 0x13, INSTR_RRE_FF }, 965 { "sqebr", 0x14, INSTR_RRE_FF }, 966 { "sqdbr", 0x15, INSTR_RRE_FF }, 967 { "sqxbr", 0x16, INSTR_RRE_FF }, 968 { "meebr", 0x17, INSTR_RRE_FF }, 969 { "kdbr", 0x18, INSTR_RRE_FF }, 970 { "cdbr", 0x19, INSTR_RRE_FF }, 971 { "adbr", 0x1a, INSTR_RRE_FF }, 972 { "sdbr", 0x1b, INSTR_RRE_FF }, 973 { "mdbr", 0x1c, INSTR_RRE_FF }, 974 { "ddbr", 0x1d, INSTR_RRE_FF }, 975 { "madbr", 0x1e, INSTR_RRF_F0FF }, 976 { "msdbr", 0x1f, INSTR_RRF_F0FF }, 977 { "lder", 0x24, INSTR_RRE_FF }, 978 { "lxdr", 0x25, INSTR_RRE_FF }, 979 { "lxer", 0x26, INSTR_RRE_FF }, 980 { "maer", 0x2e, INSTR_RRF_F0FF }, 981 { "mser", 0x2f, INSTR_RRF_F0FF }, 982 { "sqxr", 0x36, INSTR_RRE_FF }, 983 { "meer", 0x37, INSTR_RRE_FF }, 984 { "madr", 0x3e, INSTR_RRF_F0FF }, 985 { "msdr", 0x3f, INSTR_RRF_F0FF }, 986 { "lpxbr", 0x40, INSTR_RRE_FF }, 987 { "lnxbr", 0x41, INSTR_RRE_FF }, 988 { "ltxbr", 0x42, INSTR_RRE_FF }, 989 { "lcxbr", 0x43, INSTR_RRE_FF }, 990 { { 0, LONG_INSN_LEDBRA }, 0x44, INSTR_RRF_UUFF }, 991 { { 0, LONG_INSN_LDXBRA }, 0x45, INSTR_RRF_UUFF }, 992 { { 0, LONG_INSN_LEXBRA }, 0x46, INSTR_RRF_UUFF }, 993 { { 0, LONG_INSN_FIXBRA }, 0x47, INSTR_RRF_UUFF }, 994 { "kxbr", 0x48, INSTR_RRE_FF }, 995 { "cxbr", 0x49, INSTR_RRE_FF }, 996 { "axbr", 0x4a, INSTR_RRE_FF }, 997 { "sxbr", 0x4b, INSTR_RRE_FF }, 998 { "mxbr", 0x4c, INSTR_RRE_FF }, 999 { "dxbr", 0x4d, INSTR_RRE_FF }, 1000 { "tbedr", 0x50, INSTR_RRF_U0FF }, 1001 { "tbdr", 0x51, INSTR_RRF_U0FF }, 1002 { "diebr", 0x53, INSTR_RRF_FUFF }, 1003 { { 0, LONG_INSN_FIEBRA }, 0x57, INSTR_RRF_UUFF }, 1004 { "thder", 0x58, INSTR_RRE_FF }, 1005 { "thdr", 0x59, INSTR_RRE_FF }, 1006 { "didbr", 0x5b, INSTR_RRF_FUFF }, 1007 { { 0, LONG_INSN_FIDBRA }, 0x5f, INSTR_RRF_UUFF }, 1008 { "lpxr", 0x60, INSTR_RRE_FF }, 1009 { "lnxr", 0x61, INSTR_RRE_FF }, 1010 { "ltxr", 0x62, INSTR_RRE_FF }, 1011 { "lcxr", 0x63, INSTR_RRE_FF }, 1012 { "lxr", 0x65, INSTR_RRE_FF }, 1013 { "lexr", 0x66, INSTR_RRE_FF }, 1014 { "fixr", 0x67, INSTR_RRE_FF }, 1015 { "cxr", 0x69, INSTR_RRE_FF }, 1016 { "lzer", 0x74, INSTR_RRE_F0 }, 1017 { "lzdr", 0x75, INSTR_RRE_F0 }, 1018 { "lzxr", 0x76, INSTR_RRE_F0 }, 1019 { "fier", 0x77, INSTR_RRE_FF }, 1020 { "fidr", 0x7f, INSTR_RRE_FF }, 1021 { "sfpc", 0x84, INSTR_RRE_RR_OPT }, 1022 { "efpc", 0x8c, INSTR_RRE_RR_OPT }, 1023 { "cefbr", 0x94, INSTR_RRE_RF }, 1024 { "cdfbr", 0x95, INSTR_RRE_RF }, 1025 { "cxfbr", 0x96, INSTR_RRE_RF }, 1026 { "cfebr", 0x98, INSTR_RRF_U0RF }, 1027 { "cfdbr", 0x99, INSTR_RRF_U0RF }, 1028 { "cfxbr", 0x9a, INSTR_RRF_U0RF }, 1029 { "cefr", 0xb4, INSTR_RRE_FR }, 1030 { "cdfr", 0xb5, INSTR_RRE_FR }, 1031 { "cxfr", 0xb6, INSTR_RRE_FR }, 1032 { "cfer", 0xb8, INSTR_RRF_U0RF }, 1033 { "cfdr", 0xb9, INSTR_RRF_U0RF }, 1034 { "cfxr", 0xba, INSTR_RRF_U0RF }, 1035 { "", 0, INSTR_INVALID } 1036 }; 1037 1038 static struct insn opcode_b9[] = { 1039 #ifdef CONFIG_64BIT 1040 { "lpgr", 0x00, INSTR_RRE_RR }, 1041 { "lngr", 0x01, INSTR_RRE_RR }, 1042 { "ltgr", 0x02, INSTR_RRE_RR }, 1043 { "lcgr", 0x03, INSTR_RRE_RR }, 1044 { "lgr", 0x04, INSTR_RRE_RR }, 1045 { "lurag", 0x05, INSTR_RRE_RR }, 1046 { "lgbr", 0x06, INSTR_RRE_RR }, 1047 { "lghr", 0x07, INSTR_RRE_RR }, 1048 { "agr", 0x08, INSTR_RRE_RR }, 1049 { "sgr", 0x09, INSTR_RRE_RR }, 1050 { "algr", 0x0a, INSTR_RRE_RR }, 1051 { "slgr", 0x0b, INSTR_RRE_RR }, 1052 { "msgr", 0x0c, INSTR_RRE_RR }, 1053 { "dsgr", 0x0d, INSTR_RRE_RR }, 1054 { "eregg", 0x0e, INSTR_RRE_RR }, 1055 { "lrvgr", 0x0f, INSTR_RRE_RR }, 1056 { "lpgfr", 0x10, INSTR_RRE_RR }, 1057 { "lngfr", 0x11, INSTR_RRE_RR }, 1058 { "ltgfr", 0x12, INSTR_RRE_RR }, 1059 { "lcgfr", 0x13, INSTR_RRE_RR }, 1060 { "lgfr", 0x14, INSTR_RRE_RR }, 1061 { "llgfr", 0x16, INSTR_RRE_RR }, 1062 { "llgtr", 0x17, INSTR_RRE_RR }, 1063 { "agfr", 0x18, INSTR_RRE_RR }, 1064 { "sgfr", 0x19, INSTR_RRE_RR }, 1065 { "algfr", 0x1a, INSTR_RRE_RR }, 1066 { "slgfr", 0x1b, INSTR_RRE_RR }, 1067 { "msgfr", 0x1c, INSTR_RRE_RR }, 1068 { "dsgfr", 0x1d, INSTR_RRE_RR }, 1069 { "cgr", 0x20, INSTR_RRE_RR }, 1070 { "clgr", 0x21, INSTR_RRE_RR }, 1071 { "sturg", 0x25, INSTR_RRE_RR }, 1072 { "lbr", 0x26, INSTR_RRE_RR }, 1073 { "lhr", 0x27, INSTR_RRE_RR }, 1074 { "cgfr", 0x30, INSTR_RRE_RR }, 1075 { "clgfr", 0x31, INSTR_RRE_RR }, 1076 { "cfdtr", 0x41, INSTR_RRF_UURF }, 1077 { { 0, LONG_INSN_CLGDTR }, 0x42, INSTR_RRF_UURF }, 1078 { { 0, LONG_INSN_CLFDTR }, 0x43, INSTR_RRF_UURF }, 1079 { "bctgr", 0x46, INSTR_RRE_RR }, 1080 { "cfxtr", 0x49, INSTR_RRF_UURF }, 1081 { { 0, LONG_INSN_CLGXTR }, 0x4a, INSTR_RRF_UUFR }, 1082 { { 0, LONG_INSN_CLFXTR }, 0x4b, INSTR_RRF_UUFR }, 1083 { "cdftr", 0x51, INSTR_RRF_UUFR }, 1084 { { 0, LONG_INSN_CDLGTR }, 0x52, INSTR_RRF_UUFR }, 1085 { { 0, LONG_INSN_CDLFTR }, 0x53, INSTR_RRF_UUFR }, 1086 { "cxftr", 0x59, INSTR_RRF_UURF }, 1087 { { 0, LONG_INSN_CXLGTR }, 0x5a, INSTR_RRF_UURF }, 1088 { { 0, LONG_INSN_CXLFTR }, 0x5b, INSTR_RRF_UUFR }, 1089 { "cgrt", 0x60, INSTR_RRF_U0RR }, 1090 { "clgrt", 0x61, INSTR_RRF_U0RR }, 1091 { "crt", 0x72, INSTR_RRF_U0RR }, 1092 { "clrt", 0x73, INSTR_RRF_U0RR }, 1093 { "ngr", 0x80, INSTR_RRE_RR }, 1094 { "ogr", 0x81, INSTR_RRE_RR }, 1095 { "xgr", 0x82, INSTR_RRE_RR }, 1096 { "flogr", 0x83, INSTR_RRE_RR }, 1097 { "llgcr", 0x84, INSTR_RRE_RR }, 1098 { "llghr", 0x85, INSTR_RRE_RR }, 1099 { "mlgr", 0x86, INSTR_RRE_RR }, 1100 { "dlgr", 0x87, INSTR_RRE_RR }, 1101 { "alcgr", 0x88, INSTR_RRE_RR }, 1102 { "slbgr", 0x89, INSTR_RRE_RR }, 1103 { "cspg", 0x8a, INSTR_RRE_RR }, 1104 { "idte", 0x8e, INSTR_RRF_R0RR }, 1105 { "crdte", 0x8f, INSTR_RRF_RMRR }, 1106 { "llcr", 0x94, INSTR_RRE_RR }, 1107 { "llhr", 0x95, INSTR_RRE_RR }, 1108 { "esea", 0x9d, INSTR_RRE_R0 }, 1109 { "ptf", 0xa2, INSTR_RRE_R0 }, 1110 { "lptea", 0xaa, INSTR_RRF_RURR }, 1111 { "rrbm", 0xae, INSTR_RRE_RR }, 1112 { "pfmf", 0xaf, INSTR_RRE_RR }, 1113 { "cu14", 0xb0, INSTR_RRF_M0RR }, 1114 { "cu24", 0xb1, INSTR_RRF_M0RR }, 1115 { "cu41", 0xb2, INSTR_RRE_RR }, 1116 { "cu42", 0xb3, INSTR_RRE_RR }, 1117 { "trtre", 0xbd, INSTR_RRF_M0RR }, 1118 { "srstu", 0xbe, INSTR_RRE_RR }, 1119 { "trte", 0xbf, INSTR_RRF_M0RR }, 1120 { "ahhhr", 0xc8, INSTR_RRF_R0RR2 }, 1121 { "shhhr", 0xc9, INSTR_RRF_R0RR2 }, 1122 { { 0, LONG_INSN_ALHHHR }, 0xca, INSTR_RRF_R0RR2 }, 1123 { { 0, LONG_INSN_SLHHHR }, 0xcb, INSTR_RRF_R0RR2 }, 1124 { "chhr", 0xcd, INSTR_RRE_RR }, 1125 { "clhhr", 0xcf, INSTR_RRE_RR }, 1126 { { 0, LONG_INSN_PCISTG }, 0xd0, INSTR_RRE_RR }, 1127 { "pcilg", 0xd2, INSTR_RRE_RR }, 1128 { "rpcit", 0xd3, INSTR_RRE_RR }, 1129 { "ahhlr", 0xd8, INSTR_RRF_R0RR2 }, 1130 { "shhlr", 0xd9, INSTR_RRF_R0RR2 }, 1131 { { 0, LONG_INSN_ALHHLR }, 0xda, INSTR_RRF_R0RR2 }, 1132 { { 0, LONG_INSN_SLHHLR }, 0xdb, INSTR_RRF_R0RR2 }, 1133 { "chlr", 0xdd, INSTR_RRE_RR }, 1134 { "clhlr", 0xdf, INSTR_RRE_RR }, 1135 { { 0, LONG_INSN_POPCNT }, 0xe1, INSTR_RRE_RR }, 1136 { "locgr", 0xe2, INSTR_RRF_M0RR }, 1137 { "ngrk", 0xe4, INSTR_RRF_R0RR2 }, 1138 { "ogrk", 0xe6, INSTR_RRF_R0RR2 }, 1139 { "xgrk", 0xe7, INSTR_RRF_R0RR2 }, 1140 { "agrk", 0xe8, INSTR_RRF_R0RR2 }, 1141 { "sgrk", 0xe9, INSTR_RRF_R0RR2 }, 1142 { "algrk", 0xea, INSTR_RRF_R0RR2 }, 1143 { "slgrk", 0xeb, INSTR_RRF_R0RR2 }, 1144 { "locr", 0xf2, INSTR_RRF_M0RR }, 1145 { "nrk", 0xf4, INSTR_RRF_R0RR2 }, 1146 { "ork", 0xf6, INSTR_RRF_R0RR2 }, 1147 { "xrk", 0xf7, INSTR_RRF_R0RR2 }, 1148 { "ark", 0xf8, INSTR_RRF_R0RR2 }, 1149 { "srk", 0xf9, INSTR_RRF_R0RR2 }, 1150 { "alrk", 0xfa, INSTR_RRF_R0RR2 }, 1151 { "slrk", 0xfb, INSTR_RRF_R0RR2 }, 1152 #endif 1153 { "kmac", 0x1e, INSTR_RRE_RR }, 1154 { "lrvr", 0x1f, INSTR_RRE_RR }, 1155 { "km", 0x2e, INSTR_RRE_RR }, 1156 { "kmc", 0x2f, INSTR_RRE_RR }, 1157 { "kimd", 0x3e, INSTR_RRE_RR }, 1158 { "klmd", 0x3f, INSTR_RRE_RR }, 1159 { "epsw", 0x8d, INSTR_RRE_RR }, 1160 { "trtt", 0x90, INSTR_RRF_M0RR }, 1161 { "trto", 0x91, INSTR_RRF_M0RR }, 1162 { "trot", 0x92, INSTR_RRF_M0RR }, 1163 { "troo", 0x93, INSTR_RRF_M0RR }, 1164 { "mlr", 0x96, INSTR_RRE_RR }, 1165 { "dlr", 0x97, INSTR_RRE_RR }, 1166 { "alcr", 0x98, INSTR_RRE_RR }, 1167 { "slbr", 0x99, INSTR_RRE_RR }, 1168 { "", 0, INSTR_INVALID } 1169 }; 1170 1171 static struct insn opcode_c0[] = { 1172 #ifdef CONFIG_64BIT 1173 { "lgfi", 0x01, INSTR_RIL_RI }, 1174 { "xihf", 0x06, INSTR_RIL_RU }, 1175 { "xilf", 0x07, INSTR_RIL_RU }, 1176 { "iihf", 0x08, INSTR_RIL_RU }, 1177 { "iilf", 0x09, INSTR_RIL_RU }, 1178 { "nihf", 0x0a, INSTR_RIL_RU }, 1179 { "nilf", 0x0b, INSTR_RIL_RU }, 1180 { "oihf", 0x0c, INSTR_RIL_RU }, 1181 { "oilf", 0x0d, INSTR_RIL_RU }, 1182 { "llihf", 0x0e, INSTR_RIL_RU }, 1183 { "llilf", 0x0f, INSTR_RIL_RU }, 1184 #endif 1185 { "larl", 0x00, INSTR_RIL_RP }, 1186 { "brcl", 0x04, INSTR_RIL_UP }, 1187 { "brasl", 0x05, INSTR_RIL_RP }, 1188 { "", 0, INSTR_INVALID } 1189 }; 1190 1191 static struct insn opcode_c2[] = { 1192 #ifdef CONFIG_64BIT 1193 { "msgfi", 0x00, INSTR_RIL_RI }, 1194 { "msfi", 0x01, INSTR_RIL_RI }, 1195 { "slgfi", 0x04, INSTR_RIL_RU }, 1196 { "slfi", 0x05, INSTR_RIL_RU }, 1197 { "agfi", 0x08, INSTR_RIL_RI }, 1198 { "afi", 0x09, INSTR_RIL_RI }, 1199 { "algfi", 0x0a, INSTR_RIL_RU }, 1200 { "alfi", 0x0b, INSTR_RIL_RU }, 1201 { "cgfi", 0x0c, INSTR_RIL_RI }, 1202 { "cfi", 0x0d, INSTR_RIL_RI }, 1203 { "clgfi", 0x0e, INSTR_RIL_RU }, 1204 { "clfi", 0x0f, INSTR_RIL_RU }, 1205 #endif 1206 { "", 0, INSTR_INVALID } 1207 }; 1208 1209 static struct insn opcode_c4[] = { 1210 #ifdef CONFIG_64BIT 1211 { "llhrl", 0x02, INSTR_RIL_RP }, 1212 { "lghrl", 0x04, INSTR_RIL_RP }, 1213 { "lhrl", 0x05, INSTR_RIL_RP }, 1214 { { 0, LONG_INSN_LLGHRL }, 0x06, INSTR_RIL_RP }, 1215 { "sthrl", 0x07, INSTR_RIL_RP }, 1216 { "lgrl", 0x08, INSTR_RIL_RP }, 1217 { "stgrl", 0x0b, INSTR_RIL_RP }, 1218 { "lgfrl", 0x0c, INSTR_RIL_RP }, 1219 { "lrl", 0x0d, INSTR_RIL_RP }, 1220 { { 0, LONG_INSN_LLGFRL }, 0x0e, INSTR_RIL_RP }, 1221 { "strl", 0x0f, INSTR_RIL_RP }, 1222 #endif 1223 { "", 0, INSTR_INVALID } 1224 }; 1225 1226 static struct insn opcode_c6[] = { 1227 #ifdef CONFIG_64BIT 1228 { "exrl", 0x00, INSTR_RIL_RP }, 1229 { "pfdrl", 0x02, INSTR_RIL_UP }, 1230 { "cghrl", 0x04, INSTR_RIL_RP }, 1231 { "chrl", 0x05, INSTR_RIL_RP }, 1232 { { 0, LONG_INSN_CLGHRL }, 0x06, INSTR_RIL_RP }, 1233 { "clhrl", 0x07, INSTR_RIL_RP }, 1234 { "cgrl", 0x08, INSTR_RIL_RP }, 1235 { "clgrl", 0x0a, INSTR_RIL_RP }, 1236 { "cgfrl", 0x0c, INSTR_RIL_RP }, 1237 { "crl", 0x0d, INSTR_RIL_RP }, 1238 { { 0, LONG_INSN_CLGFRL }, 0x0e, INSTR_RIL_RP }, 1239 { "clrl", 0x0f, INSTR_RIL_RP }, 1240 #endif 1241 { "", 0, INSTR_INVALID } 1242 }; 1243 1244 static struct insn opcode_c8[] = { 1245 #ifdef CONFIG_64BIT 1246 { "mvcos", 0x00, INSTR_SSF_RRDRD }, 1247 { "ectg", 0x01, INSTR_SSF_RRDRD }, 1248 { "csst", 0x02, INSTR_SSF_RRDRD }, 1249 { "lpd", 0x04, INSTR_SSF_RRDRD2 }, 1250 { "lpdg", 0x05, INSTR_SSF_RRDRD2 }, 1251 #endif 1252 { "", 0, INSTR_INVALID } 1253 }; 1254 1255 static struct insn opcode_cc[] = { 1256 #ifdef CONFIG_64BIT 1257 { "brcth", 0x06, INSTR_RIL_RP }, 1258 { "aih", 0x08, INSTR_RIL_RI }, 1259 { "alsih", 0x0a, INSTR_RIL_RI }, 1260 { { 0, LONG_INSN_ALSIHN }, 0x0b, INSTR_RIL_RI }, 1261 { "cih", 0x0d, INSTR_RIL_RI }, 1262 { "clih", 0x0f, INSTR_RIL_RI }, 1263 #endif 1264 { "", 0, INSTR_INVALID } 1265 }; 1266 1267 static struct insn opcode_e3[] = { 1268 #ifdef CONFIG_64BIT 1269 { "ltg", 0x02, INSTR_RXY_RRRD }, 1270 { "lrag", 0x03, INSTR_RXY_RRRD }, 1271 { "lg", 0x04, INSTR_RXY_RRRD }, 1272 { "cvby", 0x06, INSTR_RXY_RRRD }, 1273 { "ag", 0x08, INSTR_RXY_RRRD }, 1274 { "sg", 0x09, INSTR_RXY_RRRD }, 1275 { "alg", 0x0a, INSTR_RXY_RRRD }, 1276 { "slg", 0x0b, INSTR_RXY_RRRD }, 1277 { "msg", 0x0c, INSTR_RXY_RRRD }, 1278 { "dsg", 0x0d, INSTR_RXY_RRRD }, 1279 { "cvbg", 0x0e, INSTR_RXY_RRRD }, 1280 { "lrvg", 0x0f, INSTR_RXY_RRRD }, 1281 { "lt", 0x12, INSTR_RXY_RRRD }, 1282 { "lray", 0x13, INSTR_RXY_RRRD }, 1283 { "lgf", 0x14, INSTR_RXY_RRRD }, 1284 { "lgh", 0x15, INSTR_RXY_RRRD }, 1285 { "llgf", 0x16, INSTR_RXY_RRRD }, 1286 { "llgt", 0x17, INSTR_RXY_RRRD }, 1287 { "agf", 0x18, INSTR_RXY_RRRD }, 1288 { "sgf", 0x19, INSTR_RXY_RRRD }, 1289 { "algf", 0x1a, INSTR_RXY_RRRD }, 1290 { "slgf", 0x1b, INSTR_RXY_RRRD }, 1291 { "msgf", 0x1c, INSTR_RXY_RRRD }, 1292 { "dsgf", 0x1d, INSTR_RXY_RRRD }, 1293 { "cg", 0x20, INSTR_RXY_RRRD }, 1294 { "clg", 0x21, INSTR_RXY_RRRD }, 1295 { "stg", 0x24, INSTR_RXY_RRRD }, 1296 { "ntstg", 0x25, INSTR_RXY_RRRD }, 1297 { "cvdy", 0x26, INSTR_RXY_RRRD }, 1298 { "cvdg", 0x2e, INSTR_RXY_RRRD }, 1299 { "strvg", 0x2f, INSTR_RXY_RRRD }, 1300 { "cgf", 0x30, INSTR_RXY_RRRD }, 1301 { "clgf", 0x31, INSTR_RXY_RRRD }, 1302 { "ltgf", 0x32, INSTR_RXY_RRRD }, 1303 { "cgh", 0x34, INSTR_RXY_RRRD }, 1304 { "pfd", 0x36, INSTR_RXY_URRD }, 1305 { "strvh", 0x3f, INSTR_RXY_RRRD }, 1306 { "bctg", 0x46, INSTR_RXY_RRRD }, 1307 { "sty", 0x50, INSTR_RXY_RRRD }, 1308 { "msy", 0x51, INSTR_RXY_RRRD }, 1309 { "ny", 0x54, INSTR_RXY_RRRD }, 1310 { "cly", 0x55, INSTR_RXY_RRRD }, 1311 { "oy", 0x56, INSTR_RXY_RRRD }, 1312 { "xy", 0x57, INSTR_RXY_RRRD }, 1313 { "ly", 0x58, INSTR_RXY_RRRD }, 1314 { "cy", 0x59, INSTR_RXY_RRRD }, 1315 { "ay", 0x5a, INSTR_RXY_RRRD }, 1316 { "sy", 0x5b, INSTR_RXY_RRRD }, 1317 { "mfy", 0x5c, INSTR_RXY_RRRD }, 1318 { "aly", 0x5e, INSTR_RXY_RRRD }, 1319 { "sly", 0x5f, INSTR_RXY_RRRD }, 1320 { "sthy", 0x70, INSTR_RXY_RRRD }, 1321 { "lay", 0x71, INSTR_RXY_RRRD }, 1322 { "stcy", 0x72, INSTR_RXY_RRRD }, 1323 { "icy", 0x73, INSTR_RXY_RRRD }, 1324 { "laey", 0x75, INSTR_RXY_RRRD }, 1325 { "lb", 0x76, INSTR_RXY_RRRD }, 1326 { "lgb", 0x77, INSTR_RXY_RRRD }, 1327 { "lhy", 0x78, INSTR_RXY_RRRD }, 1328 { "chy", 0x79, INSTR_RXY_RRRD }, 1329 { "ahy", 0x7a, INSTR_RXY_RRRD }, 1330 { "shy", 0x7b, INSTR_RXY_RRRD }, 1331 { "mhy", 0x7c, INSTR_RXY_RRRD }, 1332 { "ng", 0x80, INSTR_RXY_RRRD }, 1333 { "og", 0x81, INSTR_RXY_RRRD }, 1334 { "xg", 0x82, INSTR_RXY_RRRD }, 1335 { "lgat", 0x85, INSTR_RXY_RRRD }, 1336 { "mlg", 0x86, INSTR_RXY_RRRD }, 1337 { "dlg", 0x87, INSTR_RXY_RRRD }, 1338 { "alcg", 0x88, INSTR_RXY_RRRD }, 1339 { "slbg", 0x89, INSTR_RXY_RRRD }, 1340 { "stpq", 0x8e, INSTR_RXY_RRRD }, 1341 { "lpq", 0x8f, INSTR_RXY_RRRD }, 1342 { "llgc", 0x90, INSTR_RXY_RRRD }, 1343 { "llgh", 0x91, INSTR_RXY_RRRD }, 1344 { "llc", 0x94, INSTR_RXY_RRRD }, 1345 { "llh", 0x95, INSTR_RXY_RRRD }, 1346 { { 0, LONG_INSN_LLGTAT }, 0x9c, INSTR_RXY_RRRD }, 1347 { { 0, LONG_INSN_LLGFAT }, 0x9d, INSTR_RXY_RRRD }, 1348 { "lat", 0x9f, INSTR_RXY_RRRD }, 1349 { "lbh", 0xc0, INSTR_RXY_RRRD }, 1350 { "llch", 0xc2, INSTR_RXY_RRRD }, 1351 { "stch", 0xc3, INSTR_RXY_RRRD }, 1352 { "lhh", 0xc4, INSTR_RXY_RRRD }, 1353 { "llhh", 0xc6, INSTR_RXY_RRRD }, 1354 { "sthh", 0xc7, INSTR_RXY_RRRD }, 1355 { "lfhat", 0xc8, INSTR_RXY_RRRD }, 1356 { "lfh", 0xca, INSTR_RXY_RRRD }, 1357 { "stfh", 0xcb, INSTR_RXY_RRRD }, 1358 { "chf", 0xcd, INSTR_RXY_RRRD }, 1359 { "clhf", 0xcf, INSTR_RXY_RRRD }, 1360 { { 0, LONG_INSN_MPCIFC }, 0xd0, INSTR_RXY_RRRD }, 1361 { { 0, LONG_INSN_STPCIFC }, 0xd4, INSTR_RXY_RRRD }, 1362 #endif 1363 { "lrv", 0x1e, INSTR_RXY_RRRD }, 1364 { "lrvh", 0x1f, INSTR_RXY_RRRD }, 1365 { "strv", 0x3e, INSTR_RXY_RRRD }, 1366 { "ml", 0x96, INSTR_RXY_RRRD }, 1367 { "dl", 0x97, INSTR_RXY_RRRD }, 1368 { "alc", 0x98, INSTR_RXY_RRRD }, 1369 { "slb", 0x99, INSTR_RXY_RRRD }, 1370 { "", 0, INSTR_INVALID } 1371 }; 1372 1373 static struct insn opcode_e5[] = { 1374 #ifdef CONFIG_64BIT 1375 { "strag", 0x02, INSTR_SSE_RDRD }, 1376 { "mvhhi", 0x44, INSTR_SIL_RDI }, 1377 { "mvghi", 0x48, INSTR_SIL_RDI }, 1378 { "mvhi", 0x4c, INSTR_SIL_RDI }, 1379 { "chhsi", 0x54, INSTR_SIL_RDI }, 1380 { { 0, LONG_INSN_CLHHSI }, 0x55, INSTR_SIL_RDU }, 1381 { "cghsi", 0x58, INSTR_SIL_RDI }, 1382 { { 0, LONG_INSN_CLGHSI }, 0x59, INSTR_SIL_RDU }, 1383 { "chsi", 0x5c, INSTR_SIL_RDI }, 1384 { { 0, LONG_INSN_CLFHSI }, 0x5d, INSTR_SIL_RDU }, 1385 { { 0, LONG_INSN_TBEGIN }, 0x60, INSTR_SIL_RDU }, 1386 { { 0, LONG_INSN_TBEGINC }, 0x61, INSTR_SIL_RDU }, 1387 #endif 1388 { "lasp", 0x00, INSTR_SSE_RDRD }, 1389 { "tprot", 0x01, INSTR_SSE_RDRD }, 1390 { "mvcsk", 0x0e, INSTR_SSE_RDRD }, 1391 { "mvcdk", 0x0f, INSTR_SSE_RDRD }, 1392 { "", 0, INSTR_INVALID } 1393 }; 1394 1395 static struct insn opcode_eb[] = { 1396 #ifdef CONFIG_64BIT 1397 { "lmg", 0x04, INSTR_RSY_RRRD }, 1398 { "srag", 0x0a, INSTR_RSY_RRRD }, 1399 { "slag", 0x0b, INSTR_RSY_RRRD }, 1400 { "srlg", 0x0c, INSTR_RSY_RRRD }, 1401 { "sllg", 0x0d, INSTR_RSY_RRRD }, 1402 { "tracg", 0x0f, INSTR_RSY_RRRD }, 1403 { "csy", 0x14, INSTR_RSY_RRRD }, 1404 { "rllg", 0x1c, INSTR_RSY_RRRD }, 1405 { "clmh", 0x20, INSTR_RSY_RURD }, 1406 { "clmy", 0x21, INSTR_RSY_RURD }, 1407 { "clt", 0x23, INSTR_RSY_RURD }, 1408 { "stmg", 0x24, INSTR_RSY_RRRD }, 1409 { "stctg", 0x25, INSTR_RSY_CCRD }, 1410 { "stmh", 0x26, INSTR_RSY_RRRD }, 1411 { "clgt", 0x2b, INSTR_RSY_RURD }, 1412 { "stcmh", 0x2c, INSTR_RSY_RURD }, 1413 { "stcmy", 0x2d, INSTR_RSY_RURD }, 1414 { "lctlg", 0x2f, INSTR_RSY_CCRD }, 1415 { "csg", 0x30, INSTR_RSY_RRRD }, 1416 { "cdsy", 0x31, INSTR_RSY_RRRD }, 1417 { "cdsg", 0x3e, INSTR_RSY_RRRD }, 1418 { "bxhg", 0x44, INSTR_RSY_RRRD }, 1419 { "bxleg", 0x45, INSTR_RSY_RRRD }, 1420 { "ecag", 0x4c, INSTR_RSY_RRRD }, 1421 { "tmy", 0x51, INSTR_SIY_URD }, 1422 { "mviy", 0x52, INSTR_SIY_URD }, 1423 { "niy", 0x54, INSTR_SIY_URD }, 1424 { "cliy", 0x55, INSTR_SIY_URD }, 1425 { "oiy", 0x56, INSTR_SIY_URD }, 1426 { "xiy", 0x57, INSTR_SIY_URD }, 1427 { "asi", 0x6a, INSTR_SIY_IRD }, 1428 { "alsi", 0x6e, INSTR_SIY_IRD }, 1429 { "agsi", 0x7a, INSTR_SIY_IRD }, 1430 { "algsi", 0x7e, INSTR_SIY_IRD }, 1431 { "icmh", 0x80, INSTR_RSY_RURD }, 1432 { "icmy", 0x81, INSTR_RSY_RURD }, 1433 { "clclu", 0x8f, INSTR_RSY_RRRD }, 1434 { "stmy", 0x90, INSTR_RSY_RRRD }, 1435 { "lmh", 0x96, INSTR_RSY_RRRD }, 1436 { "lmy", 0x98, INSTR_RSY_RRRD }, 1437 { "lamy", 0x9a, INSTR_RSY_AARD }, 1438 { "stamy", 0x9b, INSTR_RSY_AARD }, 1439 { { 0, LONG_INSN_PCISTB }, 0xd0, INSTR_RSY_RRRD }, 1440 { "sic", 0xd1, INSTR_RSY_RRRD }, 1441 { "srak", 0xdc, INSTR_RSY_RRRD }, 1442 { "slak", 0xdd, INSTR_RSY_RRRD }, 1443 { "srlk", 0xde, INSTR_RSY_RRRD }, 1444 { "sllk", 0xdf, INSTR_RSY_RRRD }, 1445 { "locg", 0xe2, INSTR_RSY_RDRM }, 1446 { "stocg", 0xe3, INSTR_RSY_RDRM }, 1447 { "lang", 0xe4, INSTR_RSY_RRRD }, 1448 { "laog", 0xe6, INSTR_RSY_RRRD }, 1449 { "laxg", 0xe7, INSTR_RSY_RRRD }, 1450 { "laag", 0xe8, INSTR_RSY_RRRD }, 1451 { "laalg", 0xea, INSTR_RSY_RRRD }, 1452 { "loc", 0xf2, INSTR_RSY_RDRM }, 1453 { "stoc", 0xf3, INSTR_RSY_RDRM }, 1454 { "lan", 0xf4, INSTR_RSY_RRRD }, 1455 { "lao", 0xf6, INSTR_RSY_RRRD }, 1456 { "lax", 0xf7, INSTR_RSY_RRRD }, 1457 { "laa", 0xf8, INSTR_RSY_RRRD }, 1458 { "laal", 0xfa, INSTR_RSY_RRRD }, 1459 { "lric", 0x60, INSTR_RSY_RDRM }, 1460 { "stric", 0x61, INSTR_RSY_RDRM }, 1461 { "mric", 0x62, INSTR_RSY_RDRM }, 1462 #endif 1463 { "rll", 0x1d, INSTR_RSY_RRRD }, 1464 { "mvclu", 0x8e, INSTR_RSY_RRRD }, 1465 { "tp", 0xc0, INSTR_RSL_R0RD }, 1466 { "", 0, INSTR_INVALID } 1467 }; 1468 1469 static struct insn opcode_ec[] = { 1470 #ifdef CONFIG_64BIT 1471 { "brxhg", 0x44, INSTR_RIE_RRP }, 1472 { "brxlg", 0x45, INSTR_RIE_RRP }, 1473 { { 0, LONG_INSN_RISBLG }, 0x51, INSTR_RIE_RRUUU }, 1474 { "rnsbg", 0x54, INSTR_RIE_RRUUU }, 1475 { "risbg", 0x55, INSTR_RIE_RRUUU }, 1476 { "rosbg", 0x56, INSTR_RIE_RRUUU }, 1477 { "rxsbg", 0x57, INSTR_RIE_RRUUU }, 1478 { { 0, LONG_INSN_RISBGN }, 0x59, INSTR_RIE_RRUUU }, 1479 { { 0, LONG_INSN_RISBHG }, 0x5D, INSTR_RIE_RRUUU }, 1480 { "cgrj", 0x64, INSTR_RIE_RRPU }, 1481 { "clgrj", 0x65, INSTR_RIE_RRPU }, 1482 { "cgit", 0x70, INSTR_RIE_R0IU }, 1483 { "clgit", 0x71, INSTR_RIE_R0UU }, 1484 { "cit", 0x72, INSTR_RIE_R0IU }, 1485 { "clfit", 0x73, INSTR_RIE_R0UU }, 1486 { "crj", 0x76, INSTR_RIE_RRPU }, 1487 { "clrj", 0x77, INSTR_RIE_RRPU }, 1488 { "cgij", 0x7c, INSTR_RIE_RUPI }, 1489 { "clgij", 0x7d, INSTR_RIE_RUPU }, 1490 { "cij", 0x7e, INSTR_RIE_RUPI }, 1491 { "clij", 0x7f, INSTR_RIE_RUPU }, 1492 { "ahik", 0xd8, INSTR_RIE_RRI0 }, 1493 { "aghik", 0xd9, INSTR_RIE_RRI0 }, 1494 { { 0, LONG_INSN_ALHSIK }, 0xda, INSTR_RIE_RRI0 }, 1495 { { 0, LONG_INSN_ALGHSIK }, 0xdb, INSTR_RIE_RRI0 }, 1496 { "cgrb", 0xe4, INSTR_RRS_RRRDU }, 1497 { "clgrb", 0xe5, INSTR_RRS_RRRDU }, 1498 { "crb", 0xf6, INSTR_RRS_RRRDU }, 1499 { "clrb", 0xf7, INSTR_RRS_RRRDU }, 1500 { "cgib", 0xfc, INSTR_RIS_RURDI }, 1501 { "clgib", 0xfd, INSTR_RIS_RURDU }, 1502 { "cib", 0xfe, INSTR_RIS_RURDI }, 1503 { "clib", 0xff, INSTR_RIS_RURDU }, 1504 #endif 1505 { "", 0, INSTR_INVALID } 1506 }; 1507 1508 static struct insn opcode_ed[] = { 1509 #ifdef CONFIG_64BIT 1510 { "mayl", 0x38, INSTR_RXF_FRRDF }, 1511 { "myl", 0x39, INSTR_RXF_FRRDF }, 1512 { "may", 0x3a, INSTR_RXF_FRRDF }, 1513 { "my", 0x3b, INSTR_RXF_FRRDF }, 1514 { "mayh", 0x3c, INSTR_RXF_FRRDF }, 1515 { "myh", 0x3d, INSTR_RXF_FRRDF }, 1516 { "sldt", 0x40, INSTR_RXF_FRRDF }, 1517 { "srdt", 0x41, INSTR_RXF_FRRDF }, 1518 { "slxt", 0x48, INSTR_RXF_FRRDF }, 1519 { "srxt", 0x49, INSTR_RXF_FRRDF }, 1520 { "tdcet", 0x50, INSTR_RXE_FRRD }, 1521 { "tdget", 0x51, INSTR_RXE_FRRD }, 1522 { "tdcdt", 0x54, INSTR_RXE_FRRD }, 1523 { "tdgdt", 0x55, INSTR_RXE_FRRD }, 1524 { "tdcxt", 0x58, INSTR_RXE_FRRD }, 1525 { "tdgxt", 0x59, INSTR_RXE_FRRD }, 1526 { "ley", 0x64, INSTR_RXY_FRRD }, 1527 { "ldy", 0x65, INSTR_RXY_FRRD }, 1528 { "stey", 0x66, INSTR_RXY_FRRD }, 1529 { "stdy", 0x67, INSTR_RXY_FRRD }, 1530 { "czdt", 0xa8, INSTR_RSL_LRDFU }, 1531 { "czxt", 0xa9, INSTR_RSL_LRDFU }, 1532 { "cdzt", 0xaa, INSTR_RSL_LRDFU }, 1533 { "cxzt", 0xab, INSTR_RSL_LRDFU }, 1534 #endif 1535 { "ldeb", 0x04, INSTR_RXE_FRRD }, 1536 { "lxdb", 0x05, INSTR_RXE_FRRD }, 1537 { "lxeb", 0x06, INSTR_RXE_FRRD }, 1538 { "mxdb", 0x07, INSTR_RXE_FRRD }, 1539 { "keb", 0x08, INSTR_RXE_FRRD }, 1540 { "ceb", 0x09, INSTR_RXE_FRRD }, 1541 { "aeb", 0x0a, INSTR_RXE_FRRD }, 1542 { "seb", 0x0b, INSTR_RXE_FRRD }, 1543 { "mdeb", 0x0c, INSTR_RXE_FRRD }, 1544 { "deb", 0x0d, INSTR_RXE_FRRD }, 1545 { "maeb", 0x0e, INSTR_RXF_FRRDF }, 1546 { "mseb", 0x0f, INSTR_RXF_FRRDF }, 1547 { "tceb", 0x10, INSTR_RXE_FRRD }, 1548 { "tcdb", 0x11, INSTR_RXE_FRRD }, 1549 { "tcxb", 0x12, INSTR_RXE_FRRD }, 1550 { "sqeb", 0x14, INSTR_RXE_FRRD }, 1551 { "sqdb", 0x15, INSTR_RXE_FRRD }, 1552 { "meeb", 0x17, INSTR_RXE_FRRD }, 1553 { "kdb", 0x18, INSTR_RXE_FRRD }, 1554 { "cdb", 0x19, INSTR_RXE_FRRD }, 1555 { "adb", 0x1a, INSTR_RXE_FRRD }, 1556 { "sdb", 0x1b, INSTR_RXE_FRRD }, 1557 { "mdb", 0x1c, INSTR_RXE_FRRD }, 1558 { "ddb", 0x1d, INSTR_RXE_FRRD }, 1559 { "madb", 0x1e, INSTR_RXF_FRRDF }, 1560 { "msdb", 0x1f, INSTR_RXF_FRRDF }, 1561 { "lde", 0x24, INSTR_RXE_FRRD }, 1562 { "lxd", 0x25, INSTR_RXE_FRRD }, 1563 { "lxe", 0x26, INSTR_RXE_FRRD }, 1564 { "mae", 0x2e, INSTR_RXF_FRRDF }, 1565 { "mse", 0x2f, INSTR_RXF_FRRDF }, 1566 { "sqe", 0x34, INSTR_RXE_FRRD }, 1567 { "sqd", 0x35, INSTR_RXE_FRRD }, 1568 { "mee", 0x37, INSTR_RXE_FRRD }, 1569 { "mad", 0x3e, INSTR_RXF_FRRDF }, 1570 { "msd", 0x3f, INSTR_RXF_FRRDF }, 1571 { "", 0, INSTR_INVALID } 1572 }; 1573 1574 /* Extracts an operand value from an instruction. */ 1575 static unsigned int extract_operand(unsigned char *code, 1576 const struct operand *operand) 1577 { 1578 unsigned int val; 1579 int bits; 1580 1581 /* Extract fragments of the operand byte for byte. */ 1582 code += operand->shift / 8; 1583 bits = (operand->shift & 7) + operand->bits; 1584 val = 0; 1585 do { 1586 val <<= 8; 1587 val |= (unsigned int) *code++; 1588 bits -= 8; 1589 } while (bits > 0); 1590 val >>= -bits; 1591 val &= ((1U << (operand->bits - 1)) << 1) - 1; 1592 1593 /* Check for special long displacement case. */ 1594 if (operand->bits == 20 && operand->shift == 20) 1595 val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; 1596 1597 /* Sign extend value if the operand is signed or pc relative. */ 1598 if ((operand->flags & (OPERAND_SIGNED | OPERAND_PCREL)) && 1599 (val & (1U << (operand->bits - 1)))) 1600 val |= (-1U << (operand->bits - 1)) << 1; 1601 1602 /* Double value if the operand is pc relative. */ 1603 if (operand->flags & OPERAND_PCREL) 1604 val <<= 1; 1605 1606 /* Length x in an instructions has real length x + 1. */ 1607 if (operand->flags & OPERAND_LENGTH) 1608 val++; 1609 return val; 1610 } 1611 1612 static inline int insn_length(unsigned char code) 1613 { 1614 return ((((int) code + 64) >> 7) + 1) << 1; 1615 } 1616 1617 static struct insn *find_insn(unsigned char *code) 1618 { 1619 unsigned char opfrag = code[1]; 1620 unsigned char opmask; 1621 struct insn *table; 1622 1623 switch (code[0]) { 1624 case 0x01: 1625 table = opcode_01; 1626 break; 1627 case 0xa5: 1628 table = opcode_a5; 1629 break; 1630 case 0xa7: 1631 table = opcode_a7; 1632 break; 1633 case 0xaa: 1634 table = opcode_aa; 1635 break; 1636 case 0xb2: 1637 table = opcode_b2; 1638 break; 1639 case 0xb3: 1640 table = opcode_b3; 1641 break; 1642 case 0xb9: 1643 table = opcode_b9; 1644 break; 1645 case 0xc0: 1646 table = opcode_c0; 1647 break; 1648 case 0xc2: 1649 table = opcode_c2; 1650 break; 1651 case 0xc4: 1652 table = opcode_c4; 1653 break; 1654 case 0xc6: 1655 table = opcode_c6; 1656 break; 1657 case 0xc8: 1658 table = opcode_c8; 1659 break; 1660 case 0xcc: 1661 table = opcode_cc; 1662 break; 1663 case 0xe3: 1664 table = opcode_e3; 1665 opfrag = code[5]; 1666 break; 1667 case 0xe5: 1668 table = opcode_e5; 1669 break; 1670 case 0xeb: 1671 table = opcode_eb; 1672 opfrag = code[5]; 1673 break; 1674 case 0xec: 1675 table = opcode_ec; 1676 opfrag = code[5]; 1677 break; 1678 case 0xed: 1679 table = opcode_ed; 1680 opfrag = code[5]; 1681 break; 1682 default: 1683 table = opcode; 1684 opfrag = code[0]; 1685 break; 1686 } 1687 while (table->format != INSTR_INVALID) { 1688 opmask = formats[table->format][0]; 1689 if (table->opfrag == (opfrag & opmask)) 1690 return table; 1691 table++; 1692 } 1693 return NULL; 1694 } 1695 1696 /** 1697 * insn_to_mnemonic - decode an s390 instruction 1698 * @instruction: instruction to decode 1699 * @buf: buffer to fill with mnemonic 1700 * 1701 * Decode the instruction at @instruction and store the corresponding 1702 * mnemonic into @buf. 1703 * @buf is left unchanged if the instruction could not be decoded. 1704 * Returns: 1705 * %0 on success, %-ENOENT if the instruction was not found. 1706 */ 1707 int insn_to_mnemonic(unsigned char *instruction, char buf[8]) 1708 { 1709 struct insn *insn; 1710 1711 insn = find_insn(instruction); 1712 if (!insn) 1713 return -ENOENT; 1714 if (insn->name[0] == '\0') 1715 snprintf(buf, sizeof(buf), "%s", 1716 long_insn_name[(int) insn->name[1]]); 1717 else 1718 snprintf(buf, sizeof(buf), "%.5s", insn->name); 1719 return 0; 1720 } 1721 EXPORT_SYMBOL_GPL(insn_to_mnemonic); 1722 1723 static int print_insn(char *buffer, unsigned char *code, unsigned long addr) 1724 { 1725 struct insn *insn; 1726 const unsigned char *ops; 1727 const struct operand *operand; 1728 unsigned int value; 1729 char separator; 1730 char *ptr; 1731 int i; 1732 1733 ptr = buffer; 1734 insn = find_insn(code); 1735 if (insn) { 1736 if (insn->name[0] == '\0') 1737 ptr += sprintf(ptr, "%s\t", 1738 long_insn_name[(int) insn->name[1]]); 1739 else 1740 ptr += sprintf(ptr, "%.5s\t", insn->name); 1741 /* Extract the operands. */ 1742 separator = 0; 1743 for (ops = formats[insn->format] + 1, i = 0; 1744 *ops != 0 && i < 6; ops++, i++) { 1745 operand = operands + *ops; 1746 value = extract_operand(code, operand); 1747 if ((operand->flags & OPERAND_INDEX) && value == 0) 1748 continue; 1749 if ((operand->flags & OPERAND_BASE) && 1750 value == 0 && separator == '(') { 1751 separator = ','; 1752 continue; 1753 } 1754 if (separator) 1755 ptr += sprintf(ptr, "%c", separator); 1756 if (operand->flags & OPERAND_GPR) 1757 ptr += sprintf(ptr, "%%r%i", value); 1758 else if (operand->flags & OPERAND_FPR) 1759 ptr += sprintf(ptr, "%%f%i", value); 1760 else if (operand->flags & OPERAND_AR) 1761 ptr += sprintf(ptr, "%%a%i", value); 1762 else if (operand->flags & OPERAND_CR) 1763 ptr += sprintf(ptr, "%%c%i", value); 1764 else if (operand->flags & OPERAND_PCREL) 1765 ptr += sprintf(ptr, "%lx", (signed int) value 1766 + addr); 1767 else if (operand->flags & OPERAND_SIGNED) 1768 ptr += sprintf(ptr, "%i", value); 1769 else 1770 ptr += sprintf(ptr, "%u", value); 1771 if (operand->flags & OPERAND_DISP) 1772 separator = '('; 1773 else if (operand->flags & OPERAND_BASE) { 1774 ptr += sprintf(ptr, ")"); 1775 separator = ','; 1776 } else 1777 separator = ','; 1778 } 1779 } else 1780 ptr += sprintf(ptr, "unknown"); 1781 return (int) (ptr - buffer); 1782 } 1783 1784 void show_code(struct pt_regs *regs) 1785 { 1786 char *mode = user_mode(regs) ? "User" : "Krnl"; 1787 unsigned char code[64]; 1788 char buffer[64], *ptr; 1789 mm_segment_t old_fs; 1790 unsigned long addr; 1791 int start, end, opsize, hops, i; 1792 1793 /* Get a snapshot of the 64 bytes surrounding the fault address. */ 1794 old_fs = get_fs(); 1795 set_fs(user_mode(regs) ? USER_DS : KERNEL_DS); 1796 for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) { 1797 addr = regs->psw.addr - 34 + start; 1798 if (__copy_from_user(code + start - 2, 1799 (char __user *) addr, 2)) 1800 break; 1801 } 1802 for (end = 32; end < 64; end += 2) { 1803 addr = regs->psw.addr + end - 32; 1804 if (__copy_from_user(code + end, 1805 (char __user *) addr, 2)) 1806 break; 1807 } 1808 set_fs(old_fs); 1809 /* Code snapshot useable ? */ 1810 if ((regs->psw.addr & 1) || start >= end) { 1811 printk("%s Code: Bad PSW.\n", mode); 1812 return; 1813 } 1814 /* Find a starting point for the disassembly. */ 1815 while (start < 32) { 1816 for (i = 0, hops = 0; start + i < 32 && hops < 3; hops++) { 1817 if (!find_insn(code + start + i)) 1818 break; 1819 i += insn_length(code[start + i]); 1820 } 1821 if (start + i == 32) 1822 /* Looks good, sequence ends at PSW. */ 1823 break; 1824 start += 2; 1825 } 1826 /* Decode the instructions. */ 1827 ptr = buffer; 1828 ptr += sprintf(ptr, "%s Code:", mode); 1829 hops = 0; 1830 while (start < end && hops < 8) { 1831 opsize = insn_length(code[start]); 1832 if (start + opsize == 32) 1833 *ptr++ = '#'; 1834 else if (start == 32) 1835 *ptr++ = '>'; 1836 else 1837 *ptr++ = ' '; 1838 addr = regs->psw.addr + start - 32; 1839 ptr += sprintf(ptr, ONELONG, addr); 1840 if (start + opsize >= end) 1841 break; 1842 for (i = 0; i < opsize; i++) 1843 ptr += sprintf(ptr, "%02x", code[start + i]); 1844 *ptr++ = '\t'; 1845 if (i < 6) 1846 *ptr++ = '\t'; 1847 ptr += print_insn(ptr, code + start, addr); 1848 start += opsize; 1849 printk(buffer); 1850 ptr = buffer; 1851 ptr += sprintf(ptr, "\n "); 1852 hops++; 1853 } 1854 printk("\n"); 1855 } 1856 1857 void print_fn_code(unsigned char *code, unsigned long len) 1858 { 1859 char buffer[64], *ptr; 1860 int opsize, i; 1861 1862 while (len) { 1863 ptr = buffer; 1864 opsize = insn_length(*code); 1865 ptr += sprintf(ptr, "%p: ", code); 1866 for (i = 0; i < opsize; i++) 1867 ptr += sprintf(ptr, "%02x", code[i]); 1868 *ptr++ = '\t'; 1869 if (i < 4) 1870 *ptr++ = '\t'; 1871 ptr += print_insn(ptr, code, (unsigned long) code); 1872 *ptr++ = '\n'; 1873 *ptr++ = 0; 1874 printk(buffer); 1875 code += opsize; 1876 len -= opsize; 1877 } 1878 } 1879