1 #ifndef _S390_TLB_H 2 #define _S390_TLB_H 3 4 /* 5 * TLB flushing on s390 is complicated. The following requirement 6 * from the principles of operation is the most arduous: 7 * 8 * "A valid table entry must not be changed while it is attached 9 * to any CPU and may be used for translation by that CPU except to 10 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 11 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page 12 * table entry, or (3) make a change by means of a COMPARE AND SWAP 13 * AND PURGE instruction that purges the TLB." 14 * 15 * The modification of a pte of an active mm struct therefore is 16 * a two step process: i) invalidate the pte, ii) store the new pte. 17 * This is true for the page protection bit as well. 18 * The only possible optimization is to flush at the beginning of 19 * a tlb_gather_mmu cycle if the mm_struct is currently not in use. 20 * 21 * Pages used for the page tables is a different story. FIXME: more 22 */ 23 24 #include <linux/mm.h> 25 #include <linux/swap.h> 26 #include <asm/processor.h> 27 #include <asm/pgalloc.h> 28 #include <asm/smp.h> 29 #include <asm/tlbflush.h> 30 31 #ifndef CONFIG_SMP 32 #define TLB_NR_PTRS 1 33 #else 34 #define TLB_NR_PTRS 508 35 #endif 36 37 struct mmu_gather { 38 struct mm_struct *mm; 39 unsigned int fullmm; 40 unsigned int nr_ptes; 41 unsigned int nr_pxds; 42 void *array[TLB_NR_PTRS]; 43 }; 44 45 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers); 46 47 static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, 48 unsigned int full_mm_flush) 49 { 50 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers); 51 52 tlb->mm = mm; 53 tlb->fullmm = full_mm_flush || (num_online_cpus() == 1) || 54 (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm); 55 tlb->nr_ptes = 0; 56 tlb->nr_pxds = TLB_NR_PTRS; 57 if (tlb->fullmm) 58 __tlb_flush_mm(mm); 59 return tlb; 60 } 61 62 static inline void tlb_flush_mmu(struct mmu_gather *tlb, 63 unsigned long start, unsigned long end) 64 { 65 if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS)) 66 __tlb_flush_mm(tlb->mm); 67 while (tlb->nr_ptes > 0) 68 pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]); 69 while (tlb->nr_pxds < TLB_NR_PTRS) 70 /* pgd_free frees the pointer as region or segment table */ 71 pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]); 72 } 73 74 static inline void tlb_finish_mmu(struct mmu_gather *tlb, 75 unsigned long start, unsigned long end) 76 { 77 tlb_flush_mmu(tlb, start, end); 78 79 /* keep the page table cache within bounds */ 80 check_pgt_cache(); 81 82 put_cpu_var(mmu_gathers); 83 } 84 85 /* 86 * Release the page cache reference for a pte removed by 87 * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page 88 * has already been freed, so just do free_page_and_swap_cache. 89 */ 90 static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) 91 { 92 free_page_and_swap_cache(page); 93 } 94 95 /* 96 * pte_free_tlb frees a pte table and clears the CRSTE for the 97 * page table from the tlb. 98 */ 99 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 100 unsigned long address) 101 { 102 if (!tlb->fullmm) { 103 tlb->array[tlb->nr_ptes++] = pte; 104 if (tlb->nr_ptes >= tlb->nr_pxds) 105 tlb_flush_mmu(tlb, 0, 0); 106 } else 107 pte_free(tlb->mm, pte); 108 } 109 110 /* 111 * pmd_free_tlb frees a pmd table and clears the CRSTE for the 112 * segment table entry from the tlb. 113 * If the mm uses a two level page table the single pmd is freed 114 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB 115 * to avoid the double free of the pmd in this case. 116 */ 117 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, 118 unsigned long address) 119 { 120 #ifdef __s390x__ 121 if (tlb->mm->context.asce_limit <= (1UL << 31)) 122 return; 123 if (!tlb->fullmm) { 124 tlb->array[--tlb->nr_pxds] = pmd; 125 if (tlb->nr_ptes >= tlb->nr_pxds) 126 tlb_flush_mmu(tlb, 0, 0); 127 } else 128 pmd_free(tlb->mm, pmd); 129 #endif 130 } 131 132 /* 133 * pud_free_tlb frees a pud table and clears the CRSTE for the 134 * region third table entry from the tlb. 135 * If the mm uses a three level page table the single pud is freed 136 * as the pgd. pud_free_tlb checks the asce_limit against 4TB 137 * to avoid the double free of the pud in this case. 138 */ 139 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, 140 unsigned long address) 141 { 142 #ifdef __s390x__ 143 if (tlb->mm->context.asce_limit <= (1UL << 42)) 144 return; 145 if (!tlb->fullmm) { 146 tlb->array[--tlb->nr_pxds] = pud; 147 if (tlb->nr_ptes >= tlb->nr_pxds) 148 tlb_flush_mmu(tlb, 0, 0); 149 } else 150 pud_free(tlb->mm, pud); 151 #endif 152 } 153 154 #define tlb_start_vma(tlb, vma) do { } while (0) 155 #define tlb_end_vma(tlb, vma) do { } while (0) 156 #define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0) 157 #define tlb_migrate_finish(mm) do { } while (0) 158 159 #endif /* _S390_TLB_H */ 160