1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _S390_TLB_H 3 #define _S390_TLB_H 4 5 /* 6 * TLB flushing on s390 is complicated. The following requirement 7 * from the principles of operation is the most arduous: 8 * 9 * "A valid table entry must not be changed while it is attached 10 * to any CPU and may be used for translation by that CPU except to 11 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page 13 * table entry, or (3) make a change by means of a COMPARE AND SWAP 14 * AND PURGE instruction that purges the TLB." 15 * 16 * The modification of a pte of an active mm struct therefore is 17 * a two step process: i) invalidate the pte, ii) store the new pte. 18 * This is true for the page protection bit as well. 19 * The only possible optimization is to flush at the beginning of 20 * a tlb_gather_mmu cycle if the mm_struct is currently not in use. 21 * 22 * Pages used for the page tables is a different story. FIXME: more 23 */ 24 25 static inline void tlb_flush(struct mmu_gather *tlb); 26 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 27 struct page *page, int page_size); 28 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 29 struct page *page, unsigned int nr_pages, bool delay_rmap); 30 31 #define tlb_flush tlb_flush 32 #define pte_free_tlb pte_free_tlb 33 #define pmd_free_tlb pmd_free_tlb 34 #define p4d_free_tlb p4d_free_tlb 35 #define pud_free_tlb pud_free_tlb 36 37 #include <asm/tlbflush.h> 38 #include <asm-generic/tlb.h> 39 40 /* 41 * Release the page cache reference for a pte removed by 42 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page 43 * has already been freed, so just do free_folio_and_swap_cache. 44 * 45 * s390 doesn't delay rmap removal. 46 */ 47 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 48 struct page *page, int page_size) 49 { 50 free_folio_and_swap_cache(page_folio(page)); 51 return false; 52 } 53 54 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 55 struct page *page, unsigned int nr_pages, bool delay_rmap) 56 { 57 struct encoded_page *encoded_pages[] = { 58 encode_page(page, ENCODED_PAGE_BIT_NR_PAGES_NEXT), 59 encode_nr_pages(nr_pages), 60 }; 61 62 VM_WARN_ON_ONCE(delay_rmap); 63 VM_WARN_ON_ONCE(page_folio(page) != page_folio(page + nr_pages - 1)); 64 65 free_pages_and_swap_cache(encoded_pages, ARRAY_SIZE(encoded_pages)); 66 return false; 67 } 68 69 static inline void tlb_flush(struct mmu_gather *tlb) 70 { 71 __tlb_flush_mm_lazy(tlb->mm); 72 } 73 74 /* 75 * pte_free_tlb frees a pte table and clears the CRSTE for the 76 * page table from the tlb. 77 */ 78 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 79 unsigned long address) 80 { 81 __tlb_adjust_range(tlb, address, PAGE_SIZE); 82 tlb->mm->context.flush_mm = 1; 83 tlb->freed_tables = 1; 84 tlb->cleared_pmds = 1; 85 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pte)); 86 } 87 88 /* 89 * pmd_free_tlb frees a pmd table and clears the CRSTE for the 90 * segment table entry from the tlb. 91 * If the mm uses a two level page table the single pmd is freed 92 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB 93 * to avoid the double free of the pmd in this case. 94 */ 95 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, 96 unsigned long address) 97 { 98 if (mm_pmd_folded(tlb->mm)) 99 return; 100 __tlb_adjust_range(tlb, address, PAGE_SIZE); 101 tlb->mm->context.flush_mm = 1; 102 tlb->freed_tables = 1; 103 tlb->cleared_puds = 1; 104 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pmd)); 105 } 106 107 /* 108 * p4d_free_tlb frees a pud table and clears the CRSTE for the 109 * region second table entry from the tlb. 110 * If the mm uses a four level page table the single p4d is freed 111 * as the pgd. p4d_free_tlb checks the asce_limit against 8PB 112 * to avoid the double free of the p4d in this case. 113 */ 114 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d, 115 unsigned long address) 116 { 117 if (mm_p4d_folded(tlb->mm)) 118 return; 119 __tlb_adjust_range(tlb, address, PAGE_SIZE); 120 tlb->mm->context.flush_mm = 1; 121 tlb->freed_tables = 1; 122 tlb_remove_ptdesc(tlb, virt_to_ptdesc(p4d)); 123 } 124 125 /* 126 * pud_free_tlb frees a pud table and clears the CRSTE for the 127 * region third table entry from the tlb. 128 * If the mm uses a three level page table the single pud is freed 129 * as the pgd. pud_free_tlb checks the asce_limit against 4TB 130 * to avoid the double free of the pud in this case. 131 */ 132 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, 133 unsigned long address) 134 { 135 if (mm_pud_folded(tlb->mm)) 136 return; 137 __tlb_adjust_range(tlb, address, PAGE_SIZE); 138 tlb->mm->context.flush_mm = 1; 139 tlb->freed_tables = 1; 140 tlb->cleared_p4ds = 1; 141 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pud)); 142 } 143 144 #endif /* _S390_TLB_H */ 145