1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _S390_TLB_H 3 #define _S390_TLB_H 4 5 /* 6 * TLB flushing on s390 is complicated. The following requirement 7 * from the principles of operation is the most arduous: 8 * 9 * "A valid table entry must not be changed while it is attached 10 * to any CPU and may be used for translation by that CPU except to 11 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page 13 * table entry, or (3) make a change by means of a COMPARE AND SWAP 14 * AND PURGE instruction that purges the TLB." 15 * 16 * The modification of a pte of an active mm struct therefore is 17 * a two step process: i) invalidate the pte, ii) store the new pte. 18 * This is true for the page protection bit as well. 19 * The only possible optimization is to flush at the beginning of 20 * a tlb_gather_mmu cycle if the mm_struct is currently not in use. 21 * 22 * Pages used for the page tables is a different story. FIXME: more 23 */ 24 25 void __tlb_remove_table(void *_table); 26 static inline void tlb_flush(struct mmu_gather *tlb); 27 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 28 struct page *page, bool delay_rmap, int page_size); 29 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 30 struct page *page, unsigned int nr_pages, bool delay_rmap); 31 32 #define tlb_flush tlb_flush 33 #define pte_free_tlb pte_free_tlb 34 #define pmd_free_tlb pmd_free_tlb 35 #define p4d_free_tlb p4d_free_tlb 36 #define pud_free_tlb pud_free_tlb 37 38 #include <asm/tlbflush.h> 39 #include <asm-generic/tlb.h> 40 41 /* 42 * Release the page cache reference for a pte removed by 43 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page 44 * has already been freed, so just do free_page_and_swap_cache. 45 * 46 * s390 doesn't delay rmap removal. 47 */ 48 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 49 struct page *page, bool delay_rmap, int page_size) 50 { 51 VM_WARN_ON_ONCE(delay_rmap); 52 53 free_page_and_swap_cache(page); 54 return false; 55 } 56 57 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 58 struct page *page, unsigned int nr_pages, bool delay_rmap) 59 { 60 struct encoded_page *encoded_pages[] = { 61 encode_page(page, ENCODED_PAGE_BIT_NR_PAGES_NEXT), 62 encode_nr_pages(nr_pages), 63 }; 64 65 VM_WARN_ON_ONCE(delay_rmap); 66 VM_WARN_ON_ONCE(page_folio(page) != page_folio(page + nr_pages - 1)); 67 68 free_pages_and_swap_cache(encoded_pages, ARRAY_SIZE(encoded_pages)); 69 return false; 70 } 71 72 static inline void tlb_flush(struct mmu_gather *tlb) 73 { 74 __tlb_flush_mm_lazy(tlb->mm); 75 } 76 77 /* 78 * pte_free_tlb frees a pte table and clears the CRSTE for the 79 * page table from the tlb. 80 */ 81 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 82 unsigned long address) 83 { 84 __tlb_adjust_range(tlb, address, PAGE_SIZE); 85 tlb->mm->context.flush_mm = 1; 86 tlb->freed_tables = 1; 87 tlb->cleared_pmds = 1; 88 if (mm_alloc_pgste(tlb->mm)) 89 gmap_unlink(tlb->mm, (unsigned long *)pte, address); 90 tlb_remove_ptdesc(tlb, pte); 91 } 92 93 /* 94 * pmd_free_tlb frees a pmd table and clears the CRSTE for the 95 * segment table entry from the tlb. 96 * If the mm uses a two level page table the single pmd is freed 97 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB 98 * to avoid the double free of the pmd in this case. 99 */ 100 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, 101 unsigned long address) 102 { 103 if (mm_pmd_folded(tlb->mm)) 104 return; 105 pagetable_pmd_dtor(virt_to_ptdesc(pmd)); 106 __tlb_adjust_range(tlb, address, PAGE_SIZE); 107 tlb->mm->context.flush_mm = 1; 108 tlb->freed_tables = 1; 109 tlb->cleared_puds = 1; 110 tlb_remove_ptdesc(tlb, pmd); 111 } 112 113 /* 114 * p4d_free_tlb frees a pud table and clears the CRSTE for the 115 * region second table entry from the tlb. 116 * If the mm uses a four level page table the single p4d is freed 117 * as the pgd. p4d_free_tlb checks the asce_limit against 8PB 118 * to avoid the double free of the p4d in this case. 119 */ 120 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d, 121 unsigned long address) 122 { 123 if (mm_p4d_folded(tlb->mm)) 124 return; 125 __tlb_adjust_range(tlb, address, PAGE_SIZE); 126 tlb->mm->context.flush_mm = 1; 127 tlb->freed_tables = 1; 128 tlb_remove_ptdesc(tlb, p4d); 129 } 130 131 /* 132 * pud_free_tlb frees a pud table and clears the CRSTE for the 133 * region third table entry from the tlb. 134 * If the mm uses a three level page table the single pud is freed 135 * as the pgd. pud_free_tlb checks the asce_limit against 4TB 136 * to avoid the double free of the pud in this case. 137 */ 138 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, 139 unsigned long address) 140 { 141 if (mm_pud_folded(tlb->mm)) 142 return; 143 tlb->mm->context.flush_mm = 1; 144 tlb->freed_tables = 1; 145 tlb->cleared_p4ds = 1; 146 tlb_remove_ptdesc(tlb, pud); 147 } 148 149 150 #endif /* _S390_TLB_H */ 151