1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _S390_TLB_H 3 #define _S390_TLB_H 4 5 /* 6 * TLB flushing on s390 is complicated. The following requirement 7 * from the principles of operation is the most arduous: 8 * 9 * "A valid table entry must not be changed while it is attached 10 * to any CPU and may be used for translation by that CPU except to 11 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 12 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page 13 * table entry, or (3) make a change by means of a COMPARE AND SWAP 14 * AND PURGE instruction that purges the TLB." 15 * 16 * The modification of a pte of an active mm struct therefore is 17 * a two step process: i) invalidate the pte, ii) store the new pte. 18 * This is true for the page protection bit as well. 19 * The only possible optimization is to flush at the beginning of 20 * a tlb_gather_mmu cycle if the mm_struct is currently not in use. 21 * 22 * Pages used for the page tables is a different story. FIXME: more 23 */ 24 25 static inline void tlb_flush(struct mmu_gather *tlb); 26 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 27 struct page *page, int page_size); 28 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 29 struct page *page, unsigned int nr_pages, bool delay_rmap); 30 31 #define tlb_flush tlb_flush 32 #define pte_free_tlb pte_free_tlb 33 #define pmd_free_tlb pmd_free_tlb 34 #define p4d_free_tlb p4d_free_tlb 35 #define pud_free_tlb pud_free_tlb 36 37 #include <asm/tlbflush.h> 38 #include <asm-generic/tlb.h> 39 #include <asm/gmap.h> 40 41 /* 42 * Release the page cache reference for a pte removed by 43 * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page 44 * has already been freed, so just do free_folio_and_swap_cache. 45 * 46 * s390 doesn't delay rmap removal. 47 */ 48 static inline bool __tlb_remove_page_size(struct mmu_gather *tlb, 49 struct page *page, int page_size) 50 { 51 free_folio_and_swap_cache(page_folio(page)); 52 return false; 53 } 54 55 static inline bool __tlb_remove_folio_pages(struct mmu_gather *tlb, 56 struct page *page, unsigned int nr_pages, bool delay_rmap) 57 { 58 struct encoded_page *encoded_pages[] = { 59 encode_page(page, ENCODED_PAGE_BIT_NR_PAGES_NEXT), 60 encode_nr_pages(nr_pages), 61 }; 62 63 VM_WARN_ON_ONCE(delay_rmap); 64 VM_WARN_ON_ONCE(page_folio(page) != page_folio(page + nr_pages - 1)); 65 66 free_pages_and_swap_cache(encoded_pages, ARRAY_SIZE(encoded_pages)); 67 return false; 68 } 69 70 static inline void tlb_flush(struct mmu_gather *tlb) 71 { 72 __tlb_flush_mm_lazy(tlb->mm); 73 } 74 75 /* 76 * pte_free_tlb frees a pte table and clears the CRSTE for the 77 * page table from the tlb. 78 */ 79 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, 80 unsigned long address) 81 { 82 __tlb_adjust_range(tlb, address, PAGE_SIZE); 83 tlb->mm->context.flush_mm = 1; 84 tlb->freed_tables = 1; 85 tlb->cleared_pmds = 1; 86 if (mm_has_pgste(tlb->mm)) 87 gmap_unlink(tlb->mm, (unsigned long *)pte, address); 88 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pte)); 89 } 90 91 /* 92 * pmd_free_tlb frees a pmd table and clears the CRSTE for the 93 * segment table entry from the tlb. 94 * If the mm uses a two level page table the single pmd is freed 95 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB 96 * to avoid the double free of the pmd in this case. 97 */ 98 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, 99 unsigned long address) 100 { 101 if (mm_pmd_folded(tlb->mm)) 102 return; 103 __tlb_adjust_range(tlb, address, PAGE_SIZE); 104 tlb->mm->context.flush_mm = 1; 105 tlb->freed_tables = 1; 106 tlb->cleared_puds = 1; 107 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pmd)); 108 } 109 110 /* 111 * p4d_free_tlb frees a pud table and clears the CRSTE for the 112 * region second table entry from the tlb. 113 * If the mm uses a four level page table the single p4d is freed 114 * as the pgd. p4d_free_tlb checks the asce_limit against 8PB 115 * to avoid the double free of the p4d in this case. 116 */ 117 static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d, 118 unsigned long address) 119 { 120 if (mm_p4d_folded(tlb->mm)) 121 return; 122 __tlb_adjust_range(tlb, address, PAGE_SIZE); 123 tlb->mm->context.flush_mm = 1; 124 tlb->freed_tables = 1; 125 tlb_remove_ptdesc(tlb, virt_to_ptdesc(p4d)); 126 } 127 128 /* 129 * pud_free_tlb frees a pud table and clears the CRSTE for the 130 * region third table entry from the tlb. 131 * If the mm uses a three level page table the single pud is freed 132 * as the pgd. pud_free_tlb checks the asce_limit against 4TB 133 * to avoid the double free of the pud in this case. 134 */ 135 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, 136 unsigned long address) 137 { 138 if (mm_pud_folded(tlb->mm)) 139 return; 140 __tlb_adjust_range(tlb, address, PAGE_SIZE); 141 tlb->mm->context.flush_mm = 1; 142 tlb->freed_tables = 1; 143 tlb->cleared_p4ds = 1; 144 tlb_remove_ptdesc(tlb, virt_to_ptdesc(pud)); 145 } 146 147 #endif /* _S390_TLB_H */ 148