1 /* 2 * Routines and structures for signalling other processors. 3 * 4 * Copyright IBM Corp. 1999,2010 5 * Author(s): Denis Joseph Barrow, 6 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 7 * Heiko Carstens <heiko.carstens@de.ibm.com>, 8 */ 9 10 #ifndef __ASM_SIGP_H 11 #define __ASM_SIGP_H 12 13 #include <asm/system.h> 14 15 /* Get real cpu address from logical cpu number. */ 16 extern unsigned short __cpu_logical_map[]; 17 18 static inline int cpu_logical_map(int cpu) 19 { 20 #ifdef CONFIG_SMP 21 return __cpu_logical_map[cpu]; 22 #else 23 return stap(); 24 #endif 25 } 26 27 enum { 28 sigp_sense = 1, 29 sigp_external_call = 2, 30 sigp_emergency_signal = 3, 31 sigp_start = 4, 32 sigp_stop = 5, 33 sigp_restart = 6, 34 sigp_stop_and_store_status = 9, 35 sigp_initial_cpu_reset = 11, 36 sigp_cpu_reset = 12, 37 sigp_set_prefix = 13, 38 sigp_store_status_at_address = 14, 39 sigp_store_extended_status_at_address = 15, 40 sigp_set_architecture = 18, 41 sigp_conditional_emergency_signal = 19, 42 sigp_sense_running = 21, 43 }; 44 45 enum { 46 sigp_order_code_accepted = 0, 47 sigp_status_stored = 1, 48 sigp_busy = 2, 49 sigp_not_operational = 3, 50 }; 51 52 /* 53 * Definitions for external call. 54 */ 55 enum { 56 ec_schedule = 0, 57 ec_call_function, 58 ec_call_function_single, 59 ec_stop_cpu, 60 }; 61 62 /* 63 * Signal processor. 64 */ 65 static inline int raw_sigp(u16 cpu, int order) 66 { 67 register unsigned long reg1 asm ("1") = 0; 68 int ccode; 69 70 asm volatile( 71 " sigp %1,%2,0(%3)\n" 72 " ipm %0\n" 73 " srl %0,28\n" 74 : "=d" (ccode) 75 : "d" (reg1), "d" (cpu), 76 "a" (order) : "cc" , "memory"); 77 return ccode; 78 } 79 80 /* 81 * Signal processor with parameter. 82 */ 83 static inline int raw_sigp_p(u32 parameter, u16 cpu, int order) 84 { 85 register unsigned int reg1 asm ("1") = parameter; 86 int ccode; 87 88 asm volatile( 89 " sigp %1,%2,0(%3)\n" 90 " ipm %0\n" 91 " srl %0,28\n" 92 : "=d" (ccode) 93 : "d" (reg1), "d" (cpu), 94 "a" (order) : "cc" , "memory"); 95 return ccode; 96 } 97 98 /* 99 * Signal processor with parameter and return status. 100 */ 101 static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order) 102 { 103 register unsigned int reg1 asm ("1") = parm; 104 int ccode; 105 106 asm volatile( 107 " sigp %1,%2,0(%3)\n" 108 " ipm %0\n" 109 " srl %0,28\n" 110 : "=d" (ccode), "+d" (reg1) 111 : "d" (cpu), "a" (order) 112 : "cc" , "memory"); 113 *status = reg1; 114 return ccode; 115 } 116 117 static inline int sigp(int cpu, int order) 118 { 119 return raw_sigp(cpu_logical_map(cpu), order); 120 } 121 122 static inline int sigp_p(u32 parameter, int cpu, int order) 123 { 124 return raw_sigp_p(parameter, cpu_logical_map(cpu), order); 125 } 126 127 static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order) 128 { 129 return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order); 130 } 131 132 #endif /* __ASM_SIGP_H */ 133