1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/bits.h> 16 17 #define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */ 18 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 19 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */ 20 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */ 21 22 #define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY) 23 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) 24 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) 25 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) 26 27 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U) 28 29 #ifndef __ASSEMBLY__ 30 31 #include <linux/cpumask.h> 32 #include <linux/linkage.h> 33 #include <linux/irqflags.h> 34 #include <asm/fpu-types.h> 35 #include <asm/cpu.h> 36 #include <asm/page.h> 37 #include <asm/ptrace.h> 38 #include <asm/setup.h> 39 #include <asm/runtime_instr.h> 40 #include <asm/irqflags.h> 41 42 typedef long (*sys_call_ptr_t)(struct pt_regs *regs); 43 44 static __always_inline void set_cpu_flag(int flag) 45 { 46 S390_lowcore.cpu_flags |= (1UL << flag); 47 } 48 49 static __always_inline void clear_cpu_flag(int flag) 50 { 51 S390_lowcore.cpu_flags &= ~(1UL << flag); 52 } 53 54 static __always_inline bool test_cpu_flag(int flag) 55 { 56 return S390_lowcore.cpu_flags & (1UL << flag); 57 } 58 59 static __always_inline bool test_and_set_cpu_flag(int flag) 60 { 61 if (test_cpu_flag(flag)) 62 return true; 63 set_cpu_flag(flag); 64 return false; 65 } 66 67 static __always_inline bool test_and_clear_cpu_flag(int flag) 68 { 69 if (!test_cpu_flag(flag)) 70 return false; 71 clear_cpu_flag(flag); 72 return true; 73 } 74 75 /* 76 * Test CIF flag of another CPU. The caller needs to ensure that 77 * CPU hotplug can not happen, e.g. by disabling preemption. 78 */ 79 static __always_inline bool test_cpu_flag_of(int flag, int cpu) 80 { 81 struct lowcore *lc = lowcore_ptr[cpu]; 82 83 return lc->cpu_flags & (1UL << flag); 84 } 85 86 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 87 88 static inline void get_cpu_id(struct cpuid *ptr) 89 { 90 asm volatile("stidp %0" : "=Q" (*ptr)); 91 } 92 93 void s390_adjust_jiffies(void); 94 void s390_update_cpu_mhz(void); 95 void cpu_detect_mhz_feature(void); 96 97 extern const struct seq_operations cpuinfo_op; 98 extern void execve_tail(void); 99 unsigned long vdso_size(void); 100 101 /* 102 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 103 */ 104 105 #define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \ 106 _REGION3_SIZE : TASK_SIZE_MAX) 107 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 108 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1)) 109 #define TASK_SIZE_MAX (-PAGE_SIZE) 110 111 #define VDSO_BASE (STACK_TOP + PAGE_SIZE) 112 #define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE) 113 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE) 114 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE) 115 116 #define HAVE_ARCH_PICK_MMAP_LAYOUT 117 118 #define __stackleak_poison __stackleak_poison 119 static __always_inline void __stackleak_poison(unsigned long erase_low, 120 unsigned long erase_high, 121 unsigned long poison) 122 { 123 unsigned long tmp, count; 124 125 count = erase_high - erase_low; 126 if (!count) 127 return; 128 asm volatile( 129 " cghi %[count],8\n" 130 " je 2f\n" 131 " aghi %[count],-(8+1)\n" 132 " srlg %[tmp],%[count],8\n" 133 " ltgr %[tmp],%[tmp]\n" 134 " jz 1f\n" 135 "0: stg %[poison],0(%[addr])\n" 136 " mvc 8(256-8,%[addr]),0(%[addr])\n" 137 " la %[addr],256(%[addr])\n" 138 " brctg %[tmp],0b\n" 139 "1: stg %[poison],0(%[addr])\n" 140 " larl %[tmp],3f\n" 141 " ex %[count],0(%[tmp])\n" 142 " j 4f\n" 143 "2: stg %[poison],0(%[addr])\n" 144 " j 4f\n" 145 "3: mvc 8(1,%[addr]),0(%[addr])\n" 146 "4:\n" 147 : [addr] "+&a" (erase_low), [count] "+&d" (count), [tmp] "=&a" (tmp) 148 : [poison] "d" (poison) 149 : "memory", "cc" 150 ); 151 } 152 153 /* 154 * Thread structure 155 */ 156 struct thread_struct { 157 unsigned int acrs[NUM_ACRS]; 158 unsigned long ksp; /* kernel stack pointer */ 159 unsigned long user_timer; /* task cputime in user space */ 160 unsigned long guest_timer; /* task cputime in kvm guest */ 161 unsigned long system_timer; /* task cputime in kernel space */ 162 unsigned long hardirq_timer; /* task cputime in hardirq context */ 163 unsigned long softirq_timer; /* task cputime in softirq context */ 164 const sys_call_ptr_t *sys_call_table; /* system call table address */ 165 unsigned long gmap_addr; /* address of last gmap fault. */ 166 unsigned int gmap_write_flag; /* gmap fault write indication */ 167 unsigned int gmap_int_code; /* int code of last gmap fault */ 168 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 169 int ufpu_flags; /* user fpu flags */ 170 int kfpu_flags; /* kernel fpu flags */ 171 172 /* Per-thread information related to debugging */ 173 struct per_regs per_user; /* User specified PER registers */ 174 struct per_event per_event; /* Cause of the last PER trap */ 175 unsigned long per_flags; /* Flags to control debug behavior */ 176 unsigned int system_call; /* system call number in signal */ 177 unsigned long last_break; /* last breaking-event-address. */ 178 /* pfault_wait is used to block the process on a pfault event */ 179 unsigned long pfault_wait; 180 struct list_head list; 181 /* cpu runtime instrumentation */ 182 struct runtime_instr_cb *ri_cb; 183 struct gs_cb *gs_cb; /* Current guarded storage cb */ 184 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 185 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */ 186 struct fpu ufpu; /* User FP and VX register save area */ 187 struct fpu kfpu; /* Kernel FP and VX register save area */ 188 }; 189 190 /* Flag to disable transactions. */ 191 #define PER_FLAG_NO_TE 1UL 192 /* Flag to enable random transaction aborts. */ 193 #define PER_FLAG_TE_ABORT_RAND 2UL 194 /* Flag to specify random transaction abort mode: 195 * - abort each transaction at a random instruction before TEND if set. 196 * - abort random transactions at a random instruction if cleared. 197 */ 198 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 199 200 typedef struct thread_struct thread_struct; 201 202 #define ARCH_MIN_TASKALIGN 8 203 204 #define INIT_THREAD { \ 205 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 206 .last_break = 1, \ 207 } 208 209 /* 210 * Do necessary setup to start up a new thread. 211 */ 212 #define start_thread(regs, new_psw, new_stackp) do { \ 213 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 214 regs->psw.addr = new_psw; \ 215 regs->gprs[15] = new_stackp; \ 216 execve_tail(); \ 217 } while (0) 218 219 #define start_thread31(regs, new_psw, new_stackp) do { \ 220 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 221 regs->psw.addr = new_psw; \ 222 regs->gprs[15] = new_stackp; \ 223 execve_tail(); \ 224 } while (0) 225 226 struct task_struct; 227 struct mm_struct; 228 struct seq_file; 229 struct pt_regs; 230 231 void show_registers(struct pt_regs *regs); 232 void show_cacheinfo(struct seq_file *m); 233 234 /* Free guarded storage control block */ 235 void guarded_storage_release(struct task_struct *tsk); 236 void gs_load_bc_cb(struct pt_regs *regs); 237 238 unsigned long __get_wchan(struct task_struct *p); 239 #define task_pt_regs(tsk) ((struct pt_regs *) \ 240 (task_stack_page(tsk) + THREAD_SIZE) - 1) 241 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 242 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 243 244 /* Has task runtime instrumentation enabled ? */ 245 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 246 247 /* avoid using global register due to gcc bug in versions < 8.4 */ 248 #define current_stack_pointer (__current_stack_pointer()) 249 250 static __always_inline unsigned long __current_stack_pointer(void) 251 { 252 unsigned long sp; 253 254 asm volatile("lgr %0,15" : "=d" (sp)); 255 return sp; 256 } 257 258 static __always_inline bool on_thread_stack(void) 259 { 260 unsigned long ksp = S390_lowcore.kernel_stack; 261 262 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1)); 263 } 264 265 static __always_inline unsigned short stap(void) 266 { 267 unsigned short cpu_address; 268 269 asm volatile("stap %0" : "=Q" (cpu_address)); 270 return cpu_address; 271 } 272 273 #define cpu_relax() barrier() 274 275 #define ECAG_CACHE_ATTRIBUTE 0 276 #define ECAG_CPU_ATTRIBUTE 1 277 278 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 279 { 280 unsigned long val; 281 282 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm)); 283 return val; 284 } 285 286 static inline void psw_set_key(unsigned int key) 287 { 288 asm volatile("spka 0(%0)" : : "d" (key)); 289 } 290 291 /* 292 * Set PSW to specified value. 293 */ 294 static inline void __load_psw(psw_t psw) 295 { 296 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 297 } 298 299 /* 300 * Set PSW mask to specified value, while leaving the 301 * PSW addr pointing to the next instruction. 302 */ 303 static __always_inline void __load_psw_mask(unsigned long mask) 304 { 305 unsigned long addr; 306 psw_t psw; 307 308 psw.mask = mask; 309 310 asm volatile( 311 " larl %0,1f\n" 312 " stg %0,%1\n" 313 " lpswe %2\n" 314 "1:" 315 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc"); 316 } 317 318 /* 319 * Extract current PSW mask 320 */ 321 static inline unsigned long __extract_psw(void) 322 { 323 unsigned int reg1, reg2; 324 325 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 326 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 327 } 328 329 static inline unsigned long __local_mcck_save(void) 330 { 331 unsigned long mask = __extract_psw(); 332 333 __load_psw_mask(mask & ~PSW_MASK_MCHECK); 334 return mask & PSW_MASK_MCHECK; 335 } 336 337 #define local_mcck_save(mflags) \ 338 do { \ 339 typecheck(unsigned long, mflags); \ 340 mflags = __local_mcck_save(); \ 341 } while (0) 342 343 static inline void local_mcck_restore(unsigned long mflags) 344 { 345 unsigned long mask = __extract_psw(); 346 347 mask &= ~PSW_MASK_MCHECK; 348 __load_psw_mask(mask | mflags); 349 } 350 351 static inline void local_mcck_disable(void) 352 { 353 __local_mcck_save(); 354 } 355 356 static inline void local_mcck_enable(void) 357 { 358 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 359 } 360 361 /* 362 * Rewind PSW instruction address by specified number of bytes. 363 */ 364 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 365 { 366 unsigned long mask; 367 368 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 369 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 370 (1UL << 24) - 1; 371 return (psw.addr - ilc) & mask; 372 } 373 374 /* 375 * Function to drop a processor into disabled wait state 376 */ 377 static __always_inline void __noreturn disabled_wait(void) 378 { 379 psw_t psw; 380 381 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 382 psw.addr = _THIS_IP_; 383 __load_psw(psw); 384 while (1); 385 } 386 387 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 388 389 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs) 390 { 391 return arch_irqs_disabled_flags(regs->psw.mask); 392 } 393 394 #endif /* __ASSEMBLY__ */ 395 396 #endif /* __ASM_S390_PROCESSOR_H */ 397