1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/const.h> 16 17 #define CIF_MCCK_PENDING 0 /* machine check handling is pending */ 18 #define CIF_ASCE_PRIMARY 1 /* primary asce needs fixup / uaccess */ 19 #define CIF_ASCE_SECONDARY 2 /* secondary asce needs fixup / uaccess */ 20 #define CIF_NOHZ_DELAY 3 /* delay HZ disable for a tick */ 21 #define CIF_FPU 4 /* restore FPU registers */ 22 #define CIF_IGNORE_IRQ 5 /* ignore interrupt (for udelay) */ 23 #define CIF_ENABLED_WAIT 6 /* in enabled wait state */ 24 #define CIF_MCCK_GUEST 7 /* machine check happening in guest */ 25 #define CIF_DEDICATED_CPU 8 /* this CPU is dedicated */ 26 27 #define _CIF_MCCK_PENDING _BITUL(CIF_MCCK_PENDING) 28 #define _CIF_ASCE_PRIMARY _BITUL(CIF_ASCE_PRIMARY) 29 #define _CIF_ASCE_SECONDARY _BITUL(CIF_ASCE_SECONDARY) 30 #define _CIF_NOHZ_DELAY _BITUL(CIF_NOHZ_DELAY) 31 #define _CIF_FPU _BITUL(CIF_FPU) 32 #define _CIF_IGNORE_IRQ _BITUL(CIF_IGNORE_IRQ) 33 #define _CIF_ENABLED_WAIT _BITUL(CIF_ENABLED_WAIT) 34 #define _CIF_MCCK_GUEST _BITUL(CIF_MCCK_GUEST) 35 #define _CIF_DEDICATED_CPU _BITUL(CIF_DEDICATED_CPU) 36 37 #ifndef __ASSEMBLY__ 38 39 #include <linux/linkage.h> 40 #include <linux/irqflags.h> 41 #include <asm/cpu.h> 42 #include <asm/page.h> 43 #include <asm/ptrace.h> 44 #include <asm/setup.h> 45 #include <asm/runtime_instr.h> 46 #include <asm/fpu/types.h> 47 #include <asm/fpu/internal.h> 48 49 static inline void set_cpu_flag(int flag) 50 { 51 S390_lowcore.cpu_flags |= (1UL << flag); 52 } 53 54 static inline void clear_cpu_flag(int flag) 55 { 56 S390_lowcore.cpu_flags &= ~(1UL << flag); 57 } 58 59 static inline int test_cpu_flag(int flag) 60 { 61 return !!(S390_lowcore.cpu_flags & (1UL << flag)); 62 } 63 64 /* 65 * Test CIF flag of another CPU. The caller needs to ensure that 66 * CPU hotplug can not happen, e.g. by disabling preemption. 67 */ 68 static inline int test_cpu_flag_of(int flag, int cpu) 69 { 70 struct lowcore *lc = lowcore_ptr[cpu]; 71 return !!(lc->cpu_flags & (1UL << flag)); 72 } 73 74 #define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY) 75 76 /* 77 * Default implementation of macro that returns current 78 * instruction pointer ("program counter"). 79 */ 80 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 81 82 static inline void get_cpu_id(struct cpuid *ptr) 83 { 84 asm volatile("stidp %0" : "=Q" (*ptr)); 85 } 86 87 void s390_adjust_jiffies(void); 88 void s390_update_cpu_mhz(void); 89 void cpu_detect_mhz_feature(void); 90 91 extern const struct seq_operations cpuinfo_op; 92 extern int sysctl_ieee_emulation_warnings; 93 extern void execve_tail(void); 94 extern void __bpon(void); 95 96 /* 97 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 98 */ 99 100 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_31BIT) ? \ 101 (1UL << 31) : -PAGE_SIZE) 102 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 103 (1UL << 30) : (1UL << 41)) 104 #define TASK_SIZE TASK_SIZE_OF(current) 105 #define TASK_SIZE_MAX (-PAGE_SIZE) 106 107 #define STACK_TOP (test_thread_flag(TIF_31BIT) ? \ 108 (1UL << 31) : (1UL << 42)) 109 #define STACK_TOP_MAX (1UL << 42) 110 111 #define HAVE_ARCH_PICK_MMAP_LAYOUT 112 113 typedef unsigned int mm_segment_t; 114 115 /* 116 * Thread structure 117 */ 118 struct thread_struct { 119 unsigned int acrs[NUM_ACRS]; 120 unsigned long ksp; /* kernel stack pointer */ 121 unsigned long user_timer; /* task cputime in user space */ 122 unsigned long guest_timer; /* task cputime in kvm guest */ 123 unsigned long system_timer; /* task cputime in kernel space */ 124 unsigned long hardirq_timer; /* task cputime in hardirq context */ 125 unsigned long softirq_timer; /* task cputime in softirq context */ 126 unsigned long sys_call_table; /* system call table address */ 127 mm_segment_t mm_segment; 128 unsigned long gmap_addr; /* address of last gmap fault. */ 129 unsigned int gmap_write_flag; /* gmap fault write indication */ 130 unsigned int gmap_int_code; /* int code of last gmap fault */ 131 unsigned int gmap_pfault; /* signal of a pending guest pfault */ 132 /* Per-thread information related to debugging */ 133 struct per_regs per_user; /* User specified PER registers */ 134 struct per_event per_event; /* Cause of the last PER trap */ 135 unsigned long per_flags; /* Flags to control debug behavior */ 136 unsigned int system_call; /* system call number in signal */ 137 unsigned long last_break; /* last breaking-event-address. */ 138 /* pfault_wait is used to block the process on a pfault event */ 139 unsigned long pfault_wait; 140 struct list_head list; 141 /* cpu runtime instrumentation */ 142 struct runtime_instr_cb *ri_cb; 143 struct gs_cb *gs_cb; /* Current guarded storage cb */ 144 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 145 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 146 /* 147 * Warning: 'fpu' is dynamically-sized. It *MUST* be at 148 * the end. 149 */ 150 struct fpu fpu; /* FP and VX register save area */ 151 }; 152 153 /* Flag to disable transactions. */ 154 #define PER_FLAG_NO_TE 1UL 155 /* Flag to enable random transaction aborts. */ 156 #define PER_FLAG_TE_ABORT_RAND 2UL 157 /* Flag to specify random transaction abort mode: 158 * - abort each transaction at a random instruction before TEND if set. 159 * - abort random transactions at a random instruction if cleared. 160 */ 161 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 162 163 typedef struct thread_struct thread_struct; 164 165 /* 166 * Stack layout of a C stack frame. 167 */ 168 #ifndef __PACK_STACK 169 struct stack_frame { 170 unsigned long back_chain; 171 unsigned long empty1[5]; 172 unsigned long gprs[10]; 173 unsigned int empty2[8]; 174 }; 175 #else 176 struct stack_frame { 177 unsigned long empty1[5]; 178 unsigned int empty2[8]; 179 unsigned long gprs[10]; 180 unsigned long back_chain; 181 }; 182 #endif 183 184 #define ARCH_MIN_TASKALIGN 8 185 186 #define INIT_THREAD { \ 187 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 188 .fpu.regs = (void *) init_task.thread.fpu.fprs, \ 189 } 190 191 /* 192 * Do necessary setup to start up a new thread. 193 */ 194 #define start_thread(regs, new_psw, new_stackp) do { \ 195 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 196 regs->psw.addr = new_psw; \ 197 regs->gprs[15] = new_stackp; \ 198 execve_tail(); \ 199 } while (0) 200 201 #define start_thread31(regs, new_psw, new_stackp) do { \ 202 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 203 regs->psw.addr = new_psw; \ 204 regs->gprs[15] = new_stackp; \ 205 crst_table_downgrade(current->mm); \ 206 execve_tail(); \ 207 } while (0) 208 209 /* Forward declaration, a strange C thing */ 210 struct task_struct; 211 struct mm_struct; 212 struct seq_file; 213 struct pt_regs; 214 215 typedef int (*dump_trace_func_t)(void *data, unsigned long address, int reliable); 216 void dump_trace(dump_trace_func_t func, void *data, 217 struct task_struct *task, unsigned long sp); 218 void show_registers(struct pt_regs *regs); 219 220 void show_cacheinfo(struct seq_file *m); 221 222 /* Free all resources held by a thread. */ 223 static inline void release_thread(struct task_struct *tsk) { } 224 225 /* Free guarded storage control block */ 226 void guarded_storage_release(struct task_struct *tsk); 227 228 unsigned long get_wchan(struct task_struct *p); 229 #define task_pt_regs(tsk) ((struct pt_regs *) \ 230 (task_stack_page(tsk) + THREAD_SIZE) - 1) 231 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 232 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 233 234 /* Has task runtime instrumentation enabled ? */ 235 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 236 237 static inline unsigned long current_stack_pointer(void) 238 { 239 unsigned long sp; 240 241 asm volatile("la %0,0(15)" : "=a" (sp)); 242 return sp; 243 } 244 245 static __no_sanitize_address_or_inline unsigned short stap(void) 246 { 247 unsigned short cpu_address; 248 249 asm volatile("stap %0" : "=Q" (cpu_address)); 250 return cpu_address; 251 } 252 253 #define CALL_ARGS_0() \ 254 register unsigned long r2 asm("2") 255 #define CALL_ARGS_1(arg1) \ 256 register unsigned long r2 asm("2") = (unsigned long)(arg1) 257 #define CALL_ARGS_2(arg1, arg2) \ 258 CALL_ARGS_1(arg1); \ 259 register unsigned long r3 asm("3") = (unsigned long)(arg2) 260 #define CALL_ARGS_3(arg1, arg2, arg3) \ 261 CALL_ARGS_2(arg1, arg2); \ 262 register unsigned long r4 asm("4") = (unsigned long)(arg3) 263 #define CALL_ARGS_4(arg1, arg2, arg3, arg4) \ 264 CALL_ARGS_3(arg1, arg2, arg3); \ 265 register unsigned long r4 asm("5") = (unsigned long)(arg4) 266 #define CALL_ARGS_5(arg1, arg2, arg3, arg4, arg5) \ 267 CALL_ARGS_4(arg1, arg2, arg3, arg4); \ 268 register unsigned long r4 asm("6") = (unsigned long)(arg5) 269 270 #define CALL_FMT_0 271 #define CALL_FMT_1 CALL_FMT_0, "0" (r2) 272 #define CALL_FMT_2 CALL_FMT_1, "d" (r3) 273 #define CALL_FMT_3 CALL_FMT_2, "d" (r4) 274 #define CALL_FMT_4 CALL_FMT_3, "d" (r5) 275 #define CALL_FMT_5 CALL_FMT_4, "d" (r6) 276 277 #define CALL_CLOBBER_5 "0", "1", "14", "cc", "memory" 278 #define CALL_CLOBBER_4 CALL_CLOBBER_5 279 #define CALL_CLOBBER_3 CALL_CLOBBER_4, "5" 280 #define CALL_CLOBBER_2 CALL_CLOBBER_3, "4" 281 #define CALL_CLOBBER_1 CALL_CLOBBER_2, "3" 282 #define CALL_CLOBBER_0 CALL_CLOBBER_1 283 284 #define CALL_ON_STACK(fn, stack, nr, args...) \ 285 ({ \ 286 CALL_ARGS_##nr(args); \ 287 unsigned long prev; \ 288 \ 289 asm volatile( \ 290 " la %[_prev],0(15)\n" \ 291 " la 15,0(%[_stack])\n" \ 292 " stg %[_prev],%[_bc](15)\n" \ 293 " brasl 14,%[_fn]\n" \ 294 " la 15,0(%[_prev])\n" \ 295 : "+&d" (r2), [_prev] "=&a" (prev) \ 296 : [_stack] "a" (stack), \ 297 [_bc] "i" (offsetof(struct stack_frame, back_chain)), \ 298 [_fn] "X" (fn) CALL_FMT_##nr : CALL_CLOBBER_##nr); \ 299 r2; \ 300 }) 301 302 /* 303 * Give up the time slice of the virtual PU. 304 */ 305 #define cpu_relax_yield cpu_relax_yield 306 void cpu_relax_yield(void); 307 308 #define cpu_relax() barrier() 309 310 #define ECAG_CACHE_ATTRIBUTE 0 311 #define ECAG_CPU_ATTRIBUTE 1 312 313 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 314 { 315 unsigned long val; 316 317 asm volatile(".insn rsy,0xeb000000004c,%0,0,0(%1)" /* ecag */ 318 : "=d" (val) : "a" (asi << 8 | parm)); 319 return val; 320 } 321 322 static inline void psw_set_key(unsigned int key) 323 { 324 asm volatile("spka 0(%0)" : : "d" (key)); 325 } 326 327 /* 328 * Set PSW to specified value. 329 */ 330 static inline void __load_psw(psw_t psw) 331 { 332 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 333 } 334 335 /* 336 * Set PSW mask to specified value, while leaving the 337 * PSW addr pointing to the next instruction. 338 */ 339 static __no_sanitize_address_or_inline void __load_psw_mask(unsigned long mask) 340 { 341 unsigned long addr; 342 psw_t psw; 343 344 psw.mask = mask; 345 346 asm volatile( 347 " larl %0,1f\n" 348 " stg %0,%O1+8(%R1)\n" 349 " lpswe %1\n" 350 "1:" 351 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 352 } 353 354 /* 355 * Extract current PSW mask 356 */ 357 static inline unsigned long __extract_psw(void) 358 { 359 unsigned int reg1, reg2; 360 361 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 362 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 363 } 364 365 static inline void local_mcck_enable(void) 366 { 367 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 368 } 369 370 static inline void local_mcck_disable(void) 371 { 372 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK); 373 } 374 375 /* 376 * Rewind PSW instruction address by specified number of bytes. 377 */ 378 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 379 { 380 unsigned long mask; 381 382 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 383 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 384 (1UL << 24) - 1; 385 return (psw.addr - ilc) & mask; 386 } 387 388 /* 389 * Function to stop a processor until the next interrupt occurs 390 */ 391 void enabled_wait(void); 392 393 /* 394 * Function to drop a processor into disabled wait state 395 */ 396 static inline void __noreturn disabled_wait(unsigned long code) 397 { 398 psw_t psw; 399 400 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 401 psw.addr = code; 402 __load_psw(psw); 403 while (1); 404 } 405 406 /* 407 * Basic Machine Check/Program Check Handler. 408 */ 409 410 extern void s390_base_mcck_handler(void); 411 extern void s390_base_pgm_handler(void); 412 extern void s390_base_ext_handler(void); 413 414 extern void (*s390_base_mcck_handler_fn)(void); 415 extern void (*s390_base_pgm_handler_fn)(void); 416 extern void (*s390_base_ext_handler_fn)(void); 417 418 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 419 420 extern int memcpy_real(void *, void *, size_t); 421 extern void memcpy_absolute(void *, void *, size_t); 422 423 #define mem_assign_absolute(dest, val) do { \ 424 __typeof__(dest) __tmp = (val); \ 425 \ 426 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 427 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 428 } while (0) 429 430 extern int s390_isolate_bp(void); 431 extern int s390_isolate_bp_guest(void); 432 433 #endif /* __ASSEMBLY__ */ 434 435 #endif /* __ASM_S390_PROCESSOR_H */ 436