1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999 4 * Author(s): Hartmut Penner (hp@de.ibm.com), 5 * Martin Schwidefsky (schwidefsky@de.ibm.com) 6 * 7 * Derived from "include/asm-i386/processor.h" 8 * Copyright (C) 1994, Linus Torvalds 9 */ 10 11 #ifndef __ASM_S390_PROCESSOR_H 12 #define __ASM_S390_PROCESSOR_H 13 14 #ifndef __ASSEMBLY__ 15 16 #include <linux/linkage.h> 17 #include <linux/irqflags.h> 18 #include <asm/cpu.h> 19 #include <asm/page.h> 20 #include <asm/ptrace.h> 21 #include <asm/setup.h> 22 #include <asm/runtime_instr.h> 23 24 /* 25 * Default implementation of macro that returns current 26 * instruction pointer ("program counter"). 27 */ 28 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 29 30 static inline void get_cpu_id(struct cpuid *ptr) 31 { 32 asm volatile("stidp %0" : "=Q" (*ptr)); 33 } 34 35 extern void s390_adjust_jiffies(void); 36 extern const struct seq_operations cpuinfo_op; 37 extern int sysctl_ieee_emulation_warnings; 38 extern void execve_tail(void); 39 40 /* 41 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 42 */ 43 #ifndef CONFIG_64BIT 44 45 #define TASK_SIZE (1UL << 31) 46 #define TASK_MAX_SIZE (1UL << 31) 47 #define TASK_UNMAPPED_BASE (1UL << 30) 48 49 #else /* CONFIG_64BIT */ 50 51 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) 52 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 53 (1UL << 30) : (1UL << 41)) 54 #define TASK_SIZE TASK_SIZE_OF(current) 55 #define TASK_MAX_SIZE (1UL << 53) 56 57 #endif /* CONFIG_64BIT */ 58 59 #ifndef CONFIG_64BIT 60 #define STACK_TOP (1UL << 31) 61 #define STACK_TOP_MAX (1UL << 31) 62 #else /* CONFIG_64BIT */ 63 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) 64 #define STACK_TOP_MAX (1UL << 42) 65 #endif /* CONFIG_64BIT */ 66 67 #define HAVE_ARCH_PICK_MMAP_LAYOUT 68 69 typedef struct { 70 __u32 ar4; 71 } mm_segment_t; 72 73 /* 74 * Thread structure 75 */ 76 struct thread_struct { 77 s390_fp_regs fp_regs; 78 unsigned int acrs[NUM_ACRS]; 79 unsigned long ksp; /* kernel stack pointer */ 80 mm_segment_t mm_segment; 81 unsigned long gmap_addr; /* address of last gmap fault. */ 82 struct per_regs per_user; /* User specified PER registers */ 83 struct per_event per_event; /* Cause of the last PER trap */ 84 unsigned long per_flags; /* Flags to control debug behavior */ 85 /* pfault_wait is used to block the process on a pfault event */ 86 unsigned long pfault_wait; 87 struct list_head list; 88 /* cpu runtime instrumentation */ 89 struct runtime_instr_cb *ri_cb; 90 int ri_signum; 91 #ifdef CONFIG_64BIT 92 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 93 #endif 94 }; 95 96 /* Flag to disable transactions. */ 97 #define PER_FLAG_NO_TE 1UL 98 /* Flag to enable random transaction aborts. */ 99 #define PER_FLAG_TE_ABORT_RAND 2UL 100 /* Flag to specify random transaction abort mode: 101 * - abort each transaction at a random instruction before TEND if set. 102 * - abort random transactions at a random instruction if cleared. 103 */ 104 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 105 106 typedef struct thread_struct thread_struct; 107 108 /* 109 * Stack layout of a C stack frame. 110 */ 111 #ifndef __PACK_STACK 112 struct stack_frame { 113 unsigned long back_chain; 114 unsigned long empty1[5]; 115 unsigned long gprs[10]; 116 unsigned int empty2[8]; 117 }; 118 #else 119 struct stack_frame { 120 unsigned long empty1[5]; 121 unsigned int empty2[8]; 122 unsigned long gprs[10]; 123 unsigned long back_chain; 124 }; 125 #endif 126 127 #define ARCH_MIN_TASKALIGN 8 128 129 #define INIT_THREAD { \ 130 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 131 } 132 133 /* 134 * Do necessary setup to start up a new thread. 135 */ 136 #define start_thread(regs, new_psw, new_stackp) do { \ 137 regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \ 138 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 139 regs->gprs[15] = new_stackp; \ 140 execve_tail(); \ 141 } while (0) 142 143 #define start_thread31(regs, new_psw, new_stackp) do { \ 144 regs->psw.mask = psw_user_bits | PSW_MASK_BA; \ 145 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 146 regs->gprs[15] = new_stackp; \ 147 __tlb_flush_mm(current->mm); \ 148 crst_table_downgrade(current->mm, 1UL << 31); \ 149 update_mm(current->mm, current); \ 150 execve_tail(); \ 151 } while (0) 152 153 /* Forward declaration, a strange C thing */ 154 struct task_struct; 155 struct mm_struct; 156 struct seq_file; 157 158 #ifdef CONFIG_64BIT 159 extern void show_cacheinfo(struct seq_file *m); 160 #else 161 static inline void show_cacheinfo(struct seq_file *m) { } 162 #endif 163 164 /* Free all resources held by a thread. */ 165 extern void release_thread(struct task_struct *); 166 167 /* 168 * Return saved PC of a blocked thread. 169 */ 170 extern unsigned long thread_saved_pc(struct task_struct *t); 171 172 extern void show_code(struct pt_regs *regs); 173 extern void print_fn_code(unsigned char *code, unsigned long len); 174 extern int insn_to_mnemonic(unsigned char *instruction, char *buf, 175 unsigned int len); 176 177 unsigned long get_wchan(struct task_struct *p); 178 #define task_pt_regs(tsk) ((struct pt_regs *) \ 179 (task_stack_page(tsk) + THREAD_SIZE) - 1) 180 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 181 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 182 183 static inline unsigned short stap(void) 184 { 185 unsigned short cpu_address; 186 187 asm volatile("stap %0" : "=m" (cpu_address)); 188 return cpu_address; 189 } 190 191 /* 192 * Give up the time slice of the virtual PU. 193 */ 194 static inline void cpu_relax(void) 195 { 196 if (MACHINE_HAS_DIAG44) 197 asm volatile("diag 0,0,68"); 198 barrier(); 199 } 200 201 static inline void psw_set_key(unsigned int key) 202 { 203 asm volatile("spka 0(%0)" : : "d" (key)); 204 } 205 206 /* 207 * Set PSW to specified value. 208 */ 209 static inline void __load_psw(psw_t psw) 210 { 211 #ifndef CONFIG_64BIT 212 asm volatile("lpsw %0" : : "Q" (psw) : "cc"); 213 #else 214 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 215 #endif 216 } 217 218 /* 219 * Set PSW mask to specified value, while leaving the 220 * PSW addr pointing to the next instruction. 221 */ 222 static inline void __load_psw_mask (unsigned long mask) 223 { 224 unsigned long addr; 225 psw_t psw; 226 227 psw.mask = mask; 228 229 #ifndef CONFIG_64BIT 230 asm volatile( 231 " basr %0,0\n" 232 "0: ahi %0,1f-0b\n" 233 " st %0,%O1+4(%R1)\n" 234 " lpsw %1\n" 235 "1:" 236 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 237 #else /* CONFIG_64BIT */ 238 asm volatile( 239 " larl %0,1f\n" 240 " stg %0,%O1+8(%R1)\n" 241 " lpswe %1\n" 242 "1:" 243 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 244 #endif /* CONFIG_64BIT */ 245 } 246 247 /* 248 * Rewind PSW instruction address by specified number of bytes. 249 */ 250 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 251 { 252 #ifndef CONFIG_64BIT 253 if (psw.addr & PSW_ADDR_AMODE) 254 /* 31 bit mode */ 255 return (psw.addr - ilc) | PSW_ADDR_AMODE; 256 /* 24 bit mode */ 257 return (psw.addr - ilc) & ((1UL << 24) - 1); 258 #else 259 unsigned long mask; 260 261 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 262 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 263 (1UL << 24) - 1; 264 return (psw.addr - ilc) & mask; 265 #endif 266 } 267 268 /* 269 * Function to drop a processor into disabled wait state 270 */ 271 static inline void __noreturn disabled_wait(unsigned long code) 272 { 273 unsigned long ctl_buf; 274 psw_t dw_psw; 275 276 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 277 dw_psw.addr = code; 278 /* 279 * Store status and then load disabled wait psw, 280 * the processor is dead afterwards 281 */ 282 #ifndef CONFIG_64BIT 283 asm volatile( 284 " stctl 0,0,0(%2)\n" 285 " ni 0(%2),0xef\n" /* switch off protection */ 286 " lctl 0,0,0(%2)\n" 287 " stpt 0xd8\n" /* store timer */ 288 " stckc 0xe0\n" /* store clock comparator */ 289 " stpx 0x108\n" /* store prefix register */ 290 " stam 0,15,0x120\n" /* store access registers */ 291 " std 0,0x160\n" /* store f0 */ 292 " std 2,0x168\n" /* store f2 */ 293 " std 4,0x170\n" /* store f4 */ 294 " std 6,0x178\n" /* store f6 */ 295 " stm 0,15,0x180\n" /* store general registers */ 296 " stctl 0,15,0x1c0\n" /* store control registers */ 297 " oi 0x1c0,0x10\n" /* fake protection bit */ 298 " lpsw 0(%1)" 299 : "=m" (ctl_buf) 300 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); 301 #else /* CONFIG_64BIT */ 302 asm volatile( 303 " stctg 0,0,0(%2)\n" 304 " ni 4(%2),0xef\n" /* switch off protection */ 305 " lctlg 0,0,0(%2)\n" 306 " lghi 1,0x1000\n" 307 " stpt 0x328(1)\n" /* store timer */ 308 " stckc 0x330(1)\n" /* store clock comparator */ 309 " stpx 0x318(1)\n" /* store prefix register */ 310 " stam 0,15,0x340(1)\n"/* store access registers */ 311 " stfpc 0x31c(1)\n" /* store fpu control */ 312 " std 0,0x200(1)\n" /* store f0 */ 313 " std 1,0x208(1)\n" /* store f1 */ 314 " std 2,0x210(1)\n" /* store f2 */ 315 " std 3,0x218(1)\n" /* store f3 */ 316 " std 4,0x220(1)\n" /* store f4 */ 317 " std 5,0x228(1)\n" /* store f5 */ 318 " std 6,0x230(1)\n" /* store f6 */ 319 " std 7,0x238(1)\n" /* store f7 */ 320 " std 8,0x240(1)\n" /* store f8 */ 321 " std 9,0x248(1)\n" /* store f9 */ 322 " std 10,0x250(1)\n" /* store f10 */ 323 " std 11,0x258(1)\n" /* store f11 */ 324 " std 12,0x260(1)\n" /* store f12 */ 325 " std 13,0x268(1)\n" /* store f13 */ 326 " std 14,0x270(1)\n" /* store f14 */ 327 " std 15,0x278(1)\n" /* store f15 */ 328 " stmg 0,15,0x280(1)\n"/* store general registers */ 329 " stctg 0,15,0x380(1)\n"/* store control registers */ 330 " oi 0x384(1),0x10\n"/* fake protection bit */ 331 " lpswe 0(%1)" 332 : "=m" (ctl_buf) 333 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); 334 #endif /* CONFIG_64BIT */ 335 while (1); 336 } 337 338 /* 339 * Use to set psw mask except for the first byte which 340 * won't be changed by this function. 341 */ 342 static inline void 343 __set_psw_mask(unsigned long mask) 344 { 345 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); 346 } 347 348 #define local_mcck_enable() \ 349 __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK) 350 #define local_mcck_disable() \ 351 __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT) 352 353 /* 354 * Basic Machine Check/Program Check Handler. 355 */ 356 357 extern void s390_base_mcck_handler(void); 358 extern void s390_base_pgm_handler(void); 359 extern void s390_base_ext_handler(void); 360 361 extern void (*s390_base_mcck_handler_fn)(void); 362 extern void (*s390_base_pgm_handler_fn)(void); 363 extern void (*s390_base_ext_handler_fn)(void); 364 365 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 366 367 extern int memcpy_real(void *, void *, size_t); 368 extern void memcpy_absolute(void *, void *, size_t); 369 370 #define mem_assign_absolute(dest, val) { \ 371 __typeof__(dest) __tmp = (val); \ 372 \ 373 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 374 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 375 } 376 377 /* 378 * Helper macro for exception table entries 379 */ 380 #define EX_TABLE(_fault, _target) \ 381 ".section __ex_table,\"a\"\n" \ 382 ".align 4\n" \ 383 ".long (" #_fault ") - .\n" \ 384 ".long (" #_target ") - .\n" \ 385 ".previous\n" 386 387 #else /* __ASSEMBLY__ */ 388 389 #define EX_TABLE(_fault, _target) \ 390 .section __ex_table,"a" ; \ 391 .align 4 ; \ 392 .long (_fault) - . ; \ 393 .long (_target) - . ; \ 394 .previous 395 396 #endif /* __ASSEMBLY__ */ 397 398 #endif /* __ASM_S390_PROCESSOR_H */ 399