1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999 5 * Author(s): Hartmut Penner (hp@de.ibm.com), 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/processor.h" 9 * Copyright (C) 1994, Linus Torvalds 10 */ 11 12 #ifndef __ASM_S390_PROCESSOR_H 13 #define __ASM_S390_PROCESSOR_H 14 15 #include <linux/bits.h> 16 17 #define CIF_ENABLED_WAIT 5 /* in enabled wait state */ 18 #define CIF_MCCK_GUEST 6 /* machine check happening in guest */ 19 #define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */ 20 21 #define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT) 22 #define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST) 23 #define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU) 24 25 #define RESTART_FLAG_CTLREGS _AC(1 << 0, U) 26 27 #ifndef __ASSEMBLER__ 28 29 #include <linux/cpumask.h> 30 #include <linux/linkage.h> 31 #include <linux/irqflags.h> 32 #include <linux/instruction_pointer.h> 33 #include <linux/bitops.h> 34 #include <asm/vdso/processor.h> 35 #include <asm/fpu-types.h> 36 #include <asm/cpu.h> 37 #include <asm/page.h> 38 #include <asm/ptrace.h> 39 #include <asm/setup.h> 40 #include <asm/runtime_instr.h> 41 #include <asm/irqflags.h> 42 #include <asm/alternative.h> 43 #include <asm/fault.h> 44 45 struct pcpu { 46 unsigned long ec_mask; /* bit mask for ec_xxx functions */ 47 unsigned long ec_clk; /* sigp timestamp for ec_xxx */ 48 unsigned long flags; /* per CPU flags */ 49 unsigned long capacity; /* cpu capacity for scheduler */ 50 signed char state; /* physical cpu state */ 51 signed char polarization; /* physical polarization */ 52 u16 address; /* physical cpu address */ 53 }; 54 55 DECLARE_PER_CPU(struct pcpu, pcpu_devices); 56 57 typedef long (*sys_call_ptr_t)(struct pt_regs *regs); 58 59 static __always_inline struct pcpu *this_pcpu(void) 60 { 61 return (struct pcpu *)(get_lowcore()->pcpu); 62 } 63 64 static __always_inline void set_cpu_flag(int flag) 65 { 66 set_bit(flag, &this_pcpu()->flags); 67 } 68 69 static __always_inline void clear_cpu_flag(int flag) 70 { 71 clear_bit(flag, &this_pcpu()->flags); 72 } 73 74 static __always_inline bool test_cpu_flag(int flag) 75 { 76 return test_bit(flag, &this_pcpu()->flags); 77 } 78 79 static __always_inline bool test_and_set_cpu_flag(int flag) 80 { 81 return test_and_set_bit(flag, &this_pcpu()->flags); 82 } 83 84 static __always_inline bool test_and_clear_cpu_flag(int flag) 85 { 86 return test_and_clear_bit(flag, &this_pcpu()->flags); 87 } 88 89 /* 90 * Test CIF flag of another CPU. The caller needs to ensure that 91 * CPU hotplug can not happen, e.g. by disabling preemption. 92 */ 93 static __always_inline bool test_cpu_flag_of(int flag, int cpu) 94 { 95 return test_bit(flag, &per_cpu(pcpu_devices, cpu).flags); 96 } 97 98 static inline void get_cpu_id(struct cpuid *ptr) 99 { 100 asm volatile("stidp %0" : "=Q" (*ptr)); 101 } 102 103 static __always_inline unsigned long get_cpu_timer(void) 104 { 105 unsigned long timer; 106 107 asm volatile("stpt %[timer]" : [timer] "=Q" (timer)); 108 return timer; 109 } 110 111 void s390_adjust_jiffies(void); 112 void s390_update_cpu_mhz(void); 113 void cpu_detect_mhz_feature(void); 114 115 extern const struct seq_operations cpuinfo_op; 116 extern void execve_tail(void); 117 unsigned long vdso_text_size(void); 118 unsigned long vdso_size(void); 119 120 #define TASK_SIZE (TASK_SIZE_MAX) 121 #define TASK_UNMAPPED_BASE (_REGION2_SIZE >> 1) 122 #define TASK_SIZE_MAX (-PAGE_SIZE) 123 124 #define VDSO_BASE (STACK_TOP + PAGE_SIZE) 125 #define VDSO_LIMIT (_REGION2_SIZE) 126 #define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE) 127 #define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE) 128 129 #define HAVE_ARCH_PICK_MMAP_LAYOUT 130 131 #define __stackleak_poison __stackleak_poison 132 static __always_inline void __stackleak_poison(unsigned long erase_low, 133 unsigned long erase_high, 134 unsigned long poison) 135 { 136 unsigned long tmp, count; 137 138 count = erase_high - erase_low; 139 if (!count) 140 return; 141 asm volatile( 142 " cghi %[count],8\n" 143 " je 2f\n" 144 " aghi %[count],-(8+1)\n" 145 " srlg %[tmp],%[count],8\n" 146 " ltgr %[tmp],%[tmp]\n" 147 " jz 1f\n" 148 "0: stg %[poison],0(%[addr])\n" 149 " mvc 8(256-8,%[addr]),0(%[addr])\n" 150 " la %[addr],256(%[addr])\n" 151 " brctg %[tmp],0b\n" 152 "1: stg %[poison],0(%[addr])\n" 153 " exrl %[count],3f\n" 154 " j 4f\n" 155 "2: stg %[poison],0(%[addr])\n" 156 " j 4f\n" 157 "3: mvc 8(1,%[addr]),0(%[addr])\n" 158 "4:" 159 : [addr] "+&a" (erase_low), [count] "+&a" (count), [tmp] "=&a" (tmp) 160 : [poison] "d" (poison) 161 : "memory", "cc" 162 ); 163 } 164 165 /* 166 * Thread structure 167 */ 168 struct thread_struct { 169 unsigned int acrs[NUM_ACRS]; 170 unsigned long ksp; /* kernel stack pointer */ 171 unsigned long user_timer; /* task cputime in user space */ 172 unsigned long guest_timer; /* task cputime in kvm guest */ 173 unsigned long system_timer; /* task cputime in kernel space */ 174 unsigned long hardirq_timer; /* task cputime in hardirq context */ 175 unsigned long softirq_timer; /* task cputime in softirq context */ 176 union teid gmap_teid; /* address and flags of last gmap fault */ 177 unsigned int gmap_int_code; /* int code of last gmap fault */ 178 int ufpu_flags; /* user fpu flags */ 179 int kfpu_flags; /* kernel fpu flags */ 180 181 /* Per-thread information related to debugging */ 182 struct per_regs per_user; /* User specified PER registers */ 183 struct per_event per_event; /* Cause of the last PER trap */ 184 unsigned long per_flags; /* Flags to control debug behavior */ 185 unsigned int system_call; /* system call number in signal */ 186 unsigned long last_break; /* last breaking-event-address. */ 187 /* pfault_wait is used to block the process on a pfault event */ 188 unsigned long pfault_wait; 189 struct list_head list; 190 /* cpu runtime instrumentation */ 191 struct runtime_instr_cb *ri_cb; 192 struct gs_cb *gs_cb; /* Current guarded storage cb */ 193 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */ 194 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */ 195 struct fpu ufpu; /* User FP and VX register save area */ 196 struct fpu kfpu; /* Kernel FP and VX register save area */ 197 }; 198 199 /* Flag to disable transactions. */ 200 #define PER_FLAG_NO_TE 1UL 201 /* Flag to enable random transaction aborts. */ 202 #define PER_FLAG_TE_ABORT_RAND 2UL 203 /* Flag to specify random transaction abort mode: 204 * - abort each transaction at a random instruction before TEND if set. 205 * - abort random transactions at a random instruction if cleared. 206 */ 207 #define PER_FLAG_TE_ABORT_RAND_TEND 4UL 208 209 typedef struct thread_struct thread_struct; 210 211 #define ARCH_MIN_TASKALIGN 8 212 213 #define INIT_THREAD { \ 214 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 215 .last_break = 1, \ 216 } 217 218 /* 219 * Do necessary setup to start up a new thread. 220 */ 221 #define start_thread(regs, new_psw, new_stackp) do { \ 222 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ 223 regs->psw.addr = new_psw; \ 224 regs->gprs[15] = new_stackp; \ 225 execve_tail(); \ 226 } while (0) 227 228 #define start_thread31(regs, new_psw, new_stackp) do { \ 229 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ 230 regs->psw.addr = new_psw; \ 231 regs->gprs[15] = new_stackp; \ 232 execve_tail(); \ 233 } while (0) 234 235 struct task_struct; 236 struct mm_struct; 237 struct seq_file; 238 struct pt_regs; 239 240 void show_registers(struct pt_regs *regs); 241 void show_cacheinfo(struct seq_file *m); 242 243 /* Free guarded storage control block */ 244 void guarded_storage_release(struct task_struct *tsk); 245 void gs_load_bc_cb(struct pt_regs *regs); 246 247 unsigned long __get_wchan(struct task_struct *p); 248 #define task_pt_regs(tsk) ((struct pt_regs *) \ 249 (task_stack_page(tsk) + THREAD_SIZE) - 1) 250 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 251 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 252 253 /* Has task runtime instrumentation enabled ? */ 254 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb) 255 256 /* avoid using global register due to gcc bug in versions < 8.4 */ 257 #define current_stack_pointer (__current_stack_pointer()) 258 259 static __always_inline unsigned long __current_stack_pointer(void) 260 { 261 unsigned long sp; 262 263 asm volatile("lgr %0,15" : "=d" (sp)); 264 return sp; 265 } 266 267 static __always_inline bool on_thread_stack(void) 268 { 269 unsigned long ksp = get_lowcore()->kernel_stack; 270 271 return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1)); 272 } 273 274 static __always_inline unsigned short stap(void) 275 { 276 unsigned short cpu_address; 277 278 asm volatile("stap %0" : "=Q" (cpu_address)); 279 return cpu_address; 280 } 281 282 #define ECAG_CACHE_ATTRIBUTE 0 283 #define ECAG_CPU_ATTRIBUTE 1 284 285 static inline unsigned long __ecag(unsigned int asi, unsigned char parm) 286 { 287 unsigned long val; 288 289 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm)); 290 return val; 291 } 292 293 static inline void psw_set_key(unsigned int key) 294 { 295 asm volatile("spka 0(%0)" : : "d" (key)); 296 } 297 298 /* 299 * Set PSW to specified value. 300 */ 301 static inline void __load_psw(psw_t psw) 302 { 303 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 304 } 305 306 /* 307 * Set PSW mask to specified value, while leaving the 308 * PSW addr pointing to the next instruction. 309 */ 310 static __always_inline void __load_psw_mask(unsigned long mask) 311 { 312 psw_t psw __uninitialized; 313 unsigned long addr; 314 315 psw.mask = mask; 316 317 asm volatile( 318 " larl %0,1f\n" 319 " stg %0,%1\n" 320 " lpswe %2\n" 321 "1:" 322 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc"); 323 } 324 325 /* 326 * Extract current PSW mask 327 */ 328 static inline unsigned long __extract_psw(void) 329 { 330 unsigned int reg1, reg2; 331 332 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); 333 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); 334 } 335 336 static inline unsigned long __local_mcck_save(void) 337 { 338 unsigned long mask = __extract_psw(); 339 340 __load_psw_mask(mask & ~PSW_MASK_MCHECK); 341 return mask & PSW_MASK_MCHECK; 342 } 343 344 #define local_mcck_save(mflags) \ 345 do { \ 346 typecheck(unsigned long, mflags); \ 347 mflags = __local_mcck_save(); \ 348 } while (0) 349 350 static inline void local_mcck_restore(unsigned long mflags) 351 { 352 unsigned long mask = __extract_psw(); 353 354 mask &= ~PSW_MASK_MCHECK; 355 __load_psw_mask(mask | mflags); 356 } 357 358 static inline void local_mcck_disable(void) 359 { 360 __local_mcck_save(); 361 } 362 363 static inline void local_mcck_enable(void) 364 { 365 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK); 366 } 367 368 /* 369 * Rewind PSW instruction address by specified number of bytes. 370 */ 371 static inline unsigned long __rewind_psw(psw_t psw, long ilen) 372 { 373 unsigned long mask; 374 375 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 376 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 377 (1UL << 24) - 1; 378 return (psw.addr - ilen) & mask; 379 } 380 381 static inline unsigned long __forward_psw(psw_t psw, long ilen) 382 { 383 return __rewind_psw(psw, -ilen); 384 } 385 386 /* 387 * Function to drop a processor into disabled wait state 388 */ 389 static __always_inline void __noreturn disabled_wait(void) 390 { 391 psw_t psw; 392 393 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 394 psw.addr = _THIS_IP_; 395 __load_psw(psw); 396 while (1); 397 } 398 399 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 400 401 static __always_inline bool regs_irqs_disabled(struct pt_regs *regs) 402 { 403 return arch_irqs_disabled_flags(regs->psw.mask); 404 } 405 406 static __always_inline void bpon(void) 407 { 408 asm_inline volatile( 409 ALTERNATIVE(" nop\n", 410 " .insn rrf,0xb2e80000,0,0,13,0\n", 411 ALT_SPEC(82)) 412 ); 413 } 414 415 #endif /* __ASSEMBLER__ */ 416 417 #endif /* __ASM_S390_PROCESSOR_H */ 418