1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999 4 * Author(s): Hartmut Penner (hp@de.ibm.com), 5 * Martin Schwidefsky (schwidefsky@de.ibm.com) 6 * 7 * Derived from "include/asm-i386/processor.h" 8 * Copyright (C) 1994, Linus Torvalds 9 */ 10 11 #ifndef __ASM_S390_PROCESSOR_H 12 #define __ASM_S390_PROCESSOR_H 13 14 #ifndef __ASSEMBLY__ 15 16 #include <linux/linkage.h> 17 #include <linux/irqflags.h> 18 #include <asm/cpu.h> 19 #include <asm/page.h> 20 #include <asm/ptrace.h> 21 #include <asm/setup.h> 22 #include <asm/runtime_instr.h> 23 24 /* 25 * Default implementation of macro that returns current 26 * instruction pointer ("program counter"). 27 */ 28 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; }) 29 30 static inline void get_cpu_id(struct cpuid *ptr) 31 { 32 asm volatile("stidp %0" : "=Q" (*ptr)); 33 } 34 35 extern void s390_adjust_jiffies(void); 36 extern const struct seq_operations cpuinfo_op; 37 extern int sysctl_ieee_emulation_warnings; 38 39 /* 40 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. 41 */ 42 #ifndef CONFIG_64BIT 43 44 #define TASK_SIZE (1UL << 31) 45 #define TASK_UNMAPPED_BASE (1UL << 30) 46 47 #else /* CONFIG_64BIT */ 48 49 #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) 50 #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ 51 (1UL << 30) : (1UL << 41)) 52 #define TASK_SIZE TASK_SIZE_OF(current) 53 54 #endif /* CONFIG_64BIT */ 55 56 #ifndef CONFIG_64BIT 57 #define STACK_TOP (1UL << 31) 58 #define STACK_TOP_MAX (1UL << 31) 59 #else /* CONFIG_64BIT */ 60 #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42)) 61 #define STACK_TOP_MAX (1UL << 42) 62 #endif /* CONFIG_64BIT */ 63 64 #define HAVE_ARCH_PICK_MMAP_LAYOUT 65 66 typedef struct { 67 __u32 ar4; 68 } mm_segment_t; 69 70 /* 71 * Thread structure 72 */ 73 struct thread_struct { 74 s390_fp_regs fp_regs; 75 unsigned int acrs[NUM_ACRS]; 76 unsigned long ksp; /* kernel stack pointer */ 77 mm_segment_t mm_segment; 78 unsigned long gmap_addr; /* address of last gmap fault. */ 79 struct per_regs per_user; /* User specified PER registers */ 80 struct per_event per_event; /* Cause of the last PER trap */ 81 unsigned long per_flags; /* Flags to control debug behavior */ 82 /* pfault_wait is used to block the process on a pfault event */ 83 unsigned long pfault_wait; 84 struct list_head list; 85 /* cpu runtime instrumentation */ 86 struct runtime_instr_cb *ri_cb; 87 int ri_signum; 88 #ifdef CONFIG_64BIT 89 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */ 90 #endif 91 }; 92 93 #define PER_FLAG_NO_TE 1UL /* Flag to disable transactions. */ 94 95 typedef struct thread_struct thread_struct; 96 97 /* 98 * Stack layout of a C stack frame. 99 */ 100 #ifndef __PACK_STACK 101 struct stack_frame { 102 unsigned long back_chain; 103 unsigned long empty1[5]; 104 unsigned long gprs[10]; 105 unsigned int empty2[8]; 106 }; 107 #else 108 struct stack_frame { 109 unsigned long empty1[5]; 110 unsigned int empty2[8]; 111 unsigned long gprs[10]; 112 unsigned long back_chain; 113 }; 114 #endif 115 116 #define ARCH_MIN_TASKALIGN 8 117 118 #define INIT_THREAD { \ 119 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \ 120 } 121 122 /* 123 * Do necessary setup to start up a new thread. 124 */ 125 #define start_thread(regs, new_psw, new_stackp) do { \ 126 regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \ 127 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 128 regs->gprs[15] = new_stackp; \ 129 } while (0) 130 131 #define start_thread31(regs, new_psw, new_stackp) do { \ 132 regs->psw.mask = psw_user_bits | PSW_MASK_BA; \ 133 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 134 regs->gprs[15] = new_stackp; \ 135 __tlb_flush_mm(current->mm); \ 136 crst_table_downgrade(current->mm, 1UL << 31); \ 137 update_mm(current->mm, current); \ 138 } while (0) 139 140 /* Forward declaration, a strange C thing */ 141 struct task_struct; 142 struct mm_struct; 143 struct seq_file; 144 145 #ifdef CONFIG_64BIT 146 extern void show_cacheinfo(struct seq_file *m); 147 #else 148 static inline void show_cacheinfo(struct seq_file *m) { } 149 #endif 150 151 /* Free all resources held by a thread. */ 152 extern void release_thread(struct task_struct *); 153 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 154 155 /* 156 * Return saved PC of a blocked thread. 157 */ 158 extern unsigned long thread_saved_pc(struct task_struct *t); 159 160 extern void show_code(struct pt_regs *regs); 161 extern void print_fn_code(unsigned char *code, unsigned long len); 162 163 unsigned long get_wchan(struct task_struct *p); 164 #define task_pt_regs(tsk) ((struct pt_regs *) \ 165 (task_stack_page(tsk) + THREAD_SIZE) - 1) 166 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr) 167 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15]) 168 169 static inline unsigned short stap(void) 170 { 171 unsigned short cpu_address; 172 173 asm volatile("stap %0" : "=m" (cpu_address)); 174 return cpu_address; 175 } 176 177 /* 178 * Give up the time slice of the virtual PU. 179 */ 180 static inline void cpu_relax(void) 181 { 182 if (MACHINE_HAS_DIAG44) 183 asm volatile("diag 0,0,68"); 184 barrier(); 185 } 186 187 static inline void psw_set_key(unsigned int key) 188 { 189 asm volatile("spka 0(%0)" : : "d" (key)); 190 } 191 192 /* 193 * Set PSW to specified value. 194 */ 195 static inline void __load_psw(psw_t psw) 196 { 197 #ifndef CONFIG_64BIT 198 asm volatile("lpsw %0" : : "Q" (psw) : "cc"); 199 #else 200 asm volatile("lpswe %0" : : "Q" (psw) : "cc"); 201 #endif 202 } 203 204 /* 205 * Set PSW mask to specified value, while leaving the 206 * PSW addr pointing to the next instruction. 207 */ 208 static inline void __load_psw_mask (unsigned long mask) 209 { 210 unsigned long addr; 211 psw_t psw; 212 213 psw.mask = mask; 214 215 #ifndef CONFIG_64BIT 216 asm volatile( 217 " basr %0,0\n" 218 "0: ahi %0,1f-0b\n" 219 " st %0,%O1+4(%R1)\n" 220 " lpsw %1\n" 221 "1:" 222 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 223 #else /* CONFIG_64BIT */ 224 asm volatile( 225 " larl %0,1f\n" 226 " stg %0,%O1+8(%R1)\n" 227 " lpswe %1\n" 228 "1:" 229 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc"); 230 #endif /* CONFIG_64BIT */ 231 } 232 233 /* 234 * Rewind PSW instruction address by specified number of bytes. 235 */ 236 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc) 237 { 238 #ifndef CONFIG_64BIT 239 if (psw.addr & PSW_ADDR_AMODE) 240 /* 31 bit mode */ 241 return (psw.addr - ilc) | PSW_ADDR_AMODE; 242 /* 24 bit mode */ 243 return (psw.addr - ilc) & ((1UL << 24) - 1); 244 #else 245 unsigned long mask; 246 247 mask = (psw.mask & PSW_MASK_EA) ? -1UL : 248 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : 249 (1UL << 24) - 1; 250 return (psw.addr - ilc) & mask; 251 #endif 252 } 253 254 /* 255 * Function to drop a processor into disabled wait state 256 */ 257 static inline void __noreturn disabled_wait(unsigned long code) 258 { 259 unsigned long ctl_buf; 260 psw_t dw_psw; 261 262 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; 263 dw_psw.addr = code; 264 /* 265 * Store status and then load disabled wait psw, 266 * the processor is dead afterwards 267 */ 268 #ifndef CONFIG_64BIT 269 asm volatile( 270 " stctl 0,0,0(%2)\n" 271 " ni 0(%2),0xef\n" /* switch off protection */ 272 " lctl 0,0,0(%2)\n" 273 " stpt 0xd8\n" /* store timer */ 274 " stckc 0xe0\n" /* store clock comparator */ 275 " stpx 0x108\n" /* store prefix register */ 276 " stam 0,15,0x120\n" /* store access registers */ 277 " std 0,0x160\n" /* store f0 */ 278 " std 2,0x168\n" /* store f2 */ 279 " std 4,0x170\n" /* store f4 */ 280 " std 6,0x178\n" /* store f6 */ 281 " stm 0,15,0x180\n" /* store general registers */ 282 " stctl 0,15,0x1c0\n" /* store control registers */ 283 " oi 0x1c0,0x10\n" /* fake protection bit */ 284 " lpsw 0(%1)" 285 : "=m" (ctl_buf) 286 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc"); 287 #else /* CONFIG_64BIT */ 288 asm volatile( 289 " stctg 0,0,0(%2)\n" 290 " ni 4(%2),0xef\n" /* switch off protection */ 291 " lctlg 0,0,0(%2)\n" 292 " lghi 1,0x1000\n" 293 " stpt 0x328(1)\n" /* store timer */ 294 " stckc 0x330(1)\n" /* store clock comparator */ 295 " stpx 0x318(1)\n" /* store prefix register */ 296 " stam 0,15,0x340(1)\n"/* store access registers */ 297 " stfpc 0x31c(1)\n" /* store fpu control */ 298 " std 0,0x200(1)\n" /* store f0 */ 299 " std 1,0x208(1)\n" /* store f1 */ 300 " std 2,0x210(1)\n" /* store f2 */ 301 " std 3,0x218(1)\n" /* store f3 */ 302 " std 4,0x220(1)\n" /* store f4 */ 303 " std 5,0x228(1)\n" /* store f5 */ 304 " std 6,0x230(1)\n" /* store f6 */ 305 " std 7,0x238(1)\n" /* store f7 */ 306 " std 8,0x240(1)\n" /* store f8 */ 307 " std 9,0x248(1)\n" /* store f9 */ 308 " std 10,0x250(1)\n" /* store f10 */ 309 " std 11,0x258(1)\n" /* store f11 */ 310 " std 12,0x260(1)\n" /* store f12 */ 311 " std 13,0x268(1)\n" /* store f13 */ 312 " std 14,0x270(1)\n" /* store f14 */ 313 " std 15,0x278(1)\n" /* store f15 */ 314 " stmg 0,15,0x280(1)\n"/* store general registers */ 315 " stctg 0,15,0x380(1)\n"/* store control registers */ 316 " oi 0x384(1),0x10\n"/* fake protection bit */ 317 " lpswe 0(%1)" 318 : "=m" (ctl_buf) 319 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1"); 320 #endif /* CONFIG_64BIT */ 321 while (1); 322 } 323 324 /* 325 * Use to set psw mask except for the first byte which 326 * won't be changed by this function. 327 */ 328 static inline void 329 __set_psw_mask(unsigned long mask) 330 { 331 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); 332 } 333 334 #define local_mcck_enable() \ 335 __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK) 336 #define local_mcck_disable() \ 337 __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT) 338 339 /* 340 * Basic Machine Check/Program Check Handler. 341 */ 342 343 extern void s390_base_mcck_handler(void); 344 extern void s390_base_pgm_handler(void); 345 extern void s390_base_ext_handler(void); 346 347 extern void (*s390_base_mcck_handler_fn)(void); 348 extern void (*s390_base_pgm_handler_fn)(void); 349 extern void (*s390_base_ext_handler_fn)(void); 350 351 #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 352 353 extern int memcpy_real(void *, void *, size_t); 354 extern void memcpy_absolute(void *, void *, size_t); 355 356 #define mem_assign_absolute(dest, val) { \ 357 __typeof__(dest) __tmp = (val); \ 358 \ 359 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \ 360 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \ 361 } 362 363 /* 364 * Helper macro for exception table entries 365 */ 366 #define EX_TABLE(_fault, _target) \ 367 ".section __ex_table,\"a\"\n" \ 368 ".align 4\n" \ 369 ".long (" #_fault ") - .\n" \ 370 ".long (" #_target ") - .\n" \ 371 ".previous\n" 372 373 #else /* __ASSEMBLY__ */ 374 375 #define EX_TABLE(_fault, _target) \ 376 .section __ex_table,"a" ; \ 377 .align 4 ; \ 378 .long (_fault) - . ; \ 379 .long (_target) - . ; \ 380 .previous 381 382 #endif /* __ASSEMBLY__ */ 383 384 #endif /* __ASM_S390_PROCESSOR_H */ 385