1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <asm/bug.h> 33 #include <asm/page.h> 34 35 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 36 extern void paging_init(void); 37 extern void vmem_map_init(void); 38 extern void fault_init(void); 39 40 /* 41 * The S390 doesn't have any external MMU info: the kernel page 42 * tables contain all the necessary information. 43 */ 44 #define update_mmu_cache(vma, address, ptep) do { } while (0) 45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero; used 49 * for zero-mapped memory areas etc.. 50 */ 51 52 extern unsigned long empty_zero_page; 53 extern unsigned long zero_page_mask; 54 55 #define ZERO_PAGE(vaddr) \ 56 (virt_to_page((void *)(empty_zero_page + \ 57 (((unsigned long)(vaddr)) &zero_page_mask)))) 58 59 #define is_zero_pfn is_zero_pfn 60 static inline int is_zero_pfn(unsigned long pfn) 61 { 62 extern unsigned long zero_pfn; 63 unsigned long offset_from_zero_pfn = pfn - zero_pfn; 64 return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); 65 } 66 67 #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) 68 69 #endif /* !__ASSEMBLY__ */ 70 71 /* 72 * PMD_SHIFT determines the size of the area a second-level page 73 * table can map 74 * PGDIR_SHIFT determines what a third-level page table entry can map 75 */ 76 #ifndef CONFIG_64BIT 77 # define PMD_SHIFT 20 78 # define PUD_SHIFT 20 79 # define PGDIR_SHIFT 20 80 #else /* CONFIG_64BIT */ 81 # define PMD_SHIFT 20 82 # define PUD_SHIFT 31 83 # define PGDIR_SHIFT 42 84 #endif /* CONFIG_64BIT */ 85 86 #define PMD_SIZE (1UL << PMD_SHIFT) 87 #define PMD_MASK (~(PMD_SIZE-1)) 88 #define PUD_SIZE (1UL << PUD_SHIFT) 89 #define PUD_MASK (~(PUD_SIZE-1)) 90 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 91 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 92 93 /* 94 * entries per page directory level: the S390 is two-level, so 95 * we don't really have any PMD directory physically. 96 * for S390 segment-table entries are combined to one PGD 97 * that leads to 1024 pte per pgd 98 */ 99 #define PTRS_PER_PTE 256 100 #ifndef CONFIG_64BIT 101 #define PTRS_PER_PMD 1 102 #define PTRS_PER_PUD 1 103 #else /* CONFIG_64BIT */ 104 #define PTRS_PER_PMD 2048 105 #define PTRS_PER_PUD 2048 106 #endif /* CONFIG_64BIT */ 107 #define PTRS_PER_PGD 2048 108 109 #define FIRST_USER_ADDRESS 0 110 111 #define pte_ERROR(e) \ 112 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 113 #define pmd_ERROR(e) \ 114 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 115 #define pud_ERROR(e) \ 116 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 117 #define pgd_ERROR(e) \ 118 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 119 120 #ifndef __ASSEMBLY__ 121 /* 122 * The vmalloc and module area will always be on the topmost area of the kernel 123 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 124 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 125 * modules will reside. That makes sure that inter module branches always 126 * happen without trampolines and in addition the placement within a 2GB frame 127 * is branch prediction unit friendly. 128 */ 129 extern unsigned long VMALLOC_START; 130 extern unsigned long VMALLOC_END; 131 extern struct page *vmemmap; 132 133 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 134 135 #ifdef CONFIG_64BIT 136 extern unsigned long MODULES_VADDR; 137 extern unsigned long MODULES_END; 138 #define MODULES_VADDR MODULES_VADDR 139 #define MODULES_END MODULES_END 140 #define MODULES_LEN (1UL << 31) 141 #endif 142 143 /* 144 * A 31 bit pagetable entry of S390 has following format: 145 * | PFRA | | OS | 146 * 0 0IP0 147 * 00000000001111111111222222222233 148 * 01234567890123456789012345678901 149 * 150 * I Page-Invalid Bit: Page is not available for address-translation 151 * P Page-Protection Bit: Store access not possible for page 152 * 153 * A 31 bit segmenttable entry of S390 has following format: 154 * | P-table origin | |PTL 155 * 0 IC 156 * 00000000001111111111222222222233 157 * 01234567890123456789012345678901 158 * 159 * I Segment-Invalid Bit: Segment is not available for address-translation 160 * C Common-Segment Bit: Segment is not private (PoP 3-30) 161 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 162 * 163 * The 31 bit segmenttable origin of S390 has following format: 164 * 165 * |S-table origin | | STL | 166 * X **GPS 167 * 00000000001111111111222222222233 168 * 01234567890123456789012345678901 169 * 170 * X Space-Switch event: 171 * G Segment-Invalid Bit: * 172 * P Private-Space Bit: Segment is not private (PoP 3-30) 173 * S Storage-Alteration: 174 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 175 * 176 * A 64 bit pagetable entry of S390 has following format: 177 * | PFRA |0IPC| OS | 178 * 0000000000111111111122222222223333333333444444444455555555556666 179 * 0123456789012345678901234567890123456789012345678901234567890123 180 * 181 * I Page-Invalid Bit: Page is not available for address-translation 182 * P Page-Protection Bit: Store access not possible for page 183 * C Change-bit override: HW is not required to set change bit 184 * 185 * A 64 bit segmenttable entry of S390 has following format: 186 * | P-table origin | TT 187 * 0000000000111111111122222222223333333333444444444455555555556666 188 * 0123456789012345678901234567890123456789012345678901234567890123 189 * 190 * I Segment-Invalid Bit: Segment is not available for address-translation 191 * C Common-Segment Bit: Segment is not private (PoP 3-30) 192 * P Page-Protection Bit: Store access not possible for page 193 * TT Type 00 194 * 195 * A 64 bit region table entry of S390 has following format: 196 * | S-table origin | TF TTTL 197 * 0000000000111111111122222222223333333333444444444455555555556666 198 * 0123456789012345678901234567890123456789012345678901234567890123 199 * 200 * I Segment-Invalid Bit: Segment is not available for address-translation 201 * TT Type 01 202 * TF 203 * TL Table length 204 * 205 * The 64 bit regiontable origin of S390 has following format: 206 * | region table origon | DTTL 207 * 0000000000111111111122222222223333333333444444444455555555556666 208 * 0123456789012345678901234567890123456789012345678901234567890123 209 * 210 * X Space-Switch event: 211 * G Segment-Invalid Bit: 212 * P Private-Space Bit: 213 * S Storage-Alteration: 214 * R Real space 215 * TL Table-Length: 216 * 217 * A storage key has the following format: 218 * | ACC |F|R|C|0| 219 * 0 3 4 5 6 7 220 * ACC: access key 221 * F : fetch protection bit 222 * R : referenced bit 223 * C : changed bit 224 */ 225 226 /* Hardware bits in the page table entry */ 227 #define _PAGE_CO 0x100 /* HW Change-bit override */ 228 #define _PAGE_RO 0x200 /* HW read-only bit */ 229 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 230 231 /* Software bits in the page table entry */ 232 #define _PAGE_SWT 0x001 /* SW pte type bit t */ 233 #define _PAGE_SWX 0x002 /* SW pte type bit x */ 234 #define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */ 235 #define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */ 236 #define _PAGE_SPECIAL 0x010 /* SW associated with special page */ 237 #define __HAVE_ARCH_PTE_SPECIAL 238 239 /* Set of bits not changed in pte_modify */ 240 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR) 241 242 /* Six different types of pages. */ 243 #define _PAGE_TYPE_EMPTY 0x400 244 #define _PAGE_TYPE_NONE 0x401 245 #define _PAGE_TYPE_SWAP 0x403 246 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ 247 #define _PAGE_TYPE_RO 0x200 248 #define _PAGE_TYPE_RW 0x000 249 250 /* 251 * Only four types for huge pages, using the invalid bit and protection bit 252 * of a segment table entry. 253 */ 254 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ 255 #define _HPAGE_TYPE_NONE 0x220 256 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ 257 #define _HPAGE_TYPE_RW 0x000 258 259 /* 260 * PTE type bits are rather complicated. handle_pte_fault uses pte_present, 261 * pte_none and pte_file to find out the pte type WITHOUT holding the page 262 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to 263 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs 264 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. 265 * This change is done while holding the lock, but the intermediate step 266 * of a previously valid pte with the hw invalid bit set can be observed by 267 * handle_pte_fault. That makes it necessary that all valid pte types with 268 * the hw invalid bit set must be distinguishable from the four pte types 269 * empty, none, swap and file. 270 * 271 * irxt ipte irxt 272 * _PAGE_TYPE_EMPTY 1000 -> 1000 273 * _PAGE_TYPE_NONE 1001 -> 1001 274 * _PAGE_TYPE_SWAP 1011 -> 1011 275 * _PAGE_TYPE_FILE 11?1 -> 11?1 276 * _PAGE_TYPE_RO 0100 -> 1100 277 * _PAGE_TYPE_RW 0000 -> 1000 278 * 279 * pte_none is true for bits combinations 1000, 1010, 1100, 1110 280 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 281 * pte_file is true for bits combinations 1101, 1111 282 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. 283 */ 284 285 #ifndef CONFIG_64BIT 286 287 /* Bits in the segment table address-space-control-element */ 288 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 289 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 290 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 291 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 292 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 293 294 /* Bits in the segment table entry */ 295 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 296 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 297 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 298 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 299 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 300 301 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 302 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 303 304 /* Page status table bits for virtualization */ 305 #define RCP_ACC_BITS 0xf0000000UL 306 #define RCP_FP_BIT 0x08000000UL 307 #define RCP_PCL_BIT 0x00800000UL 308 #define RCP_HR_BIT 0x00400000UL 309 #define RCP_HC_BIT 0x00200000UL 310 #define RCP_GR_BIT 0x00040000UL 311 #define RCP_GC_BIT 0x00020000UL 312 313 /* User dirty / referenced bit for KVM's migration feature */ 314 #define KVM_UR_BIT 0x00008000UL 315 #define KVM_UC_BIT 0x00004000UL 316 317 #else /* CONFIG_64BIT */ 318 319 /* Bits in the segment/region table address-space-control-element */ 320 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 321 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 322 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 323 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 324 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 325 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 326 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 327 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 328 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 329 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 330 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 331 332 /* Bits in the region table entry */ 333 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 334 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 335 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 336 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 337 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 338 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 339 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 340 341 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 342 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) 343 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 344 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) 345 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 346 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) 347 348 /* Bits in the segment table entry */ 349 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 350 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 351 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 352 353 #define _SEGMENT_ENTRY (0) 354 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 355 356 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 357 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 358 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 359 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT) 360 361 /* Set of bits not changed in pmd_modify */ 362 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 363 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 364 365 /* Page status table bits for virtualization */ 366 #define RCP_ACC_BITS 0xf000000000000000UL 367 #define RCP_FP_BIT 0x0800000000000000UL 368 #define RCP_PCL_BIT 0x0080000000000000UL 369 #define RCP_HR_BIT 0x0040000000000000UL 370 #define RCP_HC_BIT 0x0020000000000000UL 371 #define RCP_GR_BIT 0x0004000000000000UL 372 #define RCP_GC_BIT 0x0002000000000000UL 373 374 /* User dirty / referenced bit for KVM's migration feature */ 375 #define KVM_UR_BIT 0x0000800000000000UL 376 #define KVM_UC_BIT 0x0000400000000000UL 377 378 #endif /* CONFIG_64BIT */ 379 380 /* 381 * A user page table pointer has the space-switch-event bit, the 382 * private-space-control bit and the storage-alteration-event-control 383 * bit set. A kernel page table pointer doesn't need them. 384 */ 385 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 386 _ASCE_ALT_EVENT) 387 388 /* 389 * Page protection definitions. 390 */ 391 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) 392 #define PAGE_RO __pgprot(_PAGE_TYPE_RO) 393 #define PAGE_RW __pgprot(_PAGE_TYPE_RW) 394 395 #define PAGE_KERNEL PAGE_RW 396 #define PAGE_COPY PAGE_RO 397 398 /* 399 * On s390 the page table entry has an invalid bit and a read-only bit. 400 * Read permission implies execute permission and write permission 401 * implies read permission. 402 */ 403 /*xwr*/ 404 #define __P000 PAGE_NONE 405 #define __P001 PAGE_RO 406 #define __P010 PAGE_RO 407 #define __P011 PAGE_RO 408 #define __P100 PAGE_RO 409 #define __P101 PAGE_RO 410 #define __P110 PAGE_RO 411 #define __P111 PAGE_RO 412 413 #define __S000 PAGE_NONE 414 #define __S001 PAGE_RO 415 #define __S010 PAGE_RW 416 #define __S011 PAGE_RW 417 #define __S100 PAGE_RO 418 #define __S101 PAGE_RO 419 #define __S110 PAGE_RW 420 #define __S111 PAGE_RW 421 422 static inline int mm_exclusive(struct mm_struct *mm) 423 { 424 return likely(mm == current->active_mm && 425 atomic_read(&mm->context.attach_count) <= 1); 426 } 427 428 static inline int mm_has_pgste(struct mm_struct *mm) 429 { 430 #ifdef CONFIG_PGSTE 431 if (unlikely(mm->context.has_pgste)) 432 return 1; 433 #endif 434 return 0; 435 } 436 /* 437 * pgd/pmd/pte query functions 438 */ 439 #ifndef CONFIG_64BIT 440 441 static inline int pgd_present(pgd_t pgd) { return 1; } 442 static inline int pgd_none(pgd_t pgd) { return 0; } 443 static inline int pgd_bad(pgd_t pgd) { return 0; } 444 445 static inline int pud_present(pud_t pud) { return 1; } 446 static inline int pud_none(pud_t pud) { return 0; } 447 static inline int pud_bad(pud_t pud) { return 0; } 448 449 #else /* CONFIG_64BIT */ 450 451 static inline int pgd_present(pgd_t pgd) 452 { 453 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 454 return 1; 455 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 456 } 457 458 static inline int pgd_none(pgd_t pgd) 459 { 460 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 461 return 0; 462 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; 463 } 464 465 static inline int pgd_bad(pgd_t pgd) 466 { 467 /* 468 * With dynamic page table levels the pgd can be a region table 469 * entry or a segment table entry. Check for the bit that are 470 * invalid for either table entry. 471 */ 472 unsigned long mask = 473 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 474 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 475 return (pgd_val(pgd) & mask) != 0; 476 } 477 478 static inline int pud_present(pud_t pud) 479 { 480 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 481 return 1; 482 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 483 } 484 485 static inline int pud_none(pud_t pud) 486 { 487 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 488 return 0; 489 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; 490 } 491 492 static inline int pud_bad(pud_t pud) 493 { 494 /* 495 * With dynamic page table levels the pud can be a region table 496 * entry or a segment table entry. Check for the bit that are 497 * invalid for either table entry. 498 */ 499 unsigned long mask = 500 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 501 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 502 return (pud_val(pud) & mask) != 0; 503 } 504 505 #endif /* CONFIG_64BIT */ 506 507 static inline int pmd_present(pmd_t pmd) 508 { 509 return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; 510 } 511 512 static inline int pmd_none(pmd_t pmd) 513 { 514 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; 515 } 516 517 static inline int pmd_large(pmd_t pmd) 518 { 519 #ifdef CONFIG_64BIT 520 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE); 521 #else 522 return 0; 523 #endif 524 } 525 526 static inline int pmd_bad(pmd_t pmd) 527 { 528 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; 529 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; 530 } 531 532 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 533 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 534 unsigned long addr, pmd_t *pmdp); 535 536 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 537 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 538 unsigned long address, pmd_t *pmdp, 539 pmd_t entry, int dirty); 540 541 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 542 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 543 unsigned long address, pmd_t *pmdp); 544 545 #define __HAVE_ARCH_PMD_WRITE 546 static inline int pmd_write(pmd_t pmd) 547 { 548 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0; 549 } 550 551 static inline int pmd_young(pmd_t pmd) 552 { 553 return 0; 554 } 555 556 static inline int pte_none(pte_t pte) 557 { 558 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); 559 } 560 561 static inline int pte_present(pte_t pte) 562 { 563 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; 564 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || 565 (!(pte_val(pte) & _PAGE_INVALID) && 566 !(pte_val(pte) & _PAGE_SWT)); 567 } 568 569 static inline int pte_file(pte_t pte) 570 { 571 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; 572 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; 573 } 574 575 static inline int pte_special(pte_t pte) 576 { 577 return (pte_val(pte) & _PAGE_SPECIAL); 578 } 579 580 #define __HAVE_ARCH_PTE_SAME 581 static inline int pte_same(pte_t a, pte_t b) 582 { 583 return pte_val(a) == pte_val(b); 584 } 585 586 static inline pgste_t pgste_get_lock(pte_t *ptep) 587 { 588 unsigned long new = 0; 589 #ifdef CONFIG_PGSTE 590 unsigned long old; 591 592 preempt_disable(); 593 asm( 594 " lg %0,%2\n" 595 "0: lgr %1,%0\n" 596 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */ 597 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */ 598 " csg %0,%1,%2\n" 599 " jl 0b\n" 600 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 601 : "Q" (ptep[PTRS_PER_PTE]) : "cc"); 602 #endif 603 return __pgste(new); 604 } 605 606 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 607 { 608 #ifdef CONFIG_PGSTE 609 asm( 610 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ 611 " stg %1,%0\n" 612 : "=Q" (ptep[PTRS_PER_PTE]) 613 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); 614 preempt_enable(); 615 #endif 616 } 617 618 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 619 { 620 #ifdef CONFIG_PGSTE 621 unsigned long address, bits; 622 unsigned char skey; 623 624 if (!pte_present(*ptep)) 625 return pgste; 626 address = pte_val(*ptep) & PAGE_MASK; 627 skey = page_get_storage_key(address); 628 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 629 /* Clear page changed & referenced bit in the storage key */ 630 if (bits & _PAGE_CHANGED) 631 page_set_storage_key(address, skey ^ bits, 1); 632 else if (bits) 633 page_reset_referenced(address); 634 /* Transfer page changed & referenced bit to guest bits in pgste */ 635 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */ 636 /* Get host changed & referenced bits from pgste */ 637 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52; 638 /* Clear host bits in pgste. */ 639 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT); 640 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT); 641 /* Copy page access key and fetch protection bit to pgste */ 642 pgste_val(pgste) |= 643 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 644 /* Transfer changed and referenced to kvm user bits */ 645 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */ 646 /* Transfer changed & referenced to pte sofware bits */ 647 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */ 648 #endif 649 return pgste; 650 651 } 652 653 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) 654 { 655 #ifdef CONFIG_PGSTE 656 int young; 657 658 if (!pte_present(*ptep)) 659 return pgste; 660 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); 661 /* Transfer page referenced bit to pte software bit (host view) */ 662 if (young || (pgste_val(pgste) & RCP_HR_BIT)) 663 pte_val(*ptep) |= _PAGE_SWR; 664 /* Clear host referenced bit in pgste. */ 665 pgste_val(pgste) &= ~RCP_HR_BIT; 666 /* Transfer page referenced bit to guest bit in pgste */ 667 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */ 668 #endif 669 return pgste; 670 671 } 672 673 static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) 674 { 675 #ifdef CONFIG_PGSTE 676 unsigned long address; 677 unsigned long okey, nkey; 678 679 if (!pte_present(entry)) 680 return; 681 address = pte_val(entry) & PAGE_MASK; 682 okey = nkey = page_get_storage_key(address); 683 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT); 684 /* Set page access key and fetch protection bit from pgste */ 685 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; 686 if (okey != nkey) 687 page_set_storage_key(address, nkey, 1); 688 #endif 689 } 690 691 /** 692 * struct gmap_struct - guest address space 693 * @mm: pointer to the parent mm_struct 694 * @table: pointer to the page directory 695 * @asce: address space control element for gmap page table 696 * @crst_list: list of all crst tables used in the guest address space 697 */ 698 struct gmap { 699 struct list_head list; 700 struct mm_struct *mm; 701 unsigned long *table; 702 unsigned long asce; 703 struct list_head crst_list; 704 }; 705 706 /** 707 * struct gmap_rmap - reverse mapping for segment table entries 708 * @next: pointer to the next gmap_rmap structure in the list 709 * @entry: pointer to a segment table entry 710 */ 711 struct gmap_rmap { 712 struct list_head list; 713 unsigned long *entry; 714 }; 715 716 /** 717 * struct gmap_pgtable - gmap information attached to a page table 718 * @vmaddr: address of the 1MB segment in the process virtual memory 719 * @mapper: list of segment table entries maping a page table 720 */ 721 struct gmap_pgtable { 722 unsigned long vmaddr; 723 struct list_head mapper; 724 }; 725 726 struct gmap *gmap_alloc(struct mm_struct *mm); 727 void gmap_free(struct gmap *gmap); 728 void gmap_enable(struct gmap *gmap); 729 void gmap_disable(struct gmap *gmap); 730 int gmap_map_segment(struct gmap *gmap, unsigned long from, 731 unsigned long to, unsigned long length); 732 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 733 unsigned long __gmap_fault(unsigned long address, struct gmap *); 734 unsigned long gmap_fault(unsigned long address, struct gmap *); 735 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 736 737 /* 738 * Certain architectures need to do special things when PTEs 739 * within a page table are directly modified. Thus, the following 740 * hook is made available. 741 */ 742 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 743 pte_t *ptep, pte_t entry) 744 { 745 pgste_t pgste; 746 747 if (mm_has_pgste(mm)) { 748 pgste = pgste_get_lock(ptep); 749 pgste_set_pte(ptep, pgste, entry); 750 *ptep = entry; 751 pgste_set_unlock(ptep, pgste); 752 } else 753 *ptep = entry; 754 } 755 756 /* 757 * query functions pte_write/pte_dirty/pte_young only work if 758 * pte_present() is true. Undefined behaviour if not.. 759 */ 760 static inline int pte_write(pte_t pte) 761 { 762 return (pte_val(pte) & _PAGE_RO) == 0; 763 } 764 765 static inline int pte_dirty(pte_t pte) 766 { 767 #ifdef CONFIG_PGSTE 768 if (pte_val(pte) & _PAGE_SWC) 769 return 1; 770 #endif 771 return 0; 772 } 773 774 static inline int pte_young(pte_t pte) 775 { 776 #ifdef CONFIG_PGSTE 777 if (pte_val(pte) & _PAGE_SWR) 778 return 1; 779 #endif 780 return 0; 781 } 782 783 /* 784 * pgd/pmd/pte modification functions 785 */ 786 787 static inline void pgd_clear(pgd_t *pgd) 788 { 789 #ifdef CONFIG_64BIT 790 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 791 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 792 #endif 793 } 794 795 static inline void pud_clear(pud_t *pud) 796 { 797 #ifdef CONFIG_64BIT 798 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 799 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 800 #endif 801 } 802 803 static inline void pmd_clear(pmd_t *pmdp) 804 { 805 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 806 } 807 808 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 809 { 810 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 811 } 812 813 /* 814 * The following pte modification functions only work if 815 * pte_present() is true. Undefined behaviour if not.. 816 */ 817 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 818 { 819 pte_val(pte) &= _PAGE_CHG_MASK; 820 pte_val(pte) |= pgprot_val(newprot); 821 return pte; 822 } 823 824 static inline pte_t pte_wrprotect(pte_t pte) 825 { 826 /* Do not clobber _PAGE_TYPE_NONE pages! */ 827 if (!(pte_val(pte) & _PAGE_INVALID)) 828 pte_val(pte) |= _PAGE_RO; 829 return pte; 830 } 831 832 static inline pte_t pte_mkwrite(pte_t pte) 833 { 834 pte_val(pte) &= ~_PAGE_RO; 835 return pte; 836 } 837 838 static inline pte_t pte_mkclean(pte_t pte) 839 { 840 #ifdef CONFIG_PGSTE 841 pte_val(pte) &= ~_PAGE_SWC; 842 #endif 843 return pte; 844 } 845 846 static inline pte_t pte_mkdirty(pte_t pte) 847 { 848 return pte; 849 } 850 851 static inline pte_t pte_mkold(pte_t pte) 852 { 853 #ifdef CONFIG_PGSTE 854 pte_val(pte) &= ~_PAGE_SWR; 855 #endif 856 return pte; 857 } 858 859 static inline pte_t pte_mkyoung(pte_t pte) 860 { 861 return pte; 862 } 863 864 static inline pte_t pte_mkspecial(pte_t pte) 865 { 866 pte_val(pte) |= _PAGE_SPECIAL; 867 return pte; 868 } 869 870 #ifdef CONFIG_HUGETLB_PAGE 871 static inline pte_t pte_mkhuge(pte_t pte) 872 { 873 /* 874 * PROT_NONE needs to be remapped from the pte type to the ste type. 875 * The HW invalid bit is also different for pte and ste. The pte 876 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE 877 * bit, so we don't have to clear it. 878 */ 879 if (pte_val(pte) & _PAGE_INVALID) { 880 if (pte_val(pte) & _PAGE_SWT) 881 pte_val(pte) |= _HPAGE_TYPE_NONE; 882 pte_val(pte) |= _SEGMENT_ENTRY_INV; 883 } 884 /* 885 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment 886 * table entry. 887 */ 888 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX); 889 /* 890 * Also set the change-override bit because we don't need dirty bit 891 * tracking for hugetlbfs pages. 892 */ 893 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO); 894 return pte; 895 } 896 #endif 897 898 /* 899 * Get (and clear) the user dirty bit for a pte. 900 */ 901 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 902 pte_t *ptep) 903 { 904 pgste_t pgste; 905 int dirty = 0; 906 907 if (mm_has_pgste(mm)) { 908 pgste = pgste_get_lock(ptep); 909 pgste = pgste_update_all(ptep, pgste); 910 dirty = !!(pgste_val(pgste) & KVM_UC_BIT); 911 pgste_val(pgste) &= ~KVM_UC_BIT; 912 pgste_set_unlock(ptep, pgste); 913 return dirty; 914 } 915 return dirty; 916 } 917 918 /* 919 * Get (and clear) the user referenced bit for a pte. 920 */ 921 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, 922 pte_t *ptep) 923 { 924 pgste_t pgste; 925 int young = 0; 926 927 if (mm_has_pgste(mm)) { 928 pgste = pgste_get_lock(ptep); 929 pgste = pgste_update_young(ptep, pgste); 930 young = !!(pgste_val(pgste) & KVM_UR_BIT); 931 pgste_val(pgste) &= ~KVM_UR_BIT; 932 pgste_set_unlock(ptep, pgste); 933 } 934 return young; 935 } 936 937 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 938 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 939 unsigned long addr, pte_t *ptep) 940 { 941 pgste_t pgste; 942 pte_t pte; 943 944 if (mm_has_pgste(vma->vm_mm)) { 945 pgste = pgste_get_lock(ptep); 946 pgste = pgste_update_young(ptep, pgste); 947 pte = *ptep; 948 *ptep = pte_mkold(pte); 949 pgste_set_unlock(ptep, pgste); 950 return pte_young(pte); 951 } 952 return 0; 953 } 954 955 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 956 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 957 unsigned long address, pte_t *ptep) 958 { 959 /* No need to flush TLB 960 * On s390 reference bits are in storage key and never in TLB 961 * With virtualization we handle the reference bit, without we 962 * we can simply return */ 963 return ptep_test_and_clear_young(vma, address, ptep); 964 } 965 966 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 967 { 968 if (!(pte_val(*ptep) & _PAGE_INVALID)) { 969 #ifndef CONFIG_64BIT 970 /* pto must point to the start of the segment table */ 971 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); 972 #else 973 /* ipte in zarch mode can do the math */ 974 pte_t *pto = ptep; 975 #endif 976 asm volatile( 977 " ipte %2,%3" 978 : "=m" (*ptep) : "m" (*ptep), 979 "a" (pto), "a" (address)); 980 } 981 } 982 983 /* 984 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 985 * both clear the TLB for the unmapped pte. The reason is that 986 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 987 * to modify an active pte. The sequence is 988 * 1) ptep_get_and_clear 989 * 2) set_pte_at 990 * 3) flush_tlb_range 991 * On s390 the tlb needs to get flushed with the modification of the pte 992 * if the pte is active. The only way how this can be implemented is to 993 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 994 * is a nop. 995 */ 996 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 997 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 998 unsigned long address, pte_t *ptep) 999 { 1000 pgste_t pgste; 1001 pte_t pte; 1002 1003 mm->context.flush_mm = 1; 1004 if (mm_has_pgste(mm)) 1005 pgste = pgste_get_lock(ptep); 1006 1007 pte = *ptep; 1008 if (!mm_exclusive(mm)) 1009 __ptep_ipte(address, ptep); 1010 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1011 1012 if (mm_has_pgste(mm)) { 1013 pgste = pgste_update_all(&pte, pgste); 1014 pgste_set_unlock(ptep, pgste); 1015 } 1016 return pte; 1017 } 1018 1019 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1020 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1021 unsigned long address, 1022 pte_t *ptep) 1023 { 1024 pte_t pte; 1025 1026 mm->context.flush_mm = 1; 1027 if (mm_has_pgste(mm)) 1028 pgste_get_lock(ptep); 1029 1030 pte = *ptep; 1031 if (!mm_exclusive(mm)) 1032 __ptep_ipte(address, ptep); 1033 return pte; 1034 } 1035 1036 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1037 unsigned long address, 1038 pte_t *ptep, pte_t pte) 1039 { 1040 *ptep = pte; 1041 if (mm_has_pgste(mm)) 1042 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE)); 1043 } 1044 1045 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1046 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1047 unsigned long address, pte_t *ptep) 1048 { 1049 pgste_t pgste; 1050 pte_t pte; 1051 1052 if (mm_has_pgste(vma->vm_mm)) 1053 pgste = pgste_get_lock(ptep); 1054 1055 pte = *ptep; 1056 __ptep_ipte(address, ptep); 1057 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1058 1059 if (mm_has_pgste(vma->vm_mm)) { 1060 pgste = pgste_update_all(&pte, pgste); 1061 pgste_set_unlock(ptep, pgste); 1062 } 1063 return pte; 1064 } 1065 1066 /* 1067 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1068 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1069 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1070 * cannot be accessed while the batched unmap is running. In this case 1071 * full==1 and a simple pte_clear is enough. See tlb.h. 1072 */ 1073 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1074 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1075 unsigned long address, 1076 pte_t *ptep, int full) 1077 { 1078 pgste_t pgste; 1079 pte_t pte; 1080 1081 if (mm_has_pgste(mm)) 1082 pgste = pgste_get_lock(ptep); 1083 1084 pte = *ptep; 1085 if (!full) 1086 __ptep_ipte(address, ptep); 1087 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1088 1089 if (mm_has_pgste(mm)) { 1090 pgste = pgste_update_all(&pte, pgste); 1091 pgste_set_unlock(ptep, pgste); 1092 } 1093 return pte; 1094 } 1095 1096 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1097 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1098 unsigned long address, pte_t *ptep) 1099 { 1100 pgste_t pgste; 1101 pte_t pte = *ptep; 1102 1103 if (pte_write(pte)) { 1104 mm->context.flush_mm = 1; 1105 if (mm_has_pgste(mm)) 1106 pgste = pgste_get_lock(ptep); 1107 1108 if (!mm_exclusive(mm)) 1109 __ptep_ipte(address, ptep); 1110 *ptep = pte_wrprotect(pte); 1111 1112 if (mm_has_pgste(mm)) 1113 pgste_set_unlock(ptep, pgste); 1114 } 1115 return pte; 1116 } 1117 1118 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1119 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1120 unsigned long address, pte_t *ptep, 1121 pte_t entry, int dirty) 1122 { 1123 pgste_t pgste; 1124 1125 if (pte_same(*ptep, entry)) 1126 return 0; 1127 if (mm_has_pgste(vma->vm_mm)) 1128 pgste = pgste_get_lock(ptep); 1129 1130 __ptep_ipte(address, ptep); 1131 *ptep = entry; 1132 1133 if (mm_has_pgste(vma->vm_mm)) 1134 pgste_set_unlock(ptep, pgste); 1135 return 1; 1136 } 1137 1138 /* 1139 * Conversion functions: convert a page and protection to a page entry, 1140 * and a page entry and page directory to the page they refer to. 1141 */ 1142 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1143 { 1144 pte_t __pte; 1145 pte_val(__pte) = physpage + pgprot_val(pgprot); 1146 return __pte; 1147 } 1148 1149 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1150 { 1151 unsigned long physpage = page_to_phys(page); 1152 1153 return mk_pte_phys(physpage, pgprot); 1154 } 1155 1156 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1157 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1158 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1159 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1160 1161 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1162 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1163 1164 #ifndef CONFIG_64BIT 1165 1166 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1167 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1168 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1169 1170 #define pud_offset(pgd, address) ((pud_t *) pgd) 1171 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1172 1173 #else /* CONFIG_64BIT */ 1174 1175 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1176 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1177 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1178 1179 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1180 { 1181 pud_t *pud = (pud_t *) pgd; 1182 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1183 pud = (pud_t *) pgd_deref(*pgd); 1184 return pud + pud_index(address); 1185 } 1186 1187 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1188 { 1189 pmd_t *pmd = (pmd_t *) pud; 1190 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1191 pmd = (pmd_t *) pud_deref(*pud); 1192 return pmd + pmd_index(address); 1193 } 1194 1195 #endif /* CONFIG_64BIT */ 1196 1197 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1198 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1199 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1200 1201 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1202 1203 /* Find an entry in the lowest level page table.. */ 1204 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1205 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1206 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1207 #define pte_unmap(pte) do { } while (0) 1208 1209 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) 1210 { 1211 unsigned long sto = (unsigned long) pmdp - 1212 pmd_index(address) * sizeof(pmd_t); 1213 1214 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) { 1215 asm volatile( 1216 " .insn rrf,0xb98e0000,%2,%3,0,0" 1217 : "=m" (*pmdp) 1218 : "m" (*pmdp), "a" (sto), 1219 "a" ((address & HPAGE_MASK)) 1220 : "cc" 1221 ); 1222 } 1223 } 1224 1225 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1226 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1227 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable); 1228 1229 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1230 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm); 1231 1232 static inline int pmd_trans_splitting(pmd_t pmd) 1233 { 1234 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1235 } 1236 1237 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1238 pmd_t *pmdp, pmd_t entry) 1239 { 1240 *pmdp = entry; 1241 } 1242 1243 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1244 { 1245 unsigned long pgprot_pmd = 0; 1246 1247 if (pgprot_val(pgprot) & _PAGE_INVALID) { 1248 if (pgprot_val(pgprot) & _PAGE_SWT) 1249 pgprot_pmd |= _HPAGE_TYPE_NONE; 1250 pgprot_pmd |= _SEGMENT_ENTRY_INV; 1251 } 1252 if (pgprot_val(pgprot) & _PAGE_RO) 1253 pgprot_pmd |= _SEGMENT_ENTRY_RO; 1254 return pgprot_pmd; 1255 } 1256 1257 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1258 { 1259 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1260 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1261 return pmd; 1262 } 1263 1264 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1265 { 1266 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1267 return pmd; 1268 } 1269 1270 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1271 { 1272 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; 1273 return pmd; 1274 } 1275 1276 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1277 { 1278 pmd_val(pmd) |= _SEGMENT_ENTRY_RO; 1279 return pmd; 1280 } 1281 1282 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1283 { 1284 /* No dirty bit in the segment table entry. */ 1285 return pmd; 1286 } 1287 1288 static inline pmd_t pmd_mkold(pmd_t pmd) 1289 { 1290 /* No referenced bit in the segment table entry. */ 1291 return pmd; 1292 } 1293 1294 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1295 { 1296 /* No referenced bit in the segment table entry. */ 1297 return pmd; 1298 } 1299 1300 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1301 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1302 unsigned long address, pmd_t *pmdp) 1303 { 1304 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK; 1305 long tmp, rc; 1306 int counter; 1307 1308 rc = 0; 1309 if (MACHINE_HAS_RRBM) { 1310 counter = PTRS_PER_PTE >> 6; 1311 asm volatile( 1312 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */ 1313 " ogr %1,%0\n" 1314 " la %3,0(%4,%3)\n" 1315 " brct %2,0b\n" 1316 : "=&d" (tmp), "+&d" (rc), "+d" (counter), 1317 "+a" (pmd_addr) 1318 : "a" (64 * 4096UL) : "cc"); 1319 rc = !!rc; 1320 } else { 1321 counter = PTRS_PER_PTE; 1322 asm volatile( 1323 "0: rrbe 0,%2\n" 1324 " la %2,0(%3,%2)\n" 1325 " brc 12,1f\n" 1326 " lhi %0,1\n" 1327 "1: brct %1,0b\n" 1328 : "+d" (rc), "+d" (counter), "+a" (pmd_addr) 1329 : "a" (4096UL) : "cc"); 1330 } 1331 return rc; 1332 } 1333 1334 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1335 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1336 unsigned long address, pmd_t *pmdp) 1337 { 1338 pmd_t pmd = *pmdp; 1339 1340 __pmd_idte(address, pmdp); 1341 pmd_clear(pmdp); 1342 return pmd; 1343 } 1344 1345 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1346 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1347 unsigned long address, pmd_t *pmdp) 1348 { 1349 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1350 } 1351 1352 #define __HAVE_ARCH_PMDP_INVALIDATE 1353 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1354 unsigned long address, pmd_t *pmdp) 1355 { 1356 __pmd_idte(address, pmdp); 1357 } 1358 1359 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1360 { 1361 pmd_t __pmd; 1362 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1363 return __pmd; 1364 } 1365 1366 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1367 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1368 1369 static inline int pmd_trans_huge(pmd_t pmd) 1370 { 1371 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1372 } 1373 1374 static inline int has_transparent_hugepage(void) 1375 { 1376 return MACHINE_HAS_HPAGE ? 1 : 0; 1377 } 1378 1379 static inline unsigned long pmd_pfn(pmd_t pmd) 1380 { 1381 if (pmd_trans_huge(pmd)) 1382 return pmd_val(pmd) >> HPAGE_SHIFT; 1383 else 1384 return pmd_val(pmd) >> PAGE_SHIFT; 1385 } 1386 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1387 1388 /* 1389 * 31 bit swap entry format: 1390 * A page-table entry has some bits we have to treat in a special way. 1391 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1392 * exception will occur instead of a page translation exception. The 1393 * specifiation exception has the bad habit not to store necessary 1394 * information in the lowcore. 1395 * Bit 21 and bit 22 are the page invalid bit and the page protection 1396 * bit. We set both to indicate a swapped page. 1397 * Bit 30 and 31 are used to distinguish the different page types. For 1398 * a swapped page these bits need to be zero. 1399 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1400 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1401 * plus 24 for the offset. 1402 * 0| offset |0110|o|type |00| 1403 * 0 0000000001111111111 2222 2 22222 33 1404 * 0 1234567890123456789 0123 4 56789 01 1405 * 1406 * 64 bit swap entry format: 1407 * A page-table entry has some bits we have to treat in a special way. 1408 * Bits 52 and bit 55 have to be zero, otherwise an specification 1409 * exception will occur instead of a page translation exception. The 1410 * specifiation exception has the bad habit not to store necessary 1411 * information in the lowcore. 1412 * Bit 53 and bit 54 are the page invalid bit and the page protection 1413 * bit. We set both to indicate a swapped page. 1414 * Bit 62 and 63 are used to distinguish the different page types. For 1415 * a swapped page these bits need to be zero. 1416 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1417 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1418 * plus 56 for the offset. 1419 * | offset |0110|o|type |00| 1420 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1421 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1422 */ 1423 #ifndef CONFIG_64BIT 1424 #define __SWP_OFFSET_MASK (~0UL >> 12) 1425 #else 1426 #define __SWP_OFFSET_MASK (~0UL >> 11) 1427 #endif 1428 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1429 { 1430 pte_t pte; 1431 offset &= __SWP_OFFSET_MASK; 1432 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | 1433 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1434 return pte; 1435 } 1436 1437 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1438 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1439 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1440 1441 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1442 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1443 1444 #ifndef CONFIG_64BIT 1445 # define PTE_FILE_MAX_BITS 26 1446 #else /* CONFIG_64BIT */ 1447 # define PTE_FILE_MAX_BITS 59 1448 #endif /* CONFIG_64BIT */ 1449 1450 #define pte_to_pgoff(__pte) \ 1451 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1452 1453 #define pgoff_to_pte(__off) \ 1454 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1455 | _PAGE_TYPE_FILE }) 1456 1457 #endif /* !__ASSEMBLY__ */ 1458 1459 #define kern_addr_valid(addr) (1) 1460 1461 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1462 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1463 extern int s390_enable_sie(void); 1464 1465 /* 1466 * No page table caches to initialise 1467 */ 1468 #define pgtable_cache_init() do { } while (0) 1469 1470 #include <asm-generic/pgtable.h> 1471 1472 #endif /* _S390_PAGE_H */ 1473