1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/ctlreg.h> 22 #include <asm/bug.h> 23 #include <asm/page.h> 24 #include <asm/uv.h> 25 26 extern pgd_t swapper_pg_dir[]; 27 extern pgd_t invalid_pg_dir[]; 28 extern void paging_init(void); 29 extern struct ctlreg s390_invalid_asce; 30 31 enum { 32 PG_DIRECT_MAP_4K = 0, 33 PG_DIRECT_MAP_1M, 34 PG_DIRECT_MAP_2G, 35 PG_DIRECT_MAP_MAX 36 }; 37 38 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 39 40 static inline void update_page_count(int level, long count) 41 { 42 if (IS_ENABLED(CONFIG_PROC_FS)) 43 atomic_long_add(count, &direct_pages_count[level]); 44 } 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 52 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 53 54 /* 55 * ZERO_PAGE is a global shared page that is always zero; used 56 * for zero-mapped memory areas etc.. 57 */ 58 59 extern unsigned long empty_zero_page; 60 extern unsigned long zero_page_mask; 61 62 #define ZERO_PAGE(vaddr) \ 63 (virt_to_page((void *)(empty_zero_page + \ 64 (((unsigned long)(vaddr)) &zero_page_mask)))) 65 #define __HAVE_COLOR_ZERO_PAGE 66 67 /* TODO: s390 cannot support io_remap_pfn_range... */ 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 71 #define pmd_ERROR(e) \ 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 73 #define pud_ERROR(e) \ 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 75 #define p4d_ERROR(e) \ 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 77 #define pgd_ERROR(e) \ 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 79 80 /* 81 * The vmalloc and module area will always be on the topmost area of the 82 * kernel mapping. 512GB are reserved for vmalloc by default. 83 * At the top of the vmalloc area a 2GB area is reserved where modules 84 * will reside. That makes sure that inter module branches always 85 * happen without trampolines and in addition the placement within a 86 * 2GB frame is branch prediction unit friendly. 87 */ 88 extern unsigned long __bootdata_preserved(VMALLOC_START); 89 extern unsigned long __bootdata_preserved(VMALLOC_END); 90 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 91 extern struct page *__bootdata_preserved(vmemmap); 92 extern unsigned long __bootdata_preserved(vmemmap_size); 93 94 extern unsigned long __bootdata_preserved(MODULES_VADDR); 95 extern unsigned long __bootdata_preserved(MODULES_END); 96 #define MODULES_VADDR MODULES_VADDR 97 #define MODULES_END MODULES_END 98 #define MODULES_LEN (1UL << 31) 99 100 static inline int is_module_addr(void *addr) 101 { 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 103 if (addr < (void *)MODULES_VADDR) 104 return 0; 105 if (addr > (void *)MODULES_END) 106 return 0; 107 return 1; 108 } 109 110 #ifdef CONFIG_RANDOMIZE_BASE 111 #define KASLR_LEN (1UL << 31) 112 #else 113 #define KASLR_LEN 0UL 114 #endif 115 116 /* 117 * A 64 bit pagetable entry of S390 has following format: 118 * | PFRA |0IPC| OS | 119 * 0000000000111111111122222222223333333333444444444455555555556666 120 * 0123456789012345678901234567890123456789012345678901234567890123 121 * 122 * I Page-Invalid Bit: Page is not available for address-translation 123 * P Page-Protection Bit: Store access not possible for page 124 * C Change-bit override: HW is not required to set change bit 125 * 126 * A 64 bit segmenttable entry of S390 has following format: 127 * | P-table origin | TT 128 * 0000000000111111111122222222223333333333444444444455555555556666 129 * 0123456789012345678901234567890123456789012345678901234567890123 130 * 131 * I Segment-Invalid Bit: Segment is not available for address-translation 132 * C Common-Segment Bit: Segment is not private (PoP 3-30) 133 * P Page-Protection Bit: Store access not possible for page 134 * TT Type 00 135 * 136 * A 64 bit region table entry of S390 has following format: 137 * | S-table origin | TF TTTL 138 * 0000000000111111111122222222223333333333444444444455555555556666 139 * 0123456789012345678901234567890123456789012345678901234567890123 140 * 141 * I Segment-Invalid Bit: Segment is not available for address-translation 142 * TT Type 01 143 * TF 144 * TL Table length 145 * 146 * The 64 bit regiontable origin of S390 has following format: 147 * | region table origon | DTTL 148 * 0000000000111111111122222222223333333333444444444455555555556666 149 * 0123456789012345678901234567890123456789012345678901234567890123 150 * 151 * X Space-Switch event: 152 * G Segment-Invalid Bit: 153 * P Private-Space Bit: 154 * S Storage-Alteration: 155 * R Real space 156 * TL Table-Length: 157 * 158 * A storage key has the following format: 159 * | ACC |F|R|C|0| 160 * 0 3 4 5 6 7 161 * ACC: access key 162 * F : fetch protection bit 163 * R : referenced bit 164 * C : changed bit 165 */ 166 167 /* Hardware bits in the page table entry */ 168 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 169 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 170 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 171 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 172 173 /* Software bits in the page table entry */ 174 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 175 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 176 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 177 #define _PAGE_READ 0x010 /* SW pte read bit */ 178 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 179 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 180 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 181 182 #ifdef CONFIG_MEM_SOFT_DIRTY 183 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 184 #else 185 #define _PAGE_SOFT_DIRTY 0x000 186 #endif 187 188 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 189 190 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 191 192 /* Set of bits not changed in pte_modify */ 193 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 194 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 195 196 /* 197 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 198 * HW bit and all SW bits. 199 */ 200 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 201 202 /* 203 * handle_pte_fault uses pte_present and pte_none to find out the pte type 204 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 205 * distinguish present from not-present ptes. It is changed only with the page 206 * table lock held. 207 * 208 * The following table gives the different possible bit combinations for 209 * the pte hardware and software bits in the last 12 bits of a pte 210 * (. unassigned bit, x don't care, t swap type): 211 * 212 * 842100000000 213 * 000084210000 214 * 000000008421 215 * .IR.uswrdy.p 216 * empty .10.00000000 217 * swap .11..ttttt.0 218 * prot-none, clean, old .11.xx0000.1 219 * prot-none, clean, young .11.xx0001.1 220 * prot-none, dirty, old .11.xx0010.1 221 * prot-none, dirty, young .11.xx0011.1 222 * read-only, clean, old .11.xx0100.1 223 * read-only, clean, young .01.xx0101.1 224 * read-only, dirty, old .11.xx0110.1 225 * read-only, dirty, young .01.xx0111.1 226 * read-write, clean, old .11.xx1100.1 227 * read-write, clean, young .01.xx1101.1 228 * read-write, dirty, old .10.xx1110.1 229 * read-write, dirty, young .00.xx1111.1 230 * HW-bits: R read-only, I invalid 231 * SW-bits: p present, y young, d dirty, r read, w write, s special, 232 * u unused, l large 233 * 234 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 235 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 236 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 237 */ 238 239 /* Bits in the segment/region table address-space-control-element */ 240 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 241 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 242 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 243 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 244 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 245 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 246 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 247 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 248 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 249 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 250 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 251 252 /* Bits in the region table entry */ 253 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 254 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 255 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 256 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 257 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 258 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 259 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 260 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 261 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 262 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 263 264 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 265 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 266 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 267 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 268 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 269 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 270 271 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 272 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 273 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 274 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 275 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 276 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 277 278 #ifdef CONFIG_MEM_SOFT_DIRTY 279 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 280 #else 281 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 282 #endif 283 284 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 285 286 /* Bits in the segment table entry */ 287 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 288 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 289 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 290 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 291 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 292 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 293 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 294 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 295 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 296 297 #define _SEGMENT_ENTRY (0) 298 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 299 300 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 301 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 302 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 303 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 304 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 305 306 #ifdef CONFIG_MEM_SOFT_DIRTY 307 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 308 #else 309 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 310 #endif 311 312 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 313 #define _PAGE_ENTRIES 256 /* number of page table entries */ 314 315 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 316 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 317 318 #define _REGION1_SHIFT 53 319 #define _REGION2_SHIFT 42 320 #define _REGION3_SHIFT 31 321 #define _SEGMENT_SHIFT 20 322 323 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 324 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 325 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 326 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 327 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 328 329 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 330 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 331 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 332 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 333 334 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 335 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 336 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 337 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 338 339 #define PMD_SHIFT _SEGMENT_SHIFT 340 #define PUD_SHIFT _REGION3_SHIFT 341 #define P4D_SHIFT _REGION2_SHIFT 342 #define PGDIR_SHIFT _REGION1_SHIFT 343 344 #define PMD_SIZE _SEGMENT_SIZE 345 #define PUD_SIZE _REGION3_SIZE 346 #define P4D_SIZE _REGION2_SIZE 347 #define PGDIR_SIZE _REGION1_SIZE 348 349 #define PMD_MASK _SEGMENT_MASK 350 #define PUD_MASK _REGION3_MASK 351 #define P4D_MASK _REGION2_MASK 352 #define PGDIR_MASK _REGION1_MASK 353 354 #define PTRS_PER_PTE _PAGE_ENTRIES 355 #define PTRS_PER_PMD _CRST_ENTRIES 356 #define PTRS_PER_PUD _CRST_ENTRIES 357 #define PTRS_PER_P4D _CRST_ENTRIES 358 #define PTRS_PER_PGD _CRST_ENTRIES 359 360 /* 361 * Segment table and region3 table entry encoding 362 * (R = read-only, I = invalid, y = young bit): 363 * dy..R...I...wr 364 * prot-none, clean, old 00..1...1...00 365 * prot-none, clean, young 01..1...1...00 366 * prot-none, dirty, old 10..1...1...00 367 * prot-none, dirty, young 11..1...1...00 368 * read-only, clean, old 00..1...1...01 369 * read-only, clean, young 01..1...0...01 370 * read-only, dirty, old 10..1...1...01 371 * read-only, dirty, young 11..1...0...01 372 * read-write, clean, old 00..1...1...11 373 * read-write, clean, young 01..1...0...11 374 * read-write, dirty, old 10..0...1...11 375 * read-write, dirty, young 11..0...0...11 376 * The segment table origin is used to distinguish empty (origin==0) from 377 * read-write, old segment table entries (origin!=0) 378 * HW-bits: R read-only, I invalid 379 * SW-bits: y young, d dirty, r read, w write 380 */ 381 382 /* Page status table bits for virtualization */ 383 #define PGSTE_ACC_BITS 0xf000000000000000UL 384 #define PGSTE_FP_BIT 0x0800000000000000UL 385 #define PGSTE_PCL_BIT 0x0080000000000000UL 386 #define PGSTE_HR_BIT 0x0040000000000000UL 387 #define PGSTE_HC_BIT 0x0020000000000000UL 388 #define PGSTE_GR_BIT 0x0004000000000000UL 389 #define PGSTE_GC_BIT 0x0002000000000000UL 390 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 391 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 392 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 393 394 /* Guest Page State used for virtualization */ 395 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 396 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 397 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 398 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 399 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 400 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 401 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 402 403 /* 404 * A user page table pointer has the space-switch-event bit, the 405 * private-space-control bit and the storage-alteration-event-control 406 * bit set. A kernel page table pointer doesn't need them. 407 */ 408 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 409 _ASCE_ALT_EVENT) 410 411 /* 412 * Page protection definitions. 413 */ 414 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 415 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 416 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 417 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 418 _PAGE_INVALID | _PAGE_PROTECT) 419 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 420 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 421 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 422 _PAGE_INVALID | _PAGE_PROTECT) 423 424 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 425 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 426 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 427 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 428 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 429 _PAGE_PROTECT | _PAGE_NOEXEC) 430 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 431 _PAGE_YOUNG | _PAGE_DIRTY) 432 433 /* 434 * On s390 the page table entry has an invalid bit and a read-only bit. 435 * Read permission implies execute permission and write permission 436 * implies read permission. 437 */ 438 /*xwr*/ 439 440 /* 441 * Segment entry (large page) protection definitions. 442 */ 443 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 444 _SEGMENT_ENTRY_PROTECT) 445 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 446 _SEGMENT_ENTRY_READ | \ 447 _SEGMENT_ENTRY_NOEXEC) 448 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 449 _SEGMENT_ENTRY_READ) 450 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_WRITE | \ 452 _SEGMENT_ENTRY_NOEXEC) 453 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 454 _SEGMENT_ENTRY_WRITE) 455 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 456 _SEGMENT_ENTRY_LARGE | \ 457 _SEGMENT_ENTRY_READ | \ 458 _SEGMENT_ENTRY_WRITE | \ 459 _SEGMENT_ENTRY_YOUNG | \ 460 _SEGMENT_ENTRY_DIRTY | \ 461 _SEGMENT_ENTRY_NOEXEC) 462 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 463 _SEGMENT_ENTRY_LARGE | \ 464 _SEGMENT_ENTRY_READ | \ 465 _SEGMENT_ENTRY_YOUNG | \ 466 _SEGMENT_ENTRY_PROTECT | \ 467 _SEGMENT_ENTRY_NOEXEC) 468 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 469 _SEGMENT_ENTRY_LARGE | \ 470 _SEGMENT_ENTRY_READ | \ 471 _SEGMENT_ENTRY_WRITE | \ 472 _SEGMENT_ENTRY_YOUNG | \ 473 _SEGMENT_ENTRY_DIRTY) 474 475 /* 476 * Region3 entry (large page) protection definitions. 477 */ 478 479 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 480 _REGION3_ENTRY_LARGE | \ 481 _REGION3_ENTRY_READ | \ 482 _REGION3_ENTRY_WRITE | \ 483 _REGION3_ENTRY_YOUNG | \ 484 _REGION3_ENTRY_DIRTY | \ 485 _REGION_ENTRY_NOEXEC) 486 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 487 _REGION3_ENTRY_LARGE | \ 488 _REGION3_ENTRY_READ | \ 489 _REGION3_ENTRY_YOUNG | \ 490 _REGION_ENTRY_PROTECT | \ 491 _REGION_ENTRY_NOEXEC) 492 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 493 _REGION3_ENTRY_LARGE | \ 494 _REGION3_ENTRY_READ | \ 495 _REGION3_ENTRY_WRITE | \ 496 _REGION3_ENTRY_YOUNG | \ 497 _REGION3_ENTRY_DIRTY) 498 499 static inline bool mm_p4d_folded(struct mm_struct *mm) 500 { 501 return mm->context.asce_limit <= _REGION1_SIZE; 502 } 503 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 504 505 static inline bool mm_pud_folded(struct mm_struct *mm) 506 { 507 return mm->context.asce_limit <= _REGION2_SIZE; 508 } 509 #define mm_pud_folded(mm) mm_pud_folded(mm) 510 511 static inline bool mm_pmd_folded(struct mm_struct *mm) 512 { 513 return mm->context.asce_limit <= _REGION3_SIZE; 514 } 515 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 516 517 static inline int mm_has_pgste(struct mm_struct *mm) 518 { 519 #ifdef CONFIG_PGSTE 520 if (unlikely(mm->context.has_pgste)) 521 return 1; 522 #endif 523 return 0; 524 } 525 526 static inline int mm_is_protected(struct mm_struct *mm) 527 { 528 #ifdef CONFIG_PGSTE 529 if (unlikely(atomic_read(&mm->context.protected_count))) 530 return 1; 531 #endif 532 return 0; 533 } 534 535 static inline int mm_alloc_pgste(struct mm_struct *mm) 536 { 537 #ifdef CONFIG_PGSTE 538 if (unlikely(mm->context.alloc_pgste)) 539 return 1; 540 #endif 541 return 0; 542 } 543 544 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 545 { 546 return __pte(pte_val(pte) & ~pgprot_val(prot)); 547 } 548 549 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 550 { 551 return __pte(pte_val(pte) | pgprot_val(prot)); 552 } 553 554 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 555 { 556 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 557 } 558 559 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 560 { 561 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 562 } 563 564 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 565 { 566 return __pud(pud_val(pud) & ~pgprot_val(prot)); 567 } 568 569 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 570 { 571 return __pud(pud_val(pud) | pgprot_val(prot)); 572 } 573 574 /* 575 * In the case that a guest uses storage keys 576 * faults should no longer be backed by zero pages 577 */ 578 #define mm_forbids_zeropage mm_has_pgste 579 static inline int mm_uses_skeys(struct mm_struct *mm) 580 { 581 #ifdef CONFIG_PGSTE 582 if (mm->context.uses_skeys) 583 return 1; 584 #endif 585 return 0; 586 } 587 588 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 589 { 590 union register_pair r1 = { .even = old, .odd = new, }; 591 unsigned long address = (unsigned long)ptr | 1; 592 593 asm volatile( 594 " csp %[r1],%[address]" 595 : [r1] "+&d" (r1.pair), "+m" (*ptr) 596 : [address] "d" (address) 597 : "cc"); 598 } 599 600 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 601 { 602 union register_pair r1 = { .even = old, .odd = new, }; 603 unsigned long address = (unsigned long)ptr | 1; 604 605 asm volatile( 606 " cspg %[r1],%[address]" 607 : [r1] "+&d" (r1.pair), "+m" (*ptr) 608 : [address] "d" (address) 609 : "cc"); 610 } 611 612 #define CRDTE_DTT_PAGE 0x00UL 613 #define CRDTE_DTT_SEGMENT 0x10UL 614 #define CRDTE_DTT_REGION3 0x14UL 615 #define CRDTE_DTT_REGION2 0x18UL 616 #define CRDTE_DTT_REGION1 0x1cUL 617 618 static inline void crdte(unsigned long old, unsigned long new, 619 unsigned long *table, unsigned long dtt, 620 unsigned long address, unsigned long asce) 621 { 622 union register_pair r1 = { .even = old, .odd = new, }; 623 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 624 625 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 626 : [r1] "+&d" (r1.pair) 627 : [r2] "d" (r2.pair), [asce] "a" (asce) 628 : "memory", "cc"); 629 } 630 631 /* 632 * pgd/p4d/pud/pmd/pte query functions 633 */ 634 static inline int pgd_folded(pgd_t pgd) 635 { 636 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 637 } 638 639 static inline int pgd_present(pgd_t pgd) 640 { 641 if (pgd_folded(pgd)) 642 return 1; 643 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 644 } 645 646 static inline int pgd_none(pgd_t pgd) 647 { 648 if (pgd_folded(pgd)) 649 return 0; 650 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 651 } 652 653 static inline int pgd_bad(pgd_t pgd) 654 { 655 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 656 return 0; 657 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 658 } 659 660 static inline unsigned long pgd_pfn(pgd_t pgd) 661 { 662 unsigned long origin_mask; 663 664 origin_mask = _REGION_ENTRY_ORIGIN; 665 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 666 } 667 668 static inline int p4d_folded(p4d_t p4d) 669 { 670 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 671 } 672 673 static inline int p4d_present(p4d_t p4d) 674 { 675 if (p4d_folded(p4d)) 676 return 1; 677 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 678 } 679 680 static inline int p4d_none(p4d_t p4d) 681 { 682 if (p4d_folded(p4d)) 683 return 0; 684 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 685 } 686 687 static inline unsigned long p4d_pfn(p4d_t p4d) 688 { 689 unsigned long origin_mask; 690 691 origin_mask = _REGION_ENTRY_ORIGIN; 692 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 693 } 694 695 static inline int pud_folded(pud_t pud) 696 { 697 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 698 } 699 700 static inline int pud_present(pud_t pud) 701 { 702 if (pud_folded(pud)) 703 return 1; 704 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 705 } 706 707 static inline int pud_none(pud_t pud) 708 { 709 if (pud_folded(pud)) 710 return 0; 711 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 712 } 713 714 #define pud_leaf pud_leaf 715 static inline bool pud_leaf(pud_t pud) 716 { 717 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 718 return 0; 719 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 720 } 721 722 #define pmd_leaf pmd_leaf 723 static inline bool pmd_leaf(pmd_t pmd) 724 { 725 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 726 } 727 728 static inline int pmd_bad(pmd_t pmd) 729 { 730 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 731 return 1; 732 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 733 } 734 735 static inline int pud_bad(pud_t pud) 736 { 737 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 738 739 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 740 return 1; 741 if (type < _REGION_ENTRY_TYPE_R3) 742 return 0; 743 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 744 } 745 746 static inline int p4d_bad(p4d_t p4d) 747 { 748 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 749 750 if (type > _REGION_ENTRY_TYPE_R2) 751 return 1; 752 if (type < _REGION_ENTRY_TYPE_R2) 753 return 0; 754 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 755 } 756 757 static inline int pmd_present(pmd_t pmd) 758 { 759 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 760 } 761 762 static inline int pmd_none(pmd_t pmd) 763 { 764 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 765 } 766 767 #define pmd_write pmd_write 768 static inline int pmd_write(pmd_t pmd) 769 { 770 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 771 } 772 773 #define pud_write pud_write 774 static inline int pud_write(pud_t pud) 775 { 776 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 777 } 778 779 #define pmd_dirty pmd_dirty 780 static inline int pmd_dirty(pmd_t pmd) 781 { 782 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 783 } 784 785 #define pmd_young pmd_young 786 static inline int pmd_young(pmd_t pmd) 787 { 788 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 789 } 790 791 static inline int pte_present(pte_t pte) 792 { 793 /* Bit pattern: (pte & 0x001) == 0x001 */ 794 return (pte_val(pte) & _PAGE_PRESENT) != 0; 795 } 796 797 static inline int pte_none(pte_t pte) 798 { 799 /* Bit pattern: pte == 0x400 */ 800 return pte_val(pte) == _PAGE_INVALID; 801 } 802 803 static inline int pte_swap(pte_t pte) 804 { 805 /* Bit pattern: (pte & 0x201) == 0x200 */ 806 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 807 == _PAGE_PROTECT; 808 } 809 810 static inline int pte_special(pte_t pte) 811 { 812 return (pte_val(pte) & _PAGE_SPECIAL); 813 } 814 815 #define __HAVE_ARCH_PTE_SAME 816 static inline int pte_same(pte_t a, pte_t b) 817 { 818 return pte_val(a) == pte_val(b); 819 } 820 821 #ifdef CONFIG_NUMA_BALANCING 822 static inline int pte_protnone(pte_t pte) 823 { 824 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 825 } 826 827 static inline int pmd_protnone(pmd_t pmd) 828 { 829 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 830 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 831 } 832 #endif 833 834 static inline int pte_swp_exclusive(pte_t pte) 835 { 836 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 837 } 838 839 static inline pte_t pte_swp_mkexclusive(pte_t pte) 840 { 841 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 842 } 843 844 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 845 { 846 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 847 } 848 849 static inline int pte_soft_dirty(pte_t pte) 850 { 851 return pte_val(pte) & _PAGE_SOFT_DIRTY; 852 } 853 #define pte_swp_soft_dirty pte_soft_dirty 854 855 static inline pte_t pte_mksoft_dirty(pte_t pte) 856 { 857 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 858 } 859 #define pte_swp_mksoft_dirty pte_mksoft_dirty 860 861 static inline pte_t pte_clear_soft_dirty(pte_t pte) 862 { 863 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 864 } 865 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 866 867 static inline int pmd_soft_dirty(pmd_t pmd) 868 { 869 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 870 } 871 872 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 873 { 874 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 875 } 876 877 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 878 { 879 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 880 } 881 882 /* 883 * query functions pte_write/pte_dirty/pte_young only work if 884 * pte_present() is true. Undefined behaviour if not.. 885 */ 886 static inline int pte_write(pte_t pte) 887 { 888 return (pte_val(pte) & _PAGE_WRITE) != 0; 889 } 890 891 static inline int pte_dirty(pte_t pte) 892 { 893 return (pte_val(pte) & _PAGE_DIRTY) != 0; 894 } 895 896 static inline int pte_young(pte_t pte) 897 { 898 return (pte_val(pte) & _PAGE_YOUNG) != 0; 899 } 900 901 #define __HAVE_ARCH_PTE_UNUSED 902 static inline int pte_unused(pte_t pte) 903 { 904 return pte_val(pte) & _PAGE_UNUSED; 905 } 906 907 /* 908 * Extract the pgprot value from the given pte while at the same time making it 909 * usable for kernel address space mappings where fault driven dirty and 910 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 911 * must not be set. 912 */ 913 static inline pgprot_t pte_pgprot(pte_t pte) 914 { 915 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 916 917 if (pte_write(pte)) 918 pte_flags |= pgprot_val(PAGE_KERNEL); 919 else 920 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 921 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 922 923 return __pgprot(pte_flags); 924 } 925 926 /* 927 * pgd/pmd/pte modification functions 928 */ 929 930 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 931 { 932 WRITE_ONCE(*pgdp, pgd); 933 } 934 935 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 936 { 937 WRITE_ONCE(*p4dp, p4d); 938 } 939 940 static inline void set_pud(pud_t *pudp, pud_t pud) 941 { 942 WRITE_ONCE(*pudp, pud); 943 } 944 945 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 946 { 947 WRITE_ONCE(*pmdp, pmd); 948 } 949 950 static inline void set_pte(pte_t *ptep, pte_t pte) 951 { 952 WRITE_ONCE(*ptep, pte); 953 } 954 955 static inline void pgd_clear(pgd_t *pgd) 956 { 957 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 958 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 959 } 960 961 static inline void p4d_clear(p4d_t *p4d) 962 { 963 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 964 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 965 } 966 967 static inline void pud_clear(pud_t *pud) 968 { 969 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 970 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 971 } 972 973 static inline void pmd_clear(pmd_t *pmdp) 974 { 975 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 976 } 977 978 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 979 { 980 set_pte(ptep, __pte(_PAGE_INVALID)); 981 } 982 983 /* 984 * The following pte modification functions only work if 985 * pte_present() is true. Undefined behaviour if not.. 986 */ 987 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 988 { 989 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 990 pte = set_pte_bit(pte, newprot); 991 /* 992 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 993 * has the invalid bit set, clear it again for readable, young pages 994 */ 995 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 996 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 997 /* 998 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 999 * protection bit set, clear it again for writable, dirty pages 1000 */ 1001 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1002 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1003 return pte; 1004 } 1005 1006 static inline pte_t pte_wrprotect(pte_t pte) 1007 { 1008 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1009 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1010 } 1011 1012 static inline pte_t pte_mkwrite_novma(pte_t pte) 1013 { 1014 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1015 if (pte_val(pte) & _PAGE_DIRTY) 1016 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1017 return pte; 1018 } 1019 1020 static inline pte_t pte_mkclean(pte_t pte) 1021 { 1022 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1023 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1024 } 1025 1026 static inline pte_t pte_mkdirty(pte_t pte) 1027 { 1028 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1029 if (pte_val(pte) & _PAGE_WRITE) 1030 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1031 return pte; 1032 } 1033 1034 static inline pte_t pte_mkold(pte_t pte) 1035 { 1036 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1037 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1038 } 1039 1040 static inline pte_t pte_mkyoung(pte_t pte) 1041 { 1042 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1043 if (pte_val(pte) & _PAGE_READ) 1044 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1045 return pte; 1046 } 1047 1048 static inline pte_t pte_mkspecial(pte_t pte) 1049 { 1050 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1051 } 1052 1053 #ifdef CONFIG_HUGETLB_PAGE 1054 static inline pte_t pte_mkhuge(pte_t pte) 1055 { 1056 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1057 } 1058 #endif 1059 1060 #define IPTE_GLOBAL 0 1061 #define IPTE_LOCAL 1 1062 1063 #define IPTE_NODAT 0x400 1064 #define IPTE_GUEST_ASCE 0x800 1065 1066 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1067 unsigned long opt, unsigned long asce, 1068 int local) 1069 { 1070 unsigned long pto; 1071 1072 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1073 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1074 : "+m" (*ptep) 1075 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1076 [asce] "a" (asce), [m4] "i" (local)); 1077 } 1078 1079 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1080 unsigned long opt, unsigned long asce, 1081 int local) 1082 { 1083 unsigned long pto = __pa(ptep); 1084 1085 if (__builtin_constant_p(opt) && opt == 0) { 1086 /* Invalidation + TLB flush for the pte */ 1087 asm volatile( 1088 " ipte %[r1],%[r2],0,%[m4]" 1089 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1090 [m4] "i" (local)); 1091 return; 1092 } 1093 1094 /* Invalidate ptes with options + TLB flush of the ptes */ 1095 opt = opt | (asce & _ASCE_ORIGIN); 1096 asm volatile( 1097 " ipte %[r1],%[r2],%[r3],%[m4]" 1098 : [r2] "+a" (address), [r3] "+a" (opt) 1099 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1100 } 1101 1102 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1103 pte_t *ptep, int local) 1104 { 1105 unsigned long pto = __pa(ptep); 1106 1107 /* Invalidate a range of ptes + TLB flush of the ptes */ 1108 do { 1109 asm volatile( 1110 " ipte %[r1],%[r2],%[r3],%[m4]" 1111 : [r2] "+a" (address), [r3] "+a" (nr) 1112 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1113 } while (nr != 255); 1114 } 1115 1116 /* 1117 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1118 * both clear the TLB for the unmapped pte. The reason is that 1119 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1120 * to modify an active pte. The sequence is 1121 * 1) ptep_get_and_clear 1122 * 2) set_pte_at 1123 * 3) flush_tlb_range 1124 * On s390 the tlb needs to get flushed with the modification of the pte 1125 * if the pte is active. The only way how this can be implemented is to 1126 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1127 * is a nop. 1128 */ 1129 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1130 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1131 1132 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1133 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1134 unsigned long addr, pte_t *ptep) 1135 { 1136 pte_t pte = *ptep; 1137 1138 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1139 return pte_young(pte); 1140 } 1141 1142 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1143 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1144 unsigned long address, pte_t *ptep) 1145 { 1146 return ptep_test_and_clear_young(vma, address, ptep); 1147 } 1148 1149 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1150 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1151 unsigned long addr, pte_t *ptep) 1152 { 1153 pte_t res; 1154 1155 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1156 /* At this point the reference through the mapping is still present */ 1157 if (mm_is_protected(mm) && pte_present(res)) 1158 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1159 return res; 1160 } 1161 1162 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1163 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1164 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1165 pte_t *, pte_t, pte_t); 1166 1167 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1168 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1169 unsigned long addr, pte_t *ptep) 1170 { 1171 pte_t res; 1172 1173 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1174 /* At this point the reference through the mapping is still present */ 1175 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1176 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1177 return res; 1178 } 1179 1180 /* 1181 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1182 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1183 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1184 * cannot be accessed while the batched unmap is running. In this case 1185 * full==1 and a simple pte_clear is enough. See tlb.h. 1186 */ 1187 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1188 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1189 unsigned long addr, 1190 pte_t *ptep, int full) 1191 { 1192 pte_t res; 1193 1194 if (full) { 1195 res = *ptep; 1196 set_pte(ptep, __pte(_PAGE_INVALID)); 1197 } else { 1198 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1199 } 1200 /* Nothing to do */ 1201 if (!mm_is_protected(mm) || !pte_present(res)) 1202 return res; 1203 /* 1204 * At this point the reference through the mapping is still present. 1205 * The notifier should have destroyed all protected vCPUs at this 1206 * point, so the destroy should be successful. 1207 */ 1208 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1209 return res; 1210 /* 1211 * If something went wrong and the page could not be destroyed, or 1212 * if this is not a mm teardown, the slower export is used as 1213 * fallback instead. 1214 */ 1215 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1216 return res; 1217 } 1218 1219 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1220 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1221 unsigned long addr, pte_t *ptep) 1222 { 1223 pte_t pte = *ptep; 1224 1225 if (pte_write(pte)) 1226 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1227 } 1228 1229 /* 1230 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1231 * bits in the comparison. Those might change e.g. because of dirty and young 1232 * tracking. 1233 */ 1234 static inline int pte_allow_rdp(pte_t old, pte_t new) 1235 { 1236 /* 1237 * Only allow changes from RO to RW 1238 */ 1239 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1240 return 0; 1241 1242 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1243 } 1244 1245 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1246 unsigned long address, 1247 pte_t *ptep) 1248 { 1249 /* 1250 * RDP might not have propagated the PTE protection reset to all CPUs, 1251 * so there could be spurious TLB protection faults. 1252 * NOTE: This will also be called when a racing pagetable update on 1253 * another thread already installed the correct PTE. Both cases cannot 1254 * really be distinguished. 1255 * Therefore, only do the local TLB flush when RDP can be used, and the 1256 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1257 * A local RDP can be used to do the flush. 1258 */ 1259 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1260 __ptep_rdp(address, ptep, 0, 0, 1); 1261 } 1262 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1263 1264 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1265 pte_t new); 1266 1267 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1268 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1269 unsigned long addr, pte_t *ptep, 1270 pte_t entry, int dirty) 1271 { 1272 if (pte_same(*ptep, entry)) 1273 return 0; 1274 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1275 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1276 else 1277 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1278 return 1; 1279 } 1280 1281 /* 1282 * Additional functions to handle KVM guest page tables 1283 */ 1284 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1285 pte_t *ptep, pte_t entry); 1286 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1287 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1288 pte_t *ptep, unsigned long bits); 1289 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1290 pte_t *ptep, int prot, unsigned long bit); 1291 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1292 pte_t *ptep , int reset); 1293 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1294 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1295 pte_t *sptep, pte_t *tptep, pte_t pte); 1296 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1297 1298 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1299 pte_t *ptep); 1300 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1301 unsigned char key, bool nq); 1302 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1303 unsigned char key, unsigned char *oldkey, 1304 bool nq, bool mr, bool mc); 1305 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1306 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1307 unsigned char *key); 1308 1309 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1310 unsigned long bits, unsigned long value); 1311 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1312 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1313 unsigned long *oldpte, unsigned long *oldpgste); 1314 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1315 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1316 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1317 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1318 1319 #define pgprot_writecombine pgprot_writecombine 1320 pgprot_t pgprot_writecombine(pgprot_t prot); 1321 1322 #define pgprot_writethrough pgprot_writethrough 1323 pgprot_t pgprot_writethrough(pgprot_t prot); 1324 1325 #define PFN_PTE_SHIFT PAGE_SHIFT 1326 1327 /* 1328 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1329 * are within the same folio, PMD and VMA. 1330 */ 1331 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1332 pte_t *ptep, pte_t entry, unsigned int nr) 1333 { 1334 if (pte_present(entry)) 1335 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1336 if (mm_has_pgste(mm)) { 1337 for (;;) { 1338 ptep_set_pte_at(mm, addr, ptep, entry); 1339 if (--nr == 0) 1340 break; 1341 ptep++; 1342 entry = __pte(pte_val(entry) + PAGE_SIZE); 1343 addr += PAGE_SIZE; 1344 } 1345 } else { 1346 for (;;) { 1347 set_pte(ptep, entry); 1348 if (--nr == 0) 1349 break; 1350 ptep++; 1351 entry = __pte(pte_val(entry) + PAGE_SIZE); 1352 } 1353 } 1354 } 1355 #define set_ptes set_ptes 1356 1357 /* 1358 * Conversion functions: convert a page and protection to a page entry, 1359 * and a page entry and page directory to the page they refer to. 1360 */ 1361 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1362 { 1363 pte_t __pte; 1364 1365 __pte = __pte(physpage | pgprot_val(pgprot)); 1366 if (!MACHINE_HAS_NX) 1367 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1368 return pte_mkyoung(__pte); 1369 } 1370 1371 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1372 { 1373 unsigned long physpage = page_to_phys(page); 1374 pte_t __pte = mk_pte_phys(physpage, pgprot); 1375 1376 if (pte_write(__pte) && PageDirty(page)) 1377 __pte = pte_mkdirty(__pte); 1378 return __pte; 1379 } 1380 1381 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1382 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1383 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1384 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1385 1386 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1387 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1388 1389 static inline unsigned long pmd_deref(pmd_t pmd) 1390 { 1391 unsigned long origin_mask; 1392 1393 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1394 if (pmd_leaf(pmd)) 1395 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1396 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1397 } 1398 1399 static inline unsigned long pmd_pfn(pmd_t pmd) 1400 { 1401 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1402 } 1403 1404 static inline unsigned long pud_deref(pud_t pud) 1405 { 1406 unsigned long origin_mask; 1407 1408 origin_mask = _REGION_ENTRY_ORIGIN; 1409 if (pud_leaf(pud)) 1410 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1411 return (unsigned long)__va(pud_val(pud) & origin_mask); 1412 } 1413 1414 static inline unsigned long pud_pfn(pud_t pud) 1415 { 1416 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1417 } 1418 1419 /* 1420 * The pgd_offset function *always* adds the index for the top-level 1421 * region/segment table. This is done to get a sequence like the 1422 * following to work: 1423 * pgdp = pgd_offset(current->mm, addr); 1424 * pgd = READ_ONCE(*pgdp); 1425 * p4dp = p4d_offset(&pgd, addr); 1426 * ... 1427 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1428 * only add an index if they dereferenced the pointer. 1429 */ 1430 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1431 { 1432 unsigned long rste; 1433 unsigned int shift; 1434 1435 /* Get the first entry of the top level table */ 1436 rste = pgd_val(*pgd); 1437 /* Pick up the shift from the table type of the first entry */ 1438 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1439 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1440 } 1441 1442 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1443 1444 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1445 { 1446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1447 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1448 return (p4d_t *) pgdp; 1449 } 1450 #define p4d_offset_lockless p4d_offset_lockless 1451 1452 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1453 { 1454 return p4d_offset_lockless(pgdp, *pgdp, address); 1455 } 1456 1457 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1458 { 1459 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1460 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1461 return (pud_t *) p4dp; 1462 } 1463 #define pud_offset_lockless pud_offset_lockless 1464 1465 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1466 { 1467 return pud_offset_lockless(p4dp, *p4dp, address); 1468 } 1469 #define pud_offset pud_offset 1470 1471 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1472 { 1473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1474 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1475 return (pmd_t *) pudp; 1476 } 1477 #define pmd_offset_lockless pmd_offset_lockless 1478 1479 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1480 { 1481 return pmd_offset_lockless(pudp, *pudp, address); 1482 } 1483 #define pmd_offset pmd_offset 1484 1485 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1486 { 1487 return (unsigned long) pmd_deref(pmd); 1488 } 1489 1490 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1491 { 1492 return end <= current->mm->context.asce_limit; 1493 } 1494 #define gup_fast_permitted gup_fast_permitted 1495 1496 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1497 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1498 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1499 1500 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1501 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1502 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1503 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1504 1505 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1506 { 1507 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1508 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1509 } 1510 1511 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1512 { 1513 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1514 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1515 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1516 return pmd; 1517 } 1518 1519 static inline pmd_t pmd_mkclean(pmd_t pmd) 1520 { 1521 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1522 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1523 } 1524 1525 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1526 { 1527 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1528 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1529 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1530 return pmd; 1531 } 1532 1533 static inline pud_t pud_wrprotect(pud_t pud) 1534 { 1535 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1536 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1537 } 1538 1539 static inline pud_t pud_mkwrite(pud_t pud) 1540 { 1541 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1542 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1543 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1544 return pud; 1545 } 1546 1547 static inline pud_t pud_mkclean(pud_t pud) 1548 { 1549 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1550 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1551 } 1552 1553 static inline pud_t pud_mkdirty(pud_t pud) 1554 { 1555 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1556 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1557 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1558 return pud; 1559 } 1560 1561 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1562 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1563 { 1564 /* 1565 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1566 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1567 */ 1568 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1569 return pgprot_val(SEGMENT_NONE); 1570 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1571 return pgprot_val(SEGMENT_RO); 1572 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1573 return pgprot_val(SEGMENT_RX); 1574 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1575 return pgprot_val(SEGMENT_RW); 1576 return pgprot_val(SEGMENT_RWX); 1577 } 1578 1579 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1580 { 1581 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1582 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1583 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1584 return pmd; 1585 } 1586 1587 static inline pmd_t pmd_mkold(pmd_t pmd) 1588 { 1589 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1590 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1591 } 1592 1593 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1594 { 1595 unsigned long mask; 1596 1597 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1598 mask |= _SEGMENT_ENTRY_DIRTY; 1599 mask |= _SEGMENT_ENTRY_YOUNG; 1600 mask |= _SEGMENT_ENTRY_LARGE; 1601 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1602 pmd = __pmd(pmd_val(pmd) & mask); 1603 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1604 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1605 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1606 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1607 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1608 return pmd; 1609 } 1610 1611 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1612 { 1613 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1614 } 1615 1616 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1617 1618 static inline void __pmdp_csp(pmd_t *pmdp) 1619 { 1620 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1621 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1622 } 1623 1624 #define IDTE_GLOBAL 0 1625 #define IDTE_LOCAL 1 1626 1627 #define IDTE_PTOA 0x0800 1628 #define IDTE_NODAT 0x1000 1629 #define IDTE_GUEST_ASCE 0x2000 1630 1631 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1632 unsigned long opt, unsigned long asce, 1633 int local) 1634 { 1635 unsigned long sto; 1636 1637 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1638 if (__builtin_constant_p(opt) && opt == 0) { 1639 /* flush without guest asce */ 1640 asm volatile( 1641 " idte %[r1],0,%[r2],%[m4]" 1642 : "+m" (*pmdp) 1643 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1644 [m4] "i" (local) 1645 : "cc" ); 1646 } else { 1647 /* flush with guest asce */ 1648 asm volatile( 1649 " idte %[r1],%[r3],%[r2],%[m4]" 1650 : "+m" (*pmdp) 1651 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1652 [r3] "a" (asce), [m4] "i" (local) 1653 : "cc" ); 1654 } 1655 } 1656 1657 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1658 unsigned long opt, unsigned long asce, 1659 int local) 1660 { 1661 unsigned long r3o; 1662 1663 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1664 r3o |= _ASCE_TYPE_REGION3; 1665 if (__builtin_constant_p(opt) && opt == 0) { 1666 /* flush without guest asce */ 1667 asm volatile( 1668 " idte %[r1],0,%[r2],%[m4]" 1669 : "+m" (*pudp) 1670 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1671 [m4] "i" (local) 1672 : "cc"); 1673 } else { 1674 /* flush with guest asce */ 1675 asm volatile( 1676 " idte %[r1],%[r3],%[r2],%[m4]" 1677 : "+m" (*pudp) 1678 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1679 [r3] "a" (asce), [m4] "i" (local) 1680 : "cc" ); 1681 } 1682 } 1683 1684 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1685 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1686 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1687 1688 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1689 1690 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1691 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1692 pgtable_t pgtable); 1693 1694 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1695 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1696 1697 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1698 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1699 unsigned long addr, pmd_t *pmdp, 1700 pmd_t entry, int dirty) 1701 { 1702 VM_BUG_ON(addr & ~HPAGE_MASK); 1703 1704 entry = pmd_mkyoung(entry); 1705 if (dirty) 1706 entry = pmd_mkdirty(entry); 1707 if (pmd_val(*pmdp) == pmd_val(entry)) 1708 return 0; 1709 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1710 return 1; 1711 } 1712 1713 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1714 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1715 unsigned long addr, pmd_t *pmdp) 1716 { 1717 pmd_t pmd = *pmdp; 1718 1719 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1720 return pmd_young(pmd); 1721 } 1722 1723 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1724 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1725 unsigned long addr, pmd_t *pmdp) 1726 { 1727 VM_BUG_ON(addr & ~HPAGE_MASK); 1728 return pmdp_test_and_clear_young(vma, addr, pmdp); 1729 } 1730 1731 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1732 pmd_t *pmdp, pmd_t entry) 1733 { 1734 if (!MACHINE_HAS_NX) 1735 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1736 set_pmd(pmdp, entry); 1737 } 1738 1739 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1740 { 1741 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1742 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1743 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1744 } 1745 1746 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1747 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1748 unsigned long addr, pmd_t *pmdp) 1749 { 1750 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1751 } 1752 1753 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1754 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1755 unsigned long addr, 1756 pmd_t *pmdp, int full) 1757 { 1758 if (full) { 1759 pmd_t pmd = *pmdp; 1760 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1761 return pmd; 1762 } 1763 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1764 } 1765 1766 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1767 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1768 unsigned long addr, pmd_t *pmdp) 1769 { 1770 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1771 } 1772 1773 #define __HAVE_ARCH_PMDP_INVALIDATE 1774 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1775 unsigned long addr, pmd_t *pmdp) 1776 { 1777 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1778 1779 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1780 } 1781 1782 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1783 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1784 unsigned long addr, pmd_t *pmdp) 1785 { 1786 pmd_t pmd = *pmdp; 1787 1788 if (pmd_write(pmd)) 1789 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1790 } 1791 1792 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1793 unsigned long address, 1794 pmd_t *pmdp) 1795 { 1796 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1797 } 1798 #define pmdp_collapse_flush pmdp_collapse_flush 1799 1800 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1801 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1802 1803 static inline int pmd_trans_huge(pmd_t pmd) 1804 { 1805 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1806 } 1807 1808 #define has_transparent_hugepage has_transparent_hugepage 1809 static inline int has_transparent_hugepage(void) 1810 { 1811 return MACHINE_HAS_EDAT1 ? 1 : 0; 1812 } 1813 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1814 1815 /* 1816 * 64 bit swap entry format: 1817 * A page-table entry has some bits we have to treat in a special way. 1818 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1819 * as invalid. 1820 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1821 * | offset |E11XX|type |S0| 1822 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1823 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1824 * 1825 * Bits 0-51 store the offset. 1826 * Bit 52 (E) is used to remember PG_anon_exclusive. 1827 * Bits 57-61 store the type. 1828 * Bit 62 (S) is used for softdirty tracking. 1829 * Bits 55 and 56 (X) are unused. 1830 */ 1831 1832 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1833 #define __SWP_OFFSET_SHIFT 12 1834 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1835 #define __SWP_TYPE_SHIFT 2 1836 1837 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1838 { 1839 unsigned long pteval; 1840 1841 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1842 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1843 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1844 return __pte(pteval); 1845 } 1846 1847 static inline unsigned long __swp_type(swp_entry_t entry) 1848 { 1849 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1850 } 1851 1852 static inline unsigned long __swp_offset(swp_entry_t entry) 1853 { 1854 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1855 } 1856 1857 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1858 { 1859 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1860 } 1861 1862 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1863 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1864 1865 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1866 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1867 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1868 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1869 extern void vmem_unmap_4k_page(unsigned long addr); 1870 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1871 extern int s390_enable_sie(void); 1872 extern int s390_enable_skey(void); 1873 extern void s390_reset_cmma(struct mm_struct *mm); 1874 1875 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1876 #define HAVE_ARCH_UNMAPPED_AREA 1877 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1878 1879 #define pmd_pgtable(pmd) \ 1880 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1881 1882 #endif /* _S390_PAGE_H */ 1883