1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <linux/page-flags.h> 33 #include <asm/bug.h> 34 #include <asm/page.h> 35 36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 37 extern void paging_init(void); 38 extern void vmem_map_init(void); 39 40 /* 41 * The S390 doesn't have any external MMU info: the kernel page 42 * tables contain all the necessary information. 43 */ 44 #define update_mmu_cache(vma, address, ptep) do { } while (0) 45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero; used 49 * for zero-mapped memory areas etc.. 50 */ 51 52 extern unsigned long empty_zero_page; 53 extern unsigned long zero_page_mask; 54 55 #define ZERO_PAGE(vaddr) \ 56 (virt_to_page((void *)(empty_zero_page + \ 57 (((unsigned long)(vaddr)) &zero_page_mask)))) 58 #define __HAVE_COLOR_ZERO_PAGE 59 60 /* TODO: s390 cannot support io_remap_pfn_range... */ 61 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 62 remap_pfn_range(vma, vaddr, pfn, size, prot) 63 64 #endif /* !__ASSEMBLY__ */ 65 66 /* 67 * PMD_SHIFT determines the size of the area a second-level page 68 * table can map 69 * PGDIR_SHIFT determines what a third-level page table entry can map 70 */ 71 #ifndef CONFIG_64BIT 72 # define PMD_SHIFT 20 73 # define PUD_SHIFT 20 74 # define PGDIR_SHIFT 20 75 #else /* CONFIG_64BIT */ 76 # define PMD_SHIFT 20 77 # define PUD_SHIFT 31 78 # define PGDIR_SHIFT 42 79 #endif /* CONFIG_64BIT */ 80 81 #define PMD_SIZE (1UL << PMD_SHIFT) 82 #define PMD_MASK (~(PMD_SIZE-1)) 83 #define PUD_SIZE (1UL << PUD_SHIFT) 84 #define PUD_MASK (~(PUD_SIZE-1)) 85 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 86 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 87 88 /* 89 * entries per page directory level: the S390 is two-level, so 90 * we don't really have any PMD directory physically. 91 * for S390 segment-table entries are combined to one PGD 92 * that leads to 1024 pte per pgd 93 */ 94 #define PTRS_PER_PTE 256 95 #ifndef CONFIG_64BIT 96 #define PTRS_PER_PMD 1 97 #define PTRS_PER_PUD 1 98 #else /* CONFIG_64BIT */ 99 #define PTRS_PER_PMD 2048 100 #define PTRS_PER_PUD 2048 101 #endif /* CONFIG_64BIT */ 102 #define PTRS_PER_PGD 2048 103 104 #define FIRST_USER_ADDRESS 0 105 106 #define pte_ERROR(e) \ 107 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 108 #define pmd_ERROR(e) \ 109 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 110 #define pud_ERROR(e) \ 111 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 112 #define pgd_ERROR(e) \ 113 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 114 115 #ifndef __ASSEMBLY__ 116 /* 117 * The vmalloc and module area will always be on the topmost area of the kernel 118 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 119 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 120 * modules will reside. That makes sure that inter module branches always 121 * happen without trampolines and in addition the placement within a 2GB frame 122 * is branch prediction unit friendly. 123 */ 124 extern unsigned long VMALLOC_START; 125 extern unsigned long VMALLOC_END; 126 extern struct page *vmemmap; 127 128 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 129 130 #ifdef CONFIG_64BIT 131 extern unsigned long MODULES_VADDR; 132 extern unsigned long MODULES_END; 133 #define MODULES_VADDR MODULES_VADDR 134 #define MODULES_END MODULES_END 135 #define MODULES_LEN (1UL << 31) 136 #endif 137 138 /* 139 * A 31 bit pagetable entry of S390 has following format: 140 * | PFRA | | OS | 141 * 0 0IP0 142 * 00000000001111111111222222222233 143 * 01234567890123456789012345678901 144 * 145 * I Page-Invalid Bit: Page is not available for address-translation 146 * P Page-Protection Bit: Store access not possible for page 147 * 148 * A 31 bit segmenttable entry of S390 has following format: 149 * | P-table origin | |PTL 150 * 0 IC 151 * 00000000001111111111222222222233 152 * 01234567890123456789012345678901 153 * 154 * I Segment-Invalid Bit: Segment is not available for address-translation 155 * C Common-Segment Bit: Segment is not private (PoP 3-30) 156 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 157 * 158 * The 31 bit segmenttable origin of S390 has following format: 159 * 160 * |S-table origin | | STL | 161 * X **GPS 162 * 00000000001111111111222222222233 163 * 01234567890123456789012345678901 164 * 165 * X Space-Switch event: 166 * G Segment-Invalid Bit: * 167 * P Private-Space Bit: Segment is not private (PoP 3-30) 168 * S Storage-Alteration: 169 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 170 * 171 * A 64 bit pagetable entry of S390 has following format: 172 * | PFRA |0IPC| OS | 173 * 0000000000111111111122222222223333333333444444444455555555556666 174 * 0123456789012345678901234567890123456789012345678901234567890123 175 * 176 * I Page-Invalid Bit: Page is not available for address-translation 177 * P Page-Protection Bit: Store access not possible for page 178 * C Change-bit override: HW is not required to set change bit 179 * 180 * A 64 bit segmenttable entry of S390 has following format: 181 * | P-table origin | TT 182 * 0000000000111111111122222222223333333333444444444455555555556666 183 * 0123456789012345678901234567890123456789012345678901234567890123 184 * 185 * I Segment-Invalid Bit: Segment is not available for address-translation 186 * C Common-Segment Bit: Segment is not private (PoP 3-30) 187 * P Page-Protection Bit: Store access not possible for page 188 * TT Type 00 189 * 190 * A 64 bit region table entry of S390 has following format: 191 * | S-table origin | TF TTTL 192 * 0000000000111111111122222222223333333333444444444455555555556666 193 * 0123456789012345678901234567890123456789012345678901234567890123 194 * 195 * I Segment-Invalid Bit: Segment is not available for address-translation 196 * TT Type 01 197 * TF 198 * TL Table length 199 * 200 * The 64 bit regiontable origin of S390 has following format: 201 * | region table origon | DTTL 202 * 0000000000111111111122222222223333333333444444444455555555556666 203 * 0123456789012345678901234567890123456789012345678901234567890123 204 * 205 * X Space-Switch event: 206 * G Segment-Invalid Bit: 207 * P Private-Space Bit: 208 * S Storage-Alteration: 209 * R Real space 210 * TL Table-Length: 211 * 212 * A storage key has the following format: 213 * | ACC |F|R|C|0| 214 * 0 3 4 5 6 7 215 * ACC: access key 216 * F : fetch protection bit 217 * R : referenced bit 218 * C : changed bit 219 */ 220 221 /* Hardware bits in the page table entry */ 222 #define _PAGE_CO 0x100 /* HW Change-bit override */ 223 #define _PAGE_RO 0x200 /* HW read-only bit */ 224 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 225 226 /* Software bits in the page table entry */ 227 #define _PAGE_SWT 0x001 /* SW pte type bit t */ 228 #define _PAGE_SWX 0x002 /* SW pte type bit x */ 229 #define _PAGE_SWC 0x004 /* SW pte changed bit */ 230 #define _PAGE_SWR 0x008 /* SW pte referenced bit */ 231 #define _PAGE_SWW 0x010 /* SW pte write bit */ 232 #define _PAGE_SPECIAL 0x020 /* SW associated with special page */ 233 #define __HAVE_ARCH_PTE_SPECIAL 234 235 /* Set of bits not changed in pte_modify */ 236 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ 237 _PAGE_SWC | _PAGE_SWR) 238 239 /* Six different types of pages. */ 240 #define _PAGE_TYPE_EMPTY 0x400 241 #define _PAGE_TYPE_NONE 0x401 242 #define _PAGE_TYPE_SWAP 0x403 243 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ 244 #define _PAGE_TYPE_RO 0x200 245 #define _PAGE_TYPE_RW 0x000 246 247 /* 248 * Only four types for huge pages, using the invalid bit and protection bit 249 * of a segment table entry. 250 */ 251 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ 252 #define _HPAGE_TYPE_NONE 0x220 253 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ 254 #define _HPAGE_TYPE_RW 0x000 255 256 /* 257 * PTE type bits are rather complicated. handle_pte_fault uses pte_present, 258 * pte_none and pte_file to find out the pte type WITHOUT holding the page 259 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to 260 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs 261 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. 262 * This change is done while holding the lock, but the intermediate step 263 * of a previously valid pte with the hw invalid bit set can be observed by 264 * handle_pte_fault. That makes it necessary that all valid pte types with 265 * the hw invalid bit set must be distinguishable from the four pte types 266 * empty, none, swap and file. 267 * 268 * irxt ipte irxt 269 * _PAGE_TYPE_EMPTY 1000 -> 1000 270 * _PAGE_TYPE_NONE 1001 -> 1001 271 * _PAGE_TYPE_SWAP 1011 -> 1011 272 * _PAGE_TYPE_FILE 11?1 -> 11?1 273 * _PAGE_TYPE_RO 0100 -> 1100 274 * _PAGE_TYPE_RW 0000 -> 1000 275 * 276 * pte_none is true for bits combinations 1000, 1010, 1100, 1110 277 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 278 * pte_file is true for bits combinations 1101, 1111 279 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. 280 */ 281 282 #ifndef CONFIG_64BIT 283 284 /* Bits in the segment table address-space-control-element */ 285 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 286 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 287 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 288 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 289 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 290 291 /* Bits in the segment table entry */ 292 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 293 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 294 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 295 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 296 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 297 298 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 299 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 300 301 /* Page status table bits for virtualization */ 302 #define RCP_ACC_BITS 0xf0000000UL 303 #define RCP_FP_BIT 0x08000000UL 304 #define RCP_PCL_BIT 0x00800000UL 305 #define RCP_HR_BIT 0x00400000UL 306 #define RCP_HC_BIT 0x00200000UL 307 #define RCP_GR_BIT 0x00040000UL 308 #define RCP_GC_BIT 0x00020000UL 309 310 /* User dirty / referenced bit for KVM's migration feature */ 311 #define KVM_UR_BIT 0x00008000UL 312 #define KVM_UC_BIT 0x00004000UL 313 314 #else /* CONFIG_64BIT */ 315 316 /* Bits in the segment/region table address-space-control-element */ 317 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 318 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 319 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 320 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 321 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 322 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 323 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 324 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 325 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 326 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 327 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 328 329 /* Bits in the region table entry */ 330 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 331 #define _REGION_ENTRY_RO 0x200 /* region protection bit */ 332 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 333 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 334 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 335 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 336 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 337 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 338 339 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 340 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) 341 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 342 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) 343 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 344 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) 345 346 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 347 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ 348 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ 349 350 /* Bits in the segment table entry */ 351 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 352 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 353 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 354 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 355 356 #define _SEGMENT_ENTRY (0) 357 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 358 359 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 360 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 361 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 362 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT) 363 364 /* Set of bits not changed in pmd_modify */ 365 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 366 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 367 368 /* Page status table bits for virtualization */ 369 #define RCP_ACC_BITS 0xf000000000000000UL 370 #define RCP_FP_BIT 0x0800000000000000UL 371 #define RCP_PCL_BIT 0x0080000000000000UL 372 #define RCP_HR_BIT 0x0040000000000000UL 373 #define RCP_HC_BIT 0x0020000000000000UL 374 #define RCP_GR_BIT 0x0004000000000000UL 375 #define RCP_GC_BIT 0x0002000000000000UL 376 377 /* User dirty / referenced bit for KVM's migration feature */ 378 #define KVM_UR_BIT 0x0000800000000000UL 379 #define KVM_UC_BIT 0x0000400000000000UL 380 381 #endif /* CONFIG_64BIT */ 382 383 /* 384 * A user page table pointer has the space-switch-event bit, the 385 * private-space-control bit and the storage-alteration-event-control 386 * bit set. A kernel page table pointer doesn't need them. 387 */ 388 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 389 _ASCE_ALT_EVENT) 390 391 /* 392 * Page protection definitions. 393 */ 394 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) 395 #define PAGE_RO __pgprot(_PAGE_TYPE_RO) 396 #define PAGE_RW __pgprot(_PAGE_TYPE_RO | _PAGE_SWW) 397 #define PAGE_RWC __pgprot(_PAGE_TYPE_RW | _PAGE_SWW | _PAGE_SWC) 398 399 #define PAGE_KERNEL PAGE_RWC 400 #define PAGE_SHARED PAGE_KERNEL 401 #define PAGE_COPY PAGE_RO 402 403 /* 404 * On s390 the page table entry has an invalid bit and a read-only bit. 405 * Read permission implies execute permission and write permission 406 * implies read permission. 407 */ 408 /*xwr*/ 409 #define __P000 PAGE_NONE 410 #define __P001 PAGE_RO 411 #define __P010 PAGE_RO 412 #define __P011 PAGE_RO 413 #define __P100 PAGE_RO 414 #define __P101 PAGE_RO 415 #define __P110 PAGE_RO 416 #define __P111 PAGE_RO 417 418 #define __S000 PAGE_NONE 419 #define __S001 PAGE_RO 420 #define __S010 PAGE_RW 421 #define __S011 PAGE_RW 422 #define __S100 PAGE_RO 423 #define __S101 PAGE_RO 424 #define __S110 PAGE_RW 425 #define __S111 PAGE_RW 426 427 static inline int mm_exclusive(struct mm_struct *mm) 428 { 429 return likely(mm == current->active_mm && 430 atomic_read(&mm->context.attach_count) <= 1); 431 } 432 433 static inline int mm_has_pgste(struct mm_struct *mm) 434 { 435 #ifdef CONFIG_PGSTE 436 if (unlikely(mm->context.has_pgste)) 437 return 1; 438 #endif 439 return 0; 440 } 441 /* 442 * pgd/pmd/pte query functions 443 */ 444 #ifndef CONFIG_64BIT 445 446 static inline int pgd_present(pgd_t pgd) { return 1; } 447 static inline int pgd_none(pgd_t pgd) { return 0; } 448 static inline int pgd_bad(pgd_t pgd) { return 0; } 449 450 static inline int pud_present(pud_t pud) { return 1; } 451 static inline int pud_none(pud_t pud) { return 0; } 452 static inline int pud_large(pud_t pud) { return 0; } 453 static inline int pud_bad(pud_t pud) { return 0; } 454 455 #else /* CONFIG_64BIT */ 456 457 static inline int pgd_present(pgd_t pgd) 458 { 459 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 460 return 1; 461 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 462 } 463 464 static inline int pgd_none(pgd_t pgd) 465 { 466 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 467 return 0; 468 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; 469 } 470 471 static inline int pgd_bad(pgd_t pgd) 472 { 473 /* 474 * With dynamic page table levels the pgd can be a region table 475 * entry or a segment table entry. Check for the bit that are 476 * invalid for either table entry. 477 */ 478 unsigned long mask = 479 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 480 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 481 return (pgd_val(pgd) & mask) != 0; 482 } 483 484 static inline int pud_present(pud_t pud) 485 { 486 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 487 return 1; 488 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 489 } 490 491 static inline int pud_none(pud_t pud) 492 { 493 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 494 return 0; 495 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; 496 } 497 498 static inline int pud_large(pud_t pud) 499 { 500 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 501 return 0; 502 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 503 } 504 505 static inline int pud_bad(pud_t pud) 506 { 507 /* 508 * With dynamic page table levels the pud can be a region table 509 * entry or a segment table entry. Check for the bit that are 510 * invalid for either table entry. 511 */ 512 unsigned long mask = 513 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 514 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 515 return (pud_val(pud) & mask) != 0; 516 } 517 518 #endif /* CONFIG_64BIT */ 519 520 static inline int pmd_present(pmd_t pmd) 521 { 522 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO; 523 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE || 524 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV); 525 } 526 527 static inline int pmd_none(pmd_t pmd) 528 { 529 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) && 530 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO); 531 } 532 533 static inline int pmd_large(pmd_t pmd) 534 { 535 #ifdef CONFIG_64BIT 536 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE); 537 #else 538 return 0; 539 #endif 540 } 541 542 static inline int pmd_bad(pmd_t pmd) 543 { 544 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; 545 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; 546 } 547 548 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 549 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 550 unsigned long addr, pmd_t *pmdp); 551 552 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 553 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 554 unsigned long address, pmd_t *pmdp, 555 pmd_t entry, int dirty); 556 557 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 558 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 559 unsigned long address, pmd_t *pmdp); 560 561 #define __HAVE_ARCH_PMD_WRITE 562 static inline int pmd_write(pmd_t pmd) 563 { 564 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0; 565 } 566 567 static inline int pmd_young(pmd_t pmd) 568 { 569 return 0; 570 } 571 572 static inline int pte_none(pte_t pte) 573 { 574 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); 575 } 576 577 static inline int pte_present(pte_t pte) 578 { 579 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; 580 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || 581 (!(pte_val(pte) & _PAGE_INVALID) && 582 !(pte_val(pte) & _PAGE_SWT)); 583 } 584 585 static inline int pte_file(pte_t pte) 586 { 587 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; 588 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; 589 } 590 591 static inline int pte_special(pte_t pte) 592 { 593 return (pte_val(pte) & _PAGE_SPECIAL); 594 } 595 596 #define __HAVE_ARCH_PTE_SAME 597 static inline int pte_same(pte_t a, pte_t b) 598 { 599 return pte_val(a) == pte_val(b); 600 } 601 602 static inline pgste_t pgste_get_lock(pte_t *ptep) 603 { 604 unsigned long new = 0; 605 #ifdef CONFIG_PGSTE 606 unsigned long old; 607 608 preempt_disable(); 609 asm( 610 " lg %0,%2\n" 611 "0: lgr %1,%0\n" 612 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */ 613 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */ 614 " csg %0,%1,%2\n" 615 " jl 0b\n" 616 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 617 : "Q" (ptep[PTRS_PER_PTE]) : "cc"); 618 #endif 619 return __pgste(new); 620 } 621 622 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 623 { 624 #ifdef CONFIG_PGSTE 625 asm( 626 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ 627 " stg %1,%0\n" 628 : "=Q" (ptep[PTRS_PER_PTE]) 629 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); 630 preempt_enable(); 631 #endif 632 } 633 634 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 635 { 636 #ifdef CONFIG_PGSTE 637 unsigned long address, bits; 638 unsigned char skey; 639 640 if (!pte_present(*ptep)) 641 return pgste; 642 address = pte_val(*ptep) & PAGE_MASK; 643 skey = page_get_storage_key(address); 644 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 645 /* Clear page changed & referenced bit in the storage key */ 646 if (bits & _PAGE_CHANGED) 647 page_set_storage_key(address, skey ^ bits, 0); 648 else if (bits) 649 page_reset_referenced(address); 650 /* Transfer page changed & referenced bit to guest bits in pgste */ 651 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */ 652 /* Get host changed & referenced bits from pgste */ 653 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52; 654 /* Transfer page changed & referenced bit to kvm user bits */ 655 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */ 656 /* Clear relevant host bits in pgste. */ 657 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT); 658 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT); 659 /* Copy page access key and fetch protection bit to pgste */ 660 pgste_val(pgste) |= 661 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 662 /* Transfer referenced bit to pte */ 663 pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1; 664 #endif 665 return pgste; 666 667 } 668 669 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) 670 { 671 #ifdef CONFIG_PGSTE 672 int young; 673 674 if (!pte_present(*ptep)) 675 return pgste; 676 /* Get referenced bit from storage key */ 677 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); 678 if (young) 679 pgste_val(pgste) |= RCP_GR_BIT; 680 /* Get host referenced bit from pgste */ 681 if (pgste_val(pgste) & RCP_HR_BIT) { 682 pgste_val(pgste) &= ~RCP_HR_BIT; 683 young = 1; 684 } 685 /* Transfer referenced bit to kvm user bits and pte */ 686 if (young) { 687 pgste_val(pgste) |= KVM_UR_BIT; 688 pte_val(*ptep) |= _PAGE_SWR; 689 } 690 #endif 691 return pgste; 692 } 693 694 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) 695 { 696 #ifdef CONFIG_PGSTE 697 unsigned long address; 698 unsigned long okey, nkey; 699 700 if (!pte_present(entry)) 701 return; 702 address = pte_val(entry) & PAGE_MASK; 703 okey = nkey = page_get_storage_key(address); 704 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT); 705 /* Set page access key and fetch protection bit from pgste */ 706 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; 707 if (okey != nkey) 708 page_set_storage_key(address, nkey, 0); 709 #endif 710 } 711 712 static inline void pgste_set_pte(pte_t *ptep, pte_t entry) 713 { 714 if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_SWW)) { 715 /* 716 * Without enhanced suppression-on-protection force 717 * the dirty bit on for all writable ptes. 718 */ 719 pte_val(entry) |= _PAGE_SWC; 720 pte_val(entry) &= ~_PAGE_RO; 721 } 722 *ptep = entry; 723 } 724 725 /** 726 * struct gmap_struct - guest address space 727 * @mm: pointer to the parent mm_struct 728 * @table: pointer to the page directory 729 * @asce: address space control element for gmap page table 730 * @crst_list: list of all crst tables used in the guest address space 731 */ 732 struct gmap { 733 struct list_head list; 734 struct mm_struct *mm; 735 unsigned long *table; 736 unsigned long asce; 737 struct list_head crst_list; 738 }; 739 740 /** 741 * struct gmap_rmap - reverse mapping for segment table entries 742 * @next: pointer to the next gmap_rmap structure in the list 743 * @entry: pointer to a segment table entry 744 */ 745 struct gmap_rmap { 746 struct list_head list; 747 unsigned long *entry; 748 }; 749 750 /** 751 * struct gmap_pgtable - gmap information attached to a page table 752 * @vmaddr: address of the 1MB segment in the process virtual memory 753 * @mapper: list of segment table entries maping a page table 754 */ 755 struct gmap_pgtable { 756 unsigned long vmaddr; 757 struct list_head mapper; 758 }; 759 760 struct gmap *gmap_alloc(struct mm_struct *mm); 761 void gmap_free(struct gmap *gmap); 762 void gmap_enable(struct gmap *gmap); 763 void gmap_disable(struct gmap *gmap); 764 int gmap_map_segment(struct gmap *gmap, unsigned long from, 765 unsigned long to, unsigned long length); 766 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 767 unsigned long __gmap_fault(unsigned long address, struct gmap *); 768 unsigned long gmap_fault(unsigned long address, struct gmap *); 769 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 770 771 /* 772 * Certain architectures need to do special things when PTEs 773 * within a page table are directly modified. Thus, the following 774 * hook is made available. 775 */ 776 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 777 pte_t *ptep, pte_t entry) 778 { 779 pgste_t pgste; 780 781 if (mm_has_pgste(mm)) { 782 pgste = pgste_get_lock(ptep); 783 pgste_set_key(ptep, pgste, entry); 784 pgste_set_pte(ptep, entry); 785 pgste_set_unlock(ptep, pgste); 786 } else { 787 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) 788 pte_val(entry) |= _PAGE_CO; 789 *ptep = entry; 790 } 791 } 792 793 /* 794 * query functions pte_write/pte_dirty/pte_young only work if 795 * pte_present() is true. Undefined behaviour if not.. 796 */ 797 static inline int pte_write(pte_t pte) 798 { 799 return (pte_val(pte) & _PAGE_SWW) != 0; 800 } 801 802 static inline int pte_dirty(pte_t pte) 803 { 804 return (pte_val(pte) & _PAGE_SWC) != 0; 805 } 806 807 static inline int pte_young(pte_t pte) 808 { 809 #ifdef CONFIG_PGSTE 810 if (pte_val(pte) & _PAGE_SWR) 811 return 1; 812 #endif 813 return 0; 814 } 815 816 /* 817 * pgd/pmd/pte modification functions 818 */ 819 820 static inline void pgd_clear(pgd_t *pgd) 821 { 822 #ifdef CONFIG_64BIT 823 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 824 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 825 #endif 826 } 827 828 static inline void pud_clear(pud_t *pud) 829 { 830 #ifdef CONFIG_64BIT 831 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 832 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 833 #endif 834 } 835 836 static inline void pmd_clear(pmd_t *pmdp) 837 { 838 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 839 } 840 841 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 842 { 843 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 844 } 845 846 /* 847 * The following pte modification functions only work if 848 * pte_present() is true. Undefined behaviour if not.. 849 */ 850 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 851 { 852 pte_val(pte) &= _PAGE_CHG_MASK; 853 pte_val(pte) |= pgprot_val(newprot); 854 if ((pte_val(pte) & _PAGE_SWC) && (pte_val(pte) & _PAGE_SWW)) 855 pte_val(pte) &= ~_PAGE_RO; 856 return pte; 857 } 858 859 static inline pte_t pte_wrprotect(pte_t pte) 860 { 861 pte_val(pte) &= ~_PAGE_SWW; 862 /* Do not clobber _PAGE_TYPE_NONE pages! */ 863 if (!(pte_val(pte) & _PAGE_INVALID)) 864 pte_val(pte) |= _PAGE_RO; 865 return pte; 866 } 867 868 static inline pte_t pte_mkwrite(pte_t pte) 869 { 870 pte_val(pte) |= _PAGE_SWW; 871 if (pte_val(pte) & _PAGE_SWC) 872 pte_val(pte) &= ~_PAGE_RO; 873 return pte; 874 } 875 876 static inline pte_t pte_mkclean(pte_t pte) 877 { 878 pte_val(pte) &= ~_PAGE_SWC; 879 /* Do not clobber _PAGE_TYPE_NONE pages! */ 880 if (!(pte_val(pte) & _PAGE_INVALID)) 881 pte_val(pte) |= _PAGE_RO; 882 return pte; 883 } 884 885 static inline pte_t pte_mkdirty(pte_t pte) 886 { 887 pte_val(pte) |= _PAGE_SWC; 888 if (pte_val(pte) & _PAGE_SWW) 889 pte_val(pte) &= ~_PAGE_RO; 890 return pte; 891 } 892 893 static inline pte_t pte_mkold(pte_t pte) 894 { 895 #ifdef CONFIG_PGSTE 896 pte_val(pte) &= ~_PAGE_SWR; 897 #endif 898 return pte; 899 } 900 901 static inline pte_t pte_mkyoung(pte_t pte) 902 { 903 return pte; 904 } 905 906 static inline pte_t pte_mkspecial(pte_t pte) 907 { 908 pte_val(pte) |= _PAGE_SPECIAL; 909 return pte; 910 } 911 912 #ifdef CONFIG_HUGETLB_PAGE 913 static inline pte_t pte_mkhuge(pte_t pte) 914 { 915 /* 916 * PROT_NONE needs to be remapped from the pte type to the ste type. 917 * The HW invalid bit is also different for pte and ste. The pte 918 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE 919 * bit, so we don't have to clear it. 920 */ 921 if (pte_val(pte) & _PAGE_INVALID) { 922 if (pte_val(pte) & _PAGE_SWT) 923 pte_val(pte) |= _HPAGE_TYPE_NONE; 924 pte_val(pte) |= _SEGMENT_ENTRY_INV; 925 } 926 /* 927 * Clear SW pte bits, there are no SW bits in a segment table entry. 928 */ 929 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX | _PAGE_SWC | 930 _PAGE_SWR | _PAGE_SWW); 931 /* 932 * Also set the change-override bit because we don't need dirty bit 933 * tracking for hugetlbfs pages. 934 */ 935 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO); 936 return pte; 937 } 938 #endif 939 940 /* 941 * Get (and clear) the user dirty bit for a pte. 942 */ 943 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 944 pte_t *ptep) 945 { 946 pgste_t pgste; 947 int dirty = 0; 948 949 if (mm_has_pgste(mm)) { 950 pgste = pgste_get_lock(ptep); 951 pgste = pgste_update_all(ptep, pgste); 952 dirty = !!(pgste_val(pgste) & KVM_UC_BIT); 953 pgste_val(pgste) &= ~KVM_UC_BIT; 954 pgste_set_unlock(ptep, pgste); 955 return dirty; 956 } 957 return dirty; 958 } 959 960 /* 961 * Get (and clear) the user referenced bit for a pte. 962 */ 963 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, 964 pte_t *ptep) 965 { 966 pgste_t pgste; 967 int young = 0; 968 969 if (mm_has_pgste(mm)) { 970 pgste = pgste_get_lock(ptep); 971 pgste = pgste_update_young(ptep, pgste); 972 young = !!(pgste_val(pgste) & KVM_UR_BIT); 973 pgste_val(pgste) &= ~KVM_UR_BIT; 974 pgste_set_unlock(ptep, pgste); 975 } 976 return young; 977 } 978 979 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 980 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 981 unsigned long addr, pte_t *ptep) 982 { 983 pgste_t pgste; 984 pte_t pte; 985 986 if (mm_has_pgste(vma->vm_mm)) { 987 pgste = pgste_get_lock(ptep); 988 pgste = pgste_update_young(ptep, pgste); 989 pte = *ptep; 990 *ptep = pte_mkold(pte); 991 pgste_set_unlock(ptep, pgste); 992 return pte_young(pte); 993 } 994 return 0; 995 } 996 997 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 998 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 999 unsigned long address, pte_t *ptep) 1000 { 1001 /* No need to flush TLB 1002 * On s390 reference bits are in storage key and never in TLB 1003 * With virtualization we handle the reference bit, without we 1004 * we can simply return */ 1005 return ptep_test_and_clear_young(vma, address, ptep); 1006 } 1007 1008 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 1009 { 1010 if (!(pte_val(*ptep) & _PAGE_INVALID)) { 1011 #ifndef CONFIG_64BIT 1012 /* pto must point to the start of the segment table */ 1013 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); 1014 #else 1015 /* ipte in zarch mode can do the math */ 1016 pte_t *pto = ptep; 1017 #endif 1018 asm volatile( 1019 " ipte %2,%3" 1020 : "=m" (*ptep) : "m" (*ptep), 1021 "a" (pto), "a" (address)); 1022 } 1023 } 1024 1025 /* 1026 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1027 * both clear the TLB for the unmapped pte. The reason is that 1028 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1029 * to modify an active pte. The sequence is 1030 * 1) ptep_get_and_clear 1031 * 2) set_pte_at 1032 * 3) flush_tlb_range 1033 * On s390 the tlb needs to get flushed with the modification of the pte 1034 * if the pte is active. The only way how this can be implemented is to 1035 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1036 * is a nop. 1037 */ 1038 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1039 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1040 unsigned long address, pte_t *ptep) 1041 { 1042 pgste_t pgste; 1043 pte_t pte; 1044 1045 mm->context.flush_mm = 1; 1046 if (mm_has_pgste(mm)) 1047 pgste = pgste_get_lock(ptep); 1048 1049 pte = *ptep; 1050 if (!mm_exclusive(mm)) 1051 __ptep_ipte(address, ptep); 1052 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1053 1054 if (mm_has_pgste(mm)) { 1055 pgste = pgste_update_all(&pte, pgste); 1056 pgste_set_unlock(ptep, pgste); 1057 } 1058 return pte; 1059 } 1060 1061 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1062 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1063 unsigned long address, 1064 pte_t *ptep) 1065 { 1066 pte_t pte; 1067 1068 mm->context.flush_mm = 1; 1069 if (mm_has_pgste(mm)) 1070 pgste_get_lock(ptep); 1071 1072 pte = *ptep; 1073 if (!mm_exclusive(mm)) 1074 __ptep_ipte(address, ptep); 1075 return pte; 1076 } 1077 1078 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1079 unsigned long address, 1080 pte_t *ptep, pte_t pte) 1081 { 1082 if (mm_has_pgste(mm)) { 1083 pgste_set_pte(ptep, pte); 1084 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE)); 1085 } else 1086 *ptep = pte; 1087 } 1088 1089 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1090 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1091 unsigned long address, pte_t *ptep) 1092 { 1093 pgste_t pgste; 1094 pte_t pte; 1095 1096 if (mm_has_pgste(vma->vm_mm)) 1097 pgste = pgste_get_lock(ptep); 1098 1099 pte = *ptep; 1100 __ptep_ipte(address, ptep); 1101 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1102 1103 if (mm_has_pgste(vma->vm_mm)) { 1104 pgste = pgste_update_all(&pte, pgste); 1105 pgste_set_unlock(ptep, pgste); 1106 } 1107 return pte; 1108 } 1109 1110 /* 1111 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1112 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1113 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1114 * cannot be accessed while the batched unmap is running. In this case 1115 * full==1 and a simple pte_clear is enough. See tlb.h. 1116 */ 1117 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1118 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1119 unsigned long address, 1120 pte_t *ptep, int full) 1121 { 1122 pgste_t pgste; 1123 pte_t pte; 1124 1125 if (mm_has_pgste(mm)) 1126 pgste = pgste_get_lock(ptep); 1127 1128 pte = *ptep; 1129 if (!full) 1130 __ptep_ipte(address, ptep); 1131 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1132 1133 if (mm_has_pgste(mm)) { 1134 pgste = pgste_update_all(&pte, pgste); 1135 pgste_set_unlock(ptep, pgste); 1136 } 1137 return pte; 1138 } 1139 1140 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1141 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1142 unsigned long address, pte_t *ptep) 1143 { 1144 pgste_t pgste; 1145 pte_t pte = *ptep; 1146 1147 if (pte_write(pte)) { 1148 mm->context.flush_mm = 1; 1149 if (mm_has_pgste(mm)) 1150 pgste = pgste_get_lock(ptep); 1151 1152 if (!mm_exclusive(mm)) 1153 __ptep_ipte(address, ptep); 1154 pte = pte_wrprotect(pte); 1155 1156 if (mm_has_pgste(mm)) { 1157 pgste_set_pte(ptep, pte); 1158 pgste_set_unlock(ptep, pgste); 1159 } else 1160 *ptep = pte; 1161 } 1162 return pte; 1163 } 1164 1165 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1166 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1167 unsigned long address, pte_t *ptep, 1168 pte_t entry, int dirty) 1169 { 1170 pgste_t pgste; 1171 1172 if (pte_same(*ptep, entry)) 1173 return 0; 1174 if (mm_has_pgste(vma->vm_mm)) 1175 pgste = pgste_get_lock(ptep); 1176 1177 __ptep_ipte(address, ptep); 1178 1179 if (mm_has_pgste(vma->vm_mm)) { 1180 pgste_set_pte(ptep, entry); 1181 pgste_set_unlock(ptep, pgste); 1182 } else 1183 *ptep = entry; 1184 return 1; 1185 } 1186 1187 /* 1188 * Conversion functions: convert a page and protection to a page entry, 1189 * and a page entry and page directory to the page they refer to. 1190 */ 1191 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1192 { 1193 pte_t __pte; 1194 pte_val(__pte) = physpage + pgprot_val(pgprot); 1195 return __pte; 1196 } 1197 1198 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1199 { 1200 unsigned long physpage = page_to_phys(page); 1201 pte_t __pte = mk_pte_phys(physpage, pgprot); 1202 1203 if ((pte_val(__pte) & _PAGE_SWW) && PageDirty(page)) { 1204 pte_val(__pte) |= _PAGE_SWC; 1205 pte_val(__pte) &= ~_PAGE_RO; 1206 } 1207 return __pte; 1208 } 1209 1210 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1211 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1212 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1213 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1214 1215 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1216 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1217 1218 #ifndef CONFIG_64BIT 1219 1220 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1221 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1222 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1223 1224 #define pud_offset(pgd, address) ((pud_t *) pgd) 1225 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1226 1227 #else /* CONFIG_64BIT */ 1228 1229 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1230 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1231 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1232 1233 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1234 { 1235 pud_t *pud = (pud_t *) pgd; 1236 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1237 pud = (pud_t *) pgd_deref(*pgd); 1238 return pud + pud_index(address); 1239 } 1240 1241 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1242 { 1243 pmd_t *pmd = (pmd_t *) pud; 1244 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1245 pmd = (pmd_t *) pud_deref(*pud); 1246 return pmd + pmd_index(address); 1247 } 1248 1249 #endif /* CONFIG_64BIT */ 1250 1251 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1252 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1253 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1254 1255 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1256 1257 /* Find an entry in the lowest level page table.. */ 1258 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1259 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1260 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1261 #define pte_unmap(pte) do { } while (0) 1262 1263 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) 1264 { 1265 unsigned long sto = (unsigned long) pmdp - 1266 pmd_index(address) * sizeof(pmd_t); 1267 1268 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) { 1269 asm volatile( 1270 " .insn rrf,0xb98e0000,%2,%3,0,0" 1271 : "=m" (*pmdp) 1272 : "m" (*pmdp), "a" (sto), 1273 "a" ((address & HPAGE_MASK)) 1274 : "cc" 1275 ); 1276 } 1277 } 1278 1279 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1280 1281 #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE) 1282 #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO) 1283 #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW) 1284 1285 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1286 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable); 1287 1288 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1289 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm); 1290 1291 static inline int pmd_trans_splitting(pmd_t pmd) 1292 { 1293 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1294 } 1295 1296 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1297 pmd_t *pmdp, pmd_t entry) 1298 { 1299 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1) 1300 pmd_val(entry) |= _SEGMENT_ENTRY_CO; 1301 *pmdp = entry; 1302 } 1303 1304 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1305 { 1306 /* 1307 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx) 1308 * Convert to segment table entry format. 1309 */ 1310 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1311 return pgprot_val(SEGMENT_NONE); 1312 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1313 return pgprot_val(SEGMENT_RO); 1314 return pgprot_val(SEGMENT_RW); 1315 } 1316 1317 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1318 { 1319 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1320 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1321 return pmd; 1322 } 1323 1324 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1325 { 1326 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1327 return pmd; 1328 } 1329 1330 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1331 { 1332 /* Do not clobber _HPAGE_TYPE_NONE pages! */ 1333 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV)) 1334 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; 1335 return pmd; 1336 } 1337 1338 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1339 { 1340 pmd_val(pmd) |= _SEGMENT_ENTRY_RO; 1341 return pmd; 1342 } 1343 1344 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1345 { 1346 /* No dirty bit in the segment table entry. */ 1347 return pmd; 1348 } 1349 1350 static inline pmd_t pmd_mkold(pmd_t pmd) 1351 { 1352 /* No referenced bit in the segment table entry. */ 1353 return pmd; 1354 } 1355 1356 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1357 { 1358 /* No referenced bit in the segment table entry. */ 1359 return pmd; 1360 } 1361 1362 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1363 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1364 unsigned long address, pmd_t *pmdp) 1365 { 1366 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK; 1367 long tmp, rc; 1368 int counter; 1369 1370 rc = 0; 1371 if (MACHINE_HAS_RRBM) { 1372 counter = PTRS_PER_PTE >> 6; 1373 asm volatile( 1374 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */ 1375 " ogr %1,%0\n" 1376 " la %3,0(%4,%3)\n" 1377 " brct %2,0b\n" 1378 : "=&d" (tmp), "+&d" (rc), "+d" (counter), 1379 "+a" (pmd_addr) 1380 : "a" (64 * 4096UL) : "cc"); 1381 rc = !!rc; 1382 } else { 1383 counter = PTRS_PER_PTE; 1384 asm volatile( 1385 "0: rrbe 0,%2\n" 1386 " la %2,0(%3,%2)\n" 1387 " brc 12,1f\n" 1388 " lhi %0,1\n" 1389 "1: brct %1,0b\n" 1390 : "+d" (rc), "+d" (counter), "+a" (pmd_addr) 1391 : "a" (4096UL) : "cc"); 1392 } 1393 return rc; 1394 } 1395 1396 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1397 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1398 unsigned long address, pmd_t *pmdp) 1399 { 1400 pmd_t pmd = *pmdp; 1401 1402 __pmd_idte(address, pmdp); 1403 pmd_clear(pmdp); 1404 return pmd; 1405 } 1406 1407 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1408 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1409 unsigned long address, pmd_t *pmdp) 1410 { 1411 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1412 } 1413 1414 #define __HAVE_ARCH_PMDP_INVALIDATE 1415 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1416 unsigned long address, pmd_t *pmdp) 1417 { 1418 __pmd_idte(address, pmdp); 1419 } 1420 1421 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1422 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1423 unsigned long address, pmd_t *pmdp) 1424 { 1425 pmd_t pmd = *pmdp; 1426 1427 if (pmd_write(pmd)) { 1428 __pmd_idte(address, pmdp); 1429 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); 1430 } 1431 } 1432 1433 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1434 { 1435 pmd_t __pmd; 1436 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1437 return __pmd; 1438 } 1439 1440 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1441 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1442 1443 static inline int pmd_trans_huge(pmd_t pmd) 1444 { 1445 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1446 } 1447 1448 static inline int has_transparent_hugepage(void) 1449 { 1450 return MACHINE_HAS_HPAGE ? 1 : 0; 1451 } 1452 1453 static inline unsigned long pmd_pfn(pmd_t pmd) 1454 { 1455 return pmd_val(pmd) >> PAGE_SHIFT; 1456 } 1457 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1458 1459 /* 1460 * 31 bit swap entry format: 1461 * A page-table entry has some bits we have to treat in a special way. 1462 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1463 * exception will occur instead of a page translation exception. The 1464 * specifiation exception has the bad habit not to store necessary 1465 * information in the lowcore. 1466 * Bit 21 and bit 22 are the page invalid bit and the page protection 1467 * bit. We set both to indicate a swapped page. 1468 * Bit 30 and 31 are used to distinguish the different page types. For 1469 * a swapped page these bits need to be zero. 1470 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1471 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1472 * plus 24 for the offset. 1473 * 0| offset |0110|o|type |00| 1474 * 0 0000000001111111111 2222 2 22222 33 1475 * 0 1234567890123456789 0123 4 56789 01 1476 * 1477 * 64 bit swap entry format: 1478 * A page-table entry has some bits we have to treat in a special way. 1479 * Bits 52 and bit 55 have to be zero, otherwise an specification 1480 * exception will occur instead of a page translation exception. The 1481 * specifiation exception has the bad habit not to store necessary 1482 * information in the lowcore. 1483 * Bit 53 and bit 54 are the page invalid bit and the page protection 1484 * bit. We set both to indicate a swapped page. 1485 * Bit 62 and 63 are used to distinguish the different page types. For 1486 * a swapped page these bits need to be zero. 1487 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1488 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1489 * plus 56 for the offset. 1490 * | offset |0110|o|type |00| 1491 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1492 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1493 */ 1494 #ifndef CONFIG_64BIT 1495 #define __SWP_OFFSET_MASK (~0UL >> 12) 1496 #else 1497 #define __SWP_OFFSET_MASK (~0UL >> 11) 1498 #endif 1499 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1500 { 1501 pte_t pte; 1502 offset &= __SWP_OFFSET_MASK; 1503 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | 1504 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1505 return pte; 1506 } 1507 1508 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1509 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1510 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1511 1512 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1513 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1514 1515 #ifndef CONFIG_64BIT 1516 # define PTE_FILE_MAX_BITS 26 1517 #else /* CONFIG_64BIT */ 1518 # define PTE_FILE_MAX_BITS 59 1519 #endif /* CONFIG_64BIT */ 1520 1521 #define pte_to_pgoff(__pte) \ 1522 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1523 1524 #define pgoff_to_pte(__off) \ 1525 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1526 | _PAGE_TYPE_FILE }) 1527 1528 #endif /* !__ASSEMBLY__ */ 1529 1530 #define kern_addr_valid(addr) (1) 1531 1532 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1533 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1534 extern int s390_enable_sie(void); 1535 1536 /* 1537 * No page table caches to initialise 1538 */ 1539 static inline void pgtable_cache_init(void) { } 1540 static inline void check_pgt_cache(void) { } 1541 1542 #include <asm-generic/pgtable.h> 1543 1544 #endif /* _S390_PAGE_H */ 1545