1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/ctlreg.h> 22 #include <asm/bug.h> 23 #include <asm/page.h> 24 #include <asm/uv.h> 25 26 extern pgd_t swapper_pg_dir[]; 27 extern pgd_t invalid_pg_dir[]; 28 extern void paging_init(void); 29 extern struct ctlreg s390_invalid_asce; 30 31 enum { 32 PG_DIRECT_MAP_4K = 0, 33 PG_DIRECT_MAP_1M, 34 PG_DIRECT_MAP_2G, 35 PG_DIRECT_MAP_MAX 36 }; 37 38 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 39 40 static inline void update_page_count(int level, long count) 41 { 42 if (IS_ENABLED(CONFIG_PROC_FS)) 43 atomic_long_add(count, &direct_pages_count[level]); 44 } 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 52 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 53 54 /* 55 * ZERO_PAGE is a global shared page that is always zero; used 56 * for zero-mapped memory areas etc.. 57 */ 58 59 extern unsigned long empty_zero_page; 60 extern unsigned long zero_page_mask; 61 62 #define ZERO_PAGE(vaddr) \ 63 (virt_to_page((void *)(empty_zero_page + \ 64 (((unsigned long)(vaddr)) &zero_page_mask)))) 65 #define __HAVE_COLOR_ZERO_PAGE 66 67 /* TODO: s390 cannot support io_remap_pfn_range... */ 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 71 #define pmd_ERROR(e) \ 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 73 #define pud_ERROR(e) \ 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 75 #define p4d_ERROR(e) \ 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 77 #define pgd_ERROR(e) \ 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 79 80 /* 81 * The vmalloc and module area will always be on the topmost area of the 82 * kernel mapping. 512GB are reserved for vmalloc by default. 83 * At the top of the vmalloc area a 2GB area is reserved where modules 84 * will reside. That makes sure that inter module branches always 85 * happen without trampolines and in addition the placement within a 86 * 2GB frame is branch prediction unit friendly. 87 */ 88 extern unsigned long __bootdata_preserved(VMALLOC_START); 89 extern unsigned long __bootdata_preserved(VMALLOC_END); 90 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 91 extern struct page *__bootdata_preserved(vmemmap); 92 extern unsigned long __bootdata_preserved(vmemmap_size); 93 94 extern unsigned long __bootdata_preserved(MODULES_VADDR); 95 extern unsigned long __bootdata_preserved(MODULES_END); 96 #define MODULES_VADDR MODULES_VADDR 97 #define MODULES_END MODULES_END 98 #define MODULES_LEN (1UL << 31) 99 100 static inline int is_module_addr(void *addr) 101 { 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 103 if (addr < (void *)MODULES_VADDR) 104 return 0; 105 if (addr > (void *)MODULES_END) 106 return 0; 107 return 1; 108 } 109 110 #ifdef CONFIG_RANDOMIZE_BASE 111 #define KASLR_LEN (1UL << 31) 112 #else 113 #define KASLR_LEN 0UL 114 #endif 115 116 /* 117 * A 64 bit pagetable entry of S390 has following format: 118 * | PFRA |0IPC| OS | 119 * 0000000000111111111122222222223333333333444444444455555555556666 120 * 0123456789012345678901234567890123456789012345678901234567890123 121 * 122 * I Page-Invalid Bit: Page is not available for address-translation 123 * P Page-Protection Bit: Store access not possible for page 124 * C Change-bit override: HW is not required to set change bit 125 * 126 * A 64 bit segmenttable entry of S390 has following format: 127 * | P-table origin | TT 128 * 0000000000111111111122222222223333333333444444444455555555556666 129 * 0123456789012345678901234567890123456789012345678901234567890123 130 * 131 * I Segment-Invalid Bit: Segment is not available for address-translation 132 * C Common-Segment Bit: Segment is not private (PoP 3-30) 133 * P Page-Protection Bit: Store access not possible for page 134 * TT Type 00 135 * 136 * A 64 bit region table entry of S390 has following format: 137 * | S-table origin | TF TTTL 138 * 0000000000111111111122222222223333333333444444444455555555556666 139 * 0123456789012345678901234567890123456789012345678901234567890123 140 * 141 * I Segment-Invalid Bit: Segment is not available for address-translation 142 * TT Type 01 143 * TF 144 * TL Table length 145 * 146 * The 64 bit regiontable origin of S390 has following format: 147 * | region table origon | DTTL 148 * 0000000000111111111122222222223333333333444444444455555555556666 149 * 0123456789012345678901234567890123456789012345678901234567890123 150 * 151 * X Space-Switch event: 152 * G Segment-Invalid Bit: 153 * P Private-Space Bit: 154 * S Storage-Alteration: 155 * R Real space 156 * TL Table-Length: 157 * 158 * A storage key has the following format: 159 * | ACC |F|R|C|0| 160 * 0 3 4 5 6 7 161 * ACC: access key 162 * F : fetch protection bit 163 * R : referenced bit 164 * C : changed bit 165 */ 166 167 /* Hardware bits in the page table entry */ 168 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 169 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 170 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 171 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 172 173 /* Software bits in the page table entry */ 174 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 175 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 176 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 177 #define _PAGE_READ 0x010 /* SW pte read bit */ 178 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 179 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 180 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 181 182 #ifdef CONFIG_MEM_SOFT_DIRTY 183 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 184 #else 185 #define _PAGE_SOFT_DIRTY 0x000 186 #endif 187 188 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 189 190 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 191 192 /* Set of bits not changed in pte_modify */ 193 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 194 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 195 196 /* 197 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 198 * HW bit and all SW bits. 199 */ 200 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 201 202 /* 203 * handle_pte_fault uses pte_present and pte_none to find out the pte type 204 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 205 * distinguish present from not-present ptes. It is changed only with the page 206 * table lock held. 207 * 208 * The following table gives the different possible bit combinations for 209 * the pte hardware and software bits in the last 12 bits of a pte 210 * (. unassigned bit, x don't care, t swap type): 211 * 212 * 842100000000 213 * 000084210000 214 * 000000008421 215 * .IR.uswrdy.p 216 * empty .10.00000000 217 * swap .11..ttttt.0 218 * prot-none, clean, old .11.xx0000.1 219 * prot-none, clean, young .11.xx0001.1 220 * prot-none, dirty, old .11.xx0010.1 221 * prot-none, dirty, young .11.xx0011.1 222 * read-only, clean, old .11.xx0100.1 223 * read-only, clean, young .01.xx0101.1 224 * read-only, dirty, old .11.xx0110.1 225 * read-only, dirty, young .01.xx0111.1 226 * read-write, clean, old .11.xx1100.1 227 * read-write, clean, young .01.xx1101.1 228 * read-write, dirty, old .10.xx1110.1 229 * read-write, dirty, young .00.xx1111.1 230 * HW-bits: R read-only, I invalid 231 * SW-bits: p present, y young, d dirty, r read, w write, s special, 232 * u unused, l large 233 * 234 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 235 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 236 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 237 */ 238 239 /* Bits in the segment/region table address-space-control-element */ 240 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 241 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 242 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 243 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 244 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 245 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 246 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 247 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 248 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 249 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 250 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 251 252 /* Bits in the region table entry */ 253 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 254 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 255 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 256 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 257 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 258 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 259 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 260 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 261 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 262 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 263 264 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 265 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 266 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 267 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 268 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 269 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 270 271 #define _REGION3_ENTRY_HARDWARE_BITS 0xfffffffffffff6ffUL 272 #define _REGION3_ENTRY_HARDWARE_BITS_LARGE 0xffffffff8001073cUL 273 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 274 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 275 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 276 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 277 #define _REGION3_ENTRY_WRITE 0x0002 /* SW region write bit */ 278 #define _REGION3_ENTRY_READ 0x0001 /* SW region read bit */ 279 280 #ifdef CONFIG_MEM_SOFT_DIRTY 281 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 282 #else 283 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 284 #endif 285 286 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 287 288 /* Bits in the segment table entry */ 289 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe3fUL 290 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe3cUL 291 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff1073cUL 292 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 293 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 294 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 295 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 296 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 297 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 298 299 #define _SEGMENT_ENTRY (0) 300 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 301 302 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 303 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 304 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 305 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 306 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 307 308 #ifdef CONFIG_MEM_SOFT_DIRTY 309 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 310 #else 311 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 312 #endif 313 314 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 315 #define _PAGE_ENTRIES 256 /* number of page table entries */ 316 317 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 318 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 319 320 #define _REGION1_SHIFT 53 321 #define _REGION2_SHIFT 42 322 #define _REGION3_SHIFT 31 323 #define _SEGMENT_SHIFT 20 324 325 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 326 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 327 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 328 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 329 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 330 331 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 332 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 333 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 334 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 335 336 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 337 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 338 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 339 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 340 341 #define PMD_SHIFT _SEGMENT_SHIFT 342 #define PUD_SHIFT _REGION3_SHIFT 343 #define P4D_SHIFT _REGION2_SHIFT 344 #define PGDIR_SHIFT _REGION1_SHIFT 345 346 #define PMD_SIZE _SEGMENT_SIZE 347 #define PUD_SIZE _REGION3_SIZE 348 #define P4D_SIZE _REGION2_SIZE 349 #define PGDIR_SIZE _REGION1_SIZE 350 351 #define PMD_MASK _SEGMENT_MASK 352 #define PUD_MASK _REGION3_MASK 353 #define P4D_MASK _REGION2_MASK 354 #define PGDIR_MASK _REGION1_MASK 355 356 #define PTRS_PER_PTE _PAGE_ENTRIES 357 #define PTRS_PER_PMD _CRST_ENTRIES 358 #define PTRS_PER_PUD _CRST_ENTRIES 359 #define PTRS_PER_P4D _CRST_ENTRIES 360 #define PTRS_PER_PGD _CRST_ENTRIES 361 362 /* 363 * Segment table and region3 table entry encoding 364 * (R = read-only, I = invalid, y = young bit): 365 * dy..R...I...wr 366 * prot-none, clean, old 00..1...1...00 367 * prot-none, clean, young 01..1...1...00 368 * prot-none, dirty, old 10..1...1...00 369 * prot-none, dirty, young 11..1...1...00 370 * read-only, clean, old 00..1...1...01 371 * read-only, clean, young 01..1...0...01 372 * read-only, dirty, old 10..1...1...01 373 * read-only, dirty, young 11..1...0...01 374 * read-write, clean, old 00..1...1...11 375 * read-write, clean, young 01..1...0...11 376 * read-write, dirty, old 10..0...1...11 377 * read-write, dirty, young 11..0...0...11 378 * The segment table origin is used to distinguish empty (origin==0) from 379 * read-write, old segment table entries (origin!=0) 380 * HW-bits: R read-only, I invalid 381 * SW-bits: y young, d dirty, r read, w write 382 */ 383 384 /* Page status table bits for virtualization */ 385 #define PGSTE_ACC_BITS 0xf000000000000000UL 386 #define PGSTE_FP_BIT 0x0800000000000000UL 387 #define PGSTE_PCL_BIT 0x0080000000000000UL 388 #define PGSTE_HR_BIT 0x0040000000000000UL 389 #define PGSTE_HC_BIT 0x0020000000000000UL 390 #define PGSTE_GR_BIT 0x0004000000000000UL 391 #define PGSTE_GC_BIT 0x0002000000000000UL 392 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 393 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 394 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 395 396 /* Guest Page State used for virtualization */ 397 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 398 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 399 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 400 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 401 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 402 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 403 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 404 405 /* 406 * A user page table pointer has the space-switch-event bit, the 407 * private-space-control bit and the storage-alteration-event-control 408 * bit set. A kernel page table pointer doesn't need them. 409 */ 410 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 411 _ASCE_ALT_EVENT) 412 413 /* 414 * Page protection definitions. 415 */ 416 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 417 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 418 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 419 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 420 _PAGE_INVALID | _PAGE_PROTECT) 421 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 422 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 423 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_INVALID | _PAGE_PROTECT) 425 426 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 427 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 428 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 429 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 430 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 431 _PAGE_PROTECT | _PAGE_NOEXEC) 432 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 433 _PAGE_YOUNG | _PAGE_DIRTY) 434 435 /* 436 * On s390 the page table entry has an invalid bit and a read-only bit. 437 * Read permission implies execute permission and write permission 438 * implies read permission. 439 */ 440 /*xwr*/ 441 442 /* 443 * Segment entry (large page) protection definitions. 444 */ 445 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 446 _SEGMENT_ENTRY_PROTECT) 447 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 448 _SEGMENT_ENTRY_READ | \ 449 _SEGMENT_ENTRY_NOEXEC) 450 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 451 _SEGMENT_ENTRY_READ) 452 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 453 _SEGMENT_ENTRY_WRITE | \ 454 _SEGMENT_ENTRY_NOEXEC) 455 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 456 _SEGMENT_ENTRY_WRITE) 457 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 458 _SEGMENT_ENTRY_LARGE | \ 459 _SEGMENT_ENTRY_READ | \ 460 _SEGMENT_ENTRY_WRITE | \ 461 _SEGMENT_ENTRY_YOUNG | \ 462 _SEGMENT_ENTRY_DIRTY | \ 463 _SEGMENT_ENTRY_NOEXEC) 464 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 465 _SEGMENT_ENTRY_LARGE | \ 466 _SEGMENT_ENTRY_READ | \ 467 _SEGMENT_ENTRY_YOUNG | \ 468 _SEGMENT_ENTRY_PROTECT | \ 469 _SEGMENT_ENTRY_NOEXEC) 470 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 471 _SEGMENT_ENTRY_LARGE | \ 472 _SEGMENT_ENTRY_READ | \ 473 _SEGMENT_ENTRY_WRITE | \ 474 _SEGMENT_ENTRY_YOUNG | \ 475 _SEGMENT_ENTRY_DIRTY) 476 477 /* 478 * Region3 entry (large page) protection definitions. 479 */ 480 481 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 482 _REGION3_ENTRY_LARGE | \ 483 _REGION3_ENTRY_READ | \ 484 _REGION3_ENTRY_WRITE | \ 485 _REGION3_ENTRY_YOUNG | \ 486 _REGION3_ENTRY_DIRTY | \ 487 _REGION_ENTRY_NOEXEC) 488 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 489 _REGION3_ENTRY_LARGE | \ 490 _REGION3_ENTRY_READ | \ 491 _REGION3_ENTRY_YOUNG | \ 492 _REGION_ENTRY_PROTECT | \ 493 _REGION_ENTRY_NOEXEC) 494 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 495 _REGION3_ENTRY_LARGE | \ 496 _REGION3_ENTRY_READ | \ 497 _REGION3_ENTRY_WRITE | \ 498 _REGION3_ENTRY_YOUNG | \ 499 _REGION3_ENTRY_DIRTY) 500 501 static inline bool mm_p4d_folded(struct mm_struct *mm) 502 { 503 return mm->context.asce_limit <= _REGION1_SIZE; 504 } 505 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 506 507 static inline bool mm_pud_folded(struct mm_struct *mm) 508 { 509 return mm->context.asce_limit <= _REGION2_SIZE; 510 } 511 #define mm_pud_folded(mm) mm_pud_folded(mm) 512 513 static inline bool mm_pmd_folded(struct mm_struct *mm) 514 { 515 return mm->context.asce_limit <= _REGION3_SIZE; 516 } 517 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 518 519 static inline int mm_has_pgste(struct mm_struct *mm) 520 { 521 #ifdef CONFIG_PGSTE 522 if (unlikely(mm->context.has_pgste)) 523 return 1; 524 #endif 525 return 0; 526 } 527 528 static inline int mm_is_protected(struct mm_struct *mm) 529 { 530 #ifdef CONFIG_PGSTE 531 if (unlikely(atomic_read(&mm->context.protected_count))) 532 return 1; 533 #endif 534 return 0; 535 } 536 537 static inline int mm_alloc_pgste(struct mm_struct *mm) 538 { 539 #ifdef CONFIG_PGSTE 540 if (unlikely(mm->context.alloc_pgste)) 541 return 1; 542 #endif 543 return 0; 544 } 545 546 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 547 { 548 return __pte(pte_val(pte) & ~pgprot_val(prot)); 549 } 550 551 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 552 { 553 return __pte(pte_val(pte) | pgprot_val(prot)); 554 } 555 556 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 557 { 558 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 559 } 560 561 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 562 { 563 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 564 } 565 566 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 567 { 568 return __pud(pud_val(pud) & ~pgprot_val(prot)); 569 } 570 571 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 572 { 573 return __pud(pud_val(pud) | pgprot_val(prot)); 574 } 575 576 /* 577 * As soon as the guest uses storage keys or enables PV, we deduplicate all 578 * mapped shared zeropages and prevent new shared zeropages from getting 579 * mapped. 580 */ 581 #define mm_forbids_zeropage mm_forbids_zeropage 582 static inline int mm_forbids_zeropage(struct mm_struct *mm) 583 { 584 #ifdef CONFIG_PGSTE 585 if (!mm->context.allow_cow_sharing) 586 return 1; 587 #endif 588 return 0; 589 } 590 591 static inline int mm_uses_skeys(struct mm_struct *mm) 592 { 593 #ifdef CONFIG_PGSTE 594 if (mm->context.uses_skeys) 595 return 1; 596 #endif 597 return 0; 598 } 599 600 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 601 { 602 union register_pair r1 = { .even = old, .odd = new, }; 603 unsigned long address = (unsigned long)ptr | 1; 604 605 asm volatile( 606 " csp %[r1],%[address]" 607 : [r1] "+&d" (r1.pair), "+m" (*ptr) 608 : [address] "d" (address) 609 : "cc"); 610 } 611 612 /** 613 * cspg() - Compare and Swap and Purge (CSPG) 614 * @ptr: Pointer to the value to be exchanged 615 * @old: The expected old value 616 * @new: The new value 617 * 618 * Return: True if compare and swap was successful, otherwise false. 619 */ 620 static inline bool cspg(unsigned long *ptr, unsigned long old, unsigned long new) 621 { 622 union register_pair r1 = { .even = old, .odd = new, }; 623 unsigned long address = (unsigned long)ptr | 1; 624 625 asm volatile( 626 " cspg %[r1],%[address]" 627 : [r1] "+&d" (r1.pair), "+m" (*ptr) 628 : [address] "d" (address) 629 : "cc"); 630 return old == r1.even; 631 } 632 633 #define CRDTE_DTT_PAGE 0x00UL 634 #define CRDTE_DTT_SEGMENT 0x10UL 635 #define CRDTE_DTT_REGION3 0x14UL 636 #define CRDTE_DTT_REGION2 0x18UL 637 #define CRDTE_DTT_REGION1 0x1cUL 638 639 /** 640 * crdte() - Compare and Replace DAT Table Entry 641 * @old: The expected old value 642 * @new: The new value 643 * @table: Pointer to the value to be exchanged 644 * @dtt: Table type of the table to be exchanged 645 * @address: The address mapped by the entry to be replaced 646 * @asce: The ASCE of this entry 647 * 648 * Return: True if compare and replace was successful, otherwise false. 649 */ 650 static inline bool crdte(unsigned long old, unsigned long new, 651 unsigned long *table, unsigned long dtt, 652 unsigned long address, unsigned long asce) 653 { 654 union register_pair r1 = { .even = old, .odd = new, }; 655 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 656 657 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 658 : [r1] "+&d" (r1.pair) 659 : [r2] "d" (r2.pair), [asce] "a" (asce) 660 : "memory", "cc"); 661 return old == r1.even; 662 } 663 664 /* 665 * pgd/p4d/pud/pmd/pte query functions 666 */ 667 static inline int pgd_folded(pgd_t pgd) 668 { 669 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 670 } 671 672 static inline int pgd_present(pgd_t pgd) 673 { 674 if (pgd_folded(pgd)) 675 return 1; 676 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 677 } 678 679 static inline int pgd_none(pgd_t pgd) 680 { 681 if (pgd_folded(pgd)) 682 return 0; 683 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 684 } 685 686 static inline int pgd_bad(pgd_t pgd) 687 { 688 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 689 return 0; 690 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 691 } 692 693 static inline unsigned long pgd_pfn(pgd_t pgd) 694 { 695 unsigned long origin_mask; 696 697 origin_mask = _REGION_ENTRY_ORIGIN; 698 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 699 } 700 701 static inline int p4d_folded(p4d_t p4d) 702 { 703 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 704 } 705 706 static inline int p4d_present(p4d_t p4d) 707 { 708 if (p4d_folded(p4d)) 709 return 1; 710 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 711 } 712 713 static inline int p4d_none(p4d_t p4d) 714 { 715 if (p4d_folded(p4d)) 716 return 0; 717 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 718 } 719 720 static inline unsigned long p4d_pfn(p4d_t p4d) 721 { 722 unsigned long origin_mask; 723 724 origin_mask = _REGION_ENTRY_ORIGIN; 725 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 726 } 727 728 static inline int pud_folded(pud_t pud) 729 { 730 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 731 } 732 733 static inline int pud_present(pud_t pud) 734 { 735 if (pud_folded(pud)) 736 return 1; 737 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 738 } 739 740 static inline int pud_none(pud_t pud) 741 { 742 if (pud_folded(pud)) 743 return 0; 744 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 745 } 746 747 #define pud_leaf pud_leaf 748 static inline bool pud_leaf(pud_t pud) 749 { 750 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 751 return 0; 752 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 753 } 754 755 #define pmd_leaf pmd_leaf 756 static inline bool pmd_leaf(pmd_t pmd) 757 { 758 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 759 } 760 761 static inline int pmd_bad(pmd_t pmd) 762 { 763 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 764 return 1; 765 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 766 } 767 768 static inline int pud_bad(pud_t pud) 769 { 770 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 771 772 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 773 return 1; 774 if (type < _REGION_ENTRY_TYPE_R3) 775 return 0; 776 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 777 } 778 779 static inline int p4d_bad(p4d_t p4d) 780 { 781 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 782 783 if (type > _REGION_ENTRY_TYPE_R2) 784 return 1; 785 if (type < _REGION_ENTRY_TYPE_R2) 786 return 0; 787 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 788 } 789 790 static inline int pmd_present(pmd_t pmd) 791 { 792 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 793 } 794 795 static inline int pmd_none(pmd_t pmd) 796 { 797 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 798 } 799 800 #define pmd_write pmd_write 801 static inline int pmd_write(pmd_t pmd) 802 { 803 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 804 } 805 806 #define pud_write pud_write 807 static inline int pud_write(pud_t pud) 808 { 809 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 810 } 811 812 #define pmd_dirty pmd_dirty 813 static inline int pmd_dirty(pmd_t pmd) 814 { 815 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 816 } 817 818 #define pmd_young pmd_young 819 static inline int pmd_young(pmd_t pmd) 820 { 821 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 822 } 823 824 static inline int pte_present(pte_t pte) 825 { 826 /* Bit pattern: (pte & 0x001) == 0x001 */ 827 return (pte_val(pte) & _PAGE_PRESENT) != 0; 828 } 829 830 static inline int pte_none(pte_t pte) 831 { 832 /* Bit pattern: pte == 0x400 */ 833 return pte_val(pte) == _PAGE_INVALID; 834 } 835 836 static inline int pte_swap(pte_t pte) 837 { 838 /* Bit pattern: (pte & 0x201) == 0x200 */ 839 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 840 == _PAGE_PROTECT; 841 } 842 843 static inline int pte_special(pte_t pte) 844 { 845 return (pte_val(pte) & _PAGE_SPECIAL); 846 } 847 848 #define __HAVE_ARCH_PTE_SAME 849 static inline int pte_same(pte_t a, pte_t b) 850 { 851 return pte_val(a) == pte_val(b); 852 } 853 854 #ifdef CONFIG_NUMA_BALANCING 855 static inline int pte_protnone(pte_t pte) 856 { 857 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 858 } 859 860 static inline int pmd_protnone(pmd_t pmd) 861 { 862 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 863 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 864 } 865 #endif 866 867 static inline int pte_swp_exclusive(pte_t pte) 868 { 869 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 870 } 871 872 static inline pte_t pte_swp_mkexclusive(pte_t pte) 873 { 874 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 875 } 876 877 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 878 { 879 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 880 } 881 882 static inline int pte_soft_dirty(pte_t pte) 883 { 884 return pte_val(pte) & _PAGE_SOFT_DIRTY; 885 } 886 #define pte_swp_soft_dirty pte_soft_dirty 887 888 static inline pte_t pte_mksoft_dirty(pte_t pte) 889 { 890 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 891 } 892 #define pte_swp_mksoft_dirty pte_mksoft_dirty 893 894 static inline pte_t pte_clear_soft_dirty(pte_t pte) 895 { 896 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 897 } 898 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 899 900 static inline int pmd_soft_dirty(pmd_t pmd) 901 { 902 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 903 } 904 905 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 906 { 907 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 908 } 909 910 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 911 { 912 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 913 } 914 915 /* 916 * query functions pte_write/pte_dirty/pte_young only work if 917 * pte_present() is true. Undefined behaviour if not.. 918 */ 919 static inline int pte_write(pte_t pte) 920 { 921 return (pte_val(pte) & _PAGE_WRITE) != 0; 922 } 923 924 static inline int pte_dirty(pte_t pte) 925 { 926 return (pte_val(pte) & _PAGE_DIRTY) != 0; 927 } 928 929 static inline int pte_young(pte_t pte) 930 { 931 return (pte_val(pte) & _PAGE_YOUNG) != 0; 932 } 933 934 #define __HAVE_ARCH_PTE_UNUSED 935 static inline int pte_unused(pte_t pte) 936 { 937 return pte_val(pte) & _PAGE_UNUSED; 938 } 939 940 /* 941 * Extract the pgprot value from the given pte while at the same time making it 942 * usable for kernel address space mappings where fault driven dirty and 943 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 944 * must not be set. 945 */ 946 static inline pgprot_t pte_pgprot(pte_t pte) 947 { 948 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 949 950 if (pte_write(pte)) 951 pte_flags |= pgprot_val(PAGE_KERNEL); 952 else 953 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 954 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 955 956 return __pgprot(pte_flags); 957 } 958 959 /* 960 * pgd/pmd/pte modification functions 961 */ 962 963 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 964 { 965 WRITE_ONCE(*pgdp, pgd); 966 } 967 968 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 969 { 970 WRITE_ONCE(*p4dp, p4d); 971 } 972 973 static inline void set_pud(pud_t *pudp, pud_t pud) 974 { 975 WRITE_ONCE(*pudp, pud); 976 } 977 978 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 979 { 980 WRITE_ONCE(*pmdp, pmd); 981 } 982 983 static inline void set_pte(pte_t *ptep, pte_t pte) 984 { 985 WRITE_ONCE(*ptep, pte); 986 } 987 988 static inline void pgd_clear(pgd_t *pgd) 989 { 990 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 991 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 992 } 993 994 static inline void p4d_clear(p4d_t *p4d) 995 { 996 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 997 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 998 } 999 1000 static inline void pud_clear(pud_t *pud) 1001 { 1002 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1003 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 1004 } 1005 1006 static inline void pmd_clear(pmd_t *pmdp) 1007 { 1008 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1009 } 1010 1011 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 1012 { 1013 set_pte(ptep, __pte(_PAGE_INVALID)); 1014 } 1015 1016 /* 1017 * The following pte modification functions only work if 1018 * pte_present() is true. Undefined behaviour if not.. 1019 */ 1020 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1021 { 1022 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 1023 pte = set_pte_bit(pte, newprot); 1024 /* 1025 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 1026 * has the invalid bit set, clear it again for readable, young pages 1027 */ 1028 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 1029 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1030 /* 1031 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1032 * protection bit set, clear it again for writable, dirty pages 1033 */ 1034 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1035 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1036 return pte; 1037 } 1038 1039 static inline pte_t pte_wrprotect(pte_t pte) 1040 { 1041 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1042 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1043 } 1044 1045 static inline pte_t pte_mkwrite_novma(pte_t pte) 1046 { 1047 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1048 if (pte_val(pte) & _PAGE_DIRTY) 1049 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1050 return pte; 1051 } 1052 1053 static inline pte_t pte_mkclean(pte_t pte) 1054 { 1055 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1056 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1057 } 1058 1059 static inline pte_t pte_mkdirty(pte_t pte) 1060 { 1061 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1062 if (pte_val(pte) & _PAGE_WRITE) 1063 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1064 return pte; 1065 } 1066 1067 static inline pte_t pte_mkold(pte_t pte) 1068 { 1069 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1070 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1071 } 1072 1073 static inline pte_t pte_mkyoung(pte_t pte) 1074 { 1075 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1076 if (pte_val(pte) & _PAGE_READ) 1077 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1078 return pte; 1079 } 1080 1081 static inline pte_t pte_mkspecial(pte_t pte) 1082 { 1083 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1084 } 1085 1086 #ifdef CONFIG_HUGETLB_PAGE 1087 static inline pte_t pte_mkhuge(pte_t pte) 1088 { 1089 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1090 } 1091 #endif 1092 1093 #define IPTE_GLOBAL 0 1094 #define IPTE_LOCAL 1 1095 1096 #define IPTE_NODAT 0x400 1097 #define IPTE_GUEST_ASCE 0x800 1098 1099 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1100 unsigned long opt, unsigned long asce, 1101 int local) 1102 { 1103 unsigned long pto; 1104 1105 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1106 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1107 : "+m" (*ptep) 1108 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1109 [asce] "a" (asce), [m4] "i" (local)); 1110 } 1111 1112 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1113 unsigned long opt, unsigned long asce, 1114 int local) 1115 { 1116 unsigned long pto = __pa(ptep); 1117 1118 if (__builtin_constant_p(opt) && opt == 0) { 1119 /* Invalidation + TLB flush for the pte */ 1120 asm volatile( 1121 " ipte %[r1],%[r2],0,%[m4]" 1122 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1123 [m4] "i" (local)); 1124 return; 1125 } 1126 1127 /* Invalidate ptes with options + TLB flush of the ptes */ 1128 opt = opt | (asce & _ASCE_ORIGIN); 1129 asm volatile( 1130 " ipte %[r1],%[r2],%[r3],%[m4]" 1131 : [r2] "+a" (address), [r3] "+a" (opt) 1132 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1133 } 1134 1135 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1136 pte_t *ptep, int local) 1137 { 1138 unsigned long pto = __pa(ptep); 1139 1140 /* Invalidate a range of ptes + TLB flush of the ptes */ 1141 do { 1142 asm volatile( 1143 " ipte %[r1],%[r2],%[r3],%[m4]" 1144 : [r2] "+a" (address), [r3] "+a" (nr) 1145 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1146 } while (nr != 255); 1147 } 1148 1149 /* 1150 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1151 * both clear the TLB for the unmapped pte. The reason is that 1152 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1153 * to modify an active pte. The sequence is 1154 * 1) ptep_get_and_clear 1155 * 2) set_pte_at 1156 * 3) flush_tlb_range 1157 * On s390 the tlb needs to get flushed with the modification of the pte 1158 * if the pte is active. The only way how this can be implemented is to 1159 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1160 * is a nop. 1161 */ 1162 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1163 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1164 1165 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1166 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1167 unsigned long addr, pte_t *ptep) 1168 { 1169 pte_t pte = *ptep; 1170 1171 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1172 return pte_young(pte); 1173 } 1174 1175 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1176 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1177 unsigned long address, pte_t *ptep) 1178 { 1179 return ptep_test_and_clear_young(vma, address, ptep); 1180 } 1181 1182 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1183 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1184 unsigned long addr, pte_t *ptep) 1185 { 1186 pte_t res; 1187 1188 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1189 /* At this point the reference through the mapping is still present */ 1190 if (mm_is_protected(mm) && pte_present(res)) 1191 uv_convert_from_secure_pte(res); 1192 return res; 1193 } 1194 1195 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1196 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1197 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1198 pte_t *, pte_t, pte_t); 1199 1200 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1201 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1202 unsigned long addr, pte_t *ptep) 1203 { 1204 pte_t res; 1205 1206 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1207 /* At this point the reference through the mapping is still present */ 1208 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1209 uv_convert_from_secure_pte(res); 1210 return res; 1211 } 1212 1213 /* 1214 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1215 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1216 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1217 * cannot be accessed while the batched unmap is running. In this case 1218 * full==1 and a simple pte_clear is enough. See tlb.h. 1219 */ 1220 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1221 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1222 unsigned long addr, 1223 pte_t *ptep, int full) 1224 { 1225 pte_t res; 1226 1227 if (full) { 1228 res = *ptep; 1229 set_pte(ptep, __pte(_PAGE_INVALID)); 1230 } else { 1231 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1232 } 1233 /* Nothing to do */ 1234 if (!mm_is_protected(mm) || !pte_present(res)) 1235 return res; 1236 /* 1237 * At this point the reference through the mapping is still present. 1238 * The notifier should have destroyed all protected vCPUs at this 1239 * point, so the destroy should be successful. 1240 */ 1241 if (full && !uv_destroy_pte(res)) 1242 return res; 1243 /* 1244 * If something went wrong and the page could not be destroyed, or 1245 * if this is not a mm teardown, the slower export is used as 1246 * fallback instead. 1247 */ 1248 uv_convert_from_secure_pte(res); 1249 return res; 1250 } 1251 1252 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1253 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1254 unsigned long addr, pte_t *ptep) 1255 { 1256 pte_t pte = *ptep; 1257 1258 if (pte_write(pte)) 1259 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1260 } 1261 1262 /* 1263 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1264 * bits in the comparison. Those might change e.g. because of dirty and young 1265 * tracking. 1266 */ 1267 static inline int pte_allow_rdp(pte_t old, pte_t new) 1268 { 1269 /* 1270 * Only allow changes from RO to RW 1271 */ 1272 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1273 return 0; 1274 1275 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1276 } 1277 1278 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1279 unsigned long address, 1280 pte_t *ptep) 1281 { 1282 /* 1283 * RDP might not have propagated the PTE protection reset to all CPUs, 1284 * so there could be spurious TLB protection faults. 1285 * NOTE: This will also be called when a racing pagetable update on 1286 * another thread already installed the correct PTE. Both cases cannot 1287 * really be distinguished. 1288 * Therefore, only do the local TLB flush when RDP can be used, and the 1289 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1290 * A local RDP can be used to do the flush. 1291 */ 1292 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1293 __ptep_rdp(address, ptep, 0, 0, 1); 1294 } 1295 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1296 1297 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1298 pte_t new); 1299 1300 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1301 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1302 unsigned long addr, pte_t *ptep, 1303 pte_t entry, int dirty) 1304 { 1305 if (pte_same(*ptep, entry)) 1306 return 0; 1307 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1308 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1309 else 1310 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1311 return 1; 1312 } 1313 1314 /* 1315 * Additional functions to handle KVM guest page tables 1316 */ 1317 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1318 pte_t *ptep, pte_t entry); 1319 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1320 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1321 pte_t *ptep, unsigned long bits); 1322 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1323 pte_t *ptep, int prot, unsigned long bit); 1324 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1325 pte_t *ptep , int reset); 1326 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1327 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1328 pte_t *sptep, pte_t *tptep, pte_t pte); 1329 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1330 1331 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1332 pte_t *ptep); 1333 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1334 unsigned char key, bool nq); 1335 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1336 unsigned char key, unsigned char *oldkey, 1337 bool nq, bool mr, bool mc); 1338 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1339 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1340 unsigned char *key); 1341 1342 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1343 unsigned long bits, unsigned long value); 1344 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1345 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1346 unsigned long *oldpte, unsigned long *oldpgste); 1347 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1348 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1349 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1350 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1351 1352 #define pgprot_writecombine pgprot_writecombine 1353 pgprot_t pgprot_writecombine(pgprot_t prot); 1354 1355 #define pgprot_writethrough pgprot_writethrough 1356 pgprot_t pgprot_writethrough(pgprot_t prot); 1357 1358 #define PFN_PTE_SHIFT PAGE_SHIFT 1359 1360 /* 1361 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1362 * are within the same folio, PMD and VMA. 1363 */ 1364 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1365 pte_t *ptep, pte_t entry, unsigned int nr) 1366 { 1367 if (pte_present(entry)) 1368 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1369 if (mm_has_pgste(mm)) { 1370 for (;;) { 1371 ptep_set_pte_at(mm, addr, ptep, entry); 1372 if (--nr == 0) 1373 break; 1374 ptep++; 1375 entry = __pte(pte_val(entry) + PAGE_SIZE); 1376 addr += PAGE_SIZE; 1377 } 1378 } else { 1379 for (;;) { 1380 set_pte(ptep, entry); 1381 if (--nr == 0) 1382 break; 1383 ptep++; 1384 entry = __pte(pte_val(entry) + PAGE_SIZE); 1385 } 1386 } 1387 } 1388 #define set_ptes set_ptes 1389 1390 /* 1391 * Conversion functions: convert a page and protection to a page entry, 1392 * and a page entry and page directory to the page they refer to. 1393 */ 1394 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1395 { 1396 pte_t __pte; 1397 1398 __pte = __pte(physpage | pgprot_val(pgprot)); 1399 if (!MACHINE_HAS_NX) 1400 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1401 return pte_mkyoung(__pte); 1402 } 1403 1404 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1405 { 1406 unsigned long physpage = page_to_phys(page); 1407 pte_t __pte = mk_pte_phys(physpage, pgprot); 1408 1409 if (pte_write(__pte) && PageDirty(page)) 1410 __pte = pte_mkdirty(__pte); 1411 return __pte; 1412 } 1413 1414 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1415 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1416 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1417 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1418 1419 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1420 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1421 1422 static inline unsigned long pmd_deref(pmd_t pmd) 1423 { 1424 unsigned long origin_mask; 1425 1426 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1427 if (pmd_leaf(pmd)) 1428 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1429 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1430 } 1431 1432 static inline unsigned long pmd_pfn(pmd_t pmd) 1433 { 1434 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1435 } 1436 1437 static inline unsigned long pud_deref(pud_t pud) 1438 { 1439 unsigned long origin_mask; 1440 1441 origin_mask = _REGION_ENTRY_ORIGIN; 1442 if (pud_leaf(pud)) 1443 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1444 return (unsigned long)__va(pud_val(pud) & origin_mask); 1445 } 1446 1447 #define pud_pfn pud_pfn 1448 static inline unsigned long pud_pfn(pud_t pud) 1449 { 1450 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1451 } 1452 1453 /* 1454 * The pgd_offset function *always* adds the index for the top-level 1455 * region/segment table. This is done to get a sequence like the 1456 * following to work: 1457 * pgdp = pgd_offset(current->mm, addr); 1458 * pgd = READ_ONCE(*pgdp); 1459 * p4dp = p4d_offset(&pgd, addr); 1460 * ... 1461 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1462 * only add an index if they dereferenced the pointer. 1463 */ 1464 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1465 { 1466 unsigned long rste; 1467 unsigned int shift; 1468 1469 /* Get the first entry of the top level table */ 1470 rste = pgd_val(*pgd); 1471 /* Pick up the shift from the table type of the first entry */ 1472 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1473 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1474 } 1475 1476 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1477 1478 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1479 { 1480 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1481 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1482 return (p4d_t *) pgdp; 1483 } 1484 #define p4d_offset_lockless p4d_offset_lockless 1485 1486 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1487 { 1488 return p4d_offset_lockless(pgdp, *pgdp, address); 1489 } 1490 1491 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1492 { 1493 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1494 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1495 return (pud_t *) p4dp; 1496 } 1497 #define pud_offset_lockless pud_offset_lockless 1498 1499 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1500 { 1501 return pud_offset_lockless(p4dp, *p4dp, address); 1502 } 1503 #define pud_offset pud_offset 1504 1505 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1506 { 1507 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1508 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1509 return (pmd_t *) pudp; 1510 } 1511 #define pmd_offset_lockless pmd_offset_lockless 1512 1513 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1514 { 1515 return pmd_offset_lockless(pudp, *pudp, address); 1516 } 1517 #define pmd_offset pmd_offset 1518 1519 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1520 { 1521 return (unsigned long) pmd_deref(pmd); 1522 } 1523 1524 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1525 { 1526 return end <= current->mm->context.asce_limit; 1527 } 1528 #define gup_fast_permitted gup_fast_permitted 1529 1530 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1531 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1532 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1533 1534 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1535 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1536 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1537 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1538 1539 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1540 { 1541 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1542 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1543 } 1544 1545 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1546 { 1547 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1548 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1549 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1550 return pmd; 1551 } 1552 1553 static inline pmd_t pmd_mkclean(pmd_t pmd) 1554 { 1555 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1556 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1557 } 1558 1559 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1560 { 1561 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1562 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1563 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1564 return pmd; 1565 } 1566 1567 static inline pud_t pud_wrprotect(pud_t pud) 1568 { 1569 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1570 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1571 } 1572 1573 static inline pud_t pud_mkwrite(pud_t pud) 1574 { 1575 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1576 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1577 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1578 return pud; 1579 } 1580 1581 static inline pud_t pud_mkclean(pud_t pud) 1582 { 1583 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1584 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1585 } 1586 1587 static inline pud_t pud_mkdirty(pud_t pud) 1588 { 1589 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1590 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1591 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1592 return pud; 1593 } 1594 1595 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1596 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1597 { 1598 /* 1599 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1600 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1601 */ 1602 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1603 return pgprot_val(SEGMENT_NONE); 1604 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1605 return pgprot_val(SEGMENT_RO); 1606 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1607 return pgprot_val(SEGMENT_RX); 1608 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1609 return pgprot_val(SEGMENT_RW); 1610 return pgprot_val(SEGMENT_RWX); 1611 } 1612 1613 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1614 { 1615 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1616 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1617 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1618 return pmd; 1619 } 1620 1621 static inline pmd_t pmd_mkold(pmd_t pmd) 1622 { 1623 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1624 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1625 } 1626 1627 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1628 { 1629 unsigned long mask; 1630 1631 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1632 mask |= _SEGMENT_ENTRY_DIRTY; 1633 mask |= _SEGMENT_ENTRY_YOUNG; 1634 mask |= _SEGMENT_ENTRY_LARGE; 1635 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1636 pmd = __pmd(pmd_val(pmd) & mask); 1637 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1638 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1639 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1640 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1641 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1642 return pmd; 1643 } 1644 1645 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1646 { 1647 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1648 } 1649 1650 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1651 1652 static inline void __pmdp_csp(pmd_t *pmdp) 1653 { 1654 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1655 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1656 } 1657 1658 #define IDTE_GLOBAL 0 1659 #define IDTE_LOCAL 1 1660 1661 #define IDTE_PTOA 0x0800 1662 #define IDTE_NODAT 0x1000 1663 #define IDTE_GUEST_ASCE 0x2000 1664 1665 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1666 unsigned long opt, unsigned long asce, 1667 int local) 1668 { 1669 unsigned long sto; 1670 1671 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1672 if (__builtin_constant_p(opt) && opt == 0) { 1673 /* flush without guest asce */ 1674 asm volatile( 1675 " idte %[r1],0,%[r2],%[m4]" 1676 : "+m" (*pmdp) 1677 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1678 [m4] "i" (local) 1679 : "cc" ); 1680 } else { 1681 /* flush with guest asce */ 1682 asm volatile( 1683 " idte %[r1],%[r3],%[r2],%[m4]" 1684 : "+m" (*pmdp) 1685 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1686 [r3] "a" (asce), [m4] "i" (local) 1687 : "cc" ); 1688 } 1689 } 1690 1691 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1692 unsigned long opt, unsigned long asce, 1693 int local) 1694 { 1695 unsigned long r3o; 1696 1697 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1698 r3o |= _ASCE_TYPE_REGION3; 1699 if (__builtin_constant_p(opt) && opt == 0) { 1700 /* flush without guest asce */ 1701 asm volatile( 1702 " idte %[r1],0,%[r2],%[m4]" 1703 : "+m" (*pudp) 1704 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1705 [m4] "i" (local) 1706 : "cc"); 1707 } else { 1708 /* flush with guest asce */ 1709 asm volatile( 1710 " idte %[r1],%[r3],%[r2],%[m4]" 1711 : "+m" (*pudp) 1712 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1713 [r3] "a" (asce), [m4] "i" (local) 1714 : "cc" ); 1715 } 1716 } 1717 1718 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1719 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1720 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1721 1722 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1723 1724 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1725 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1726 pgtable_t pgtable); 1727 1728 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1729 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1730 1731 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1732 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1733 unsigned long addr, pmd_t *pmdp, 1734 pmd_t entry, int dirty) 1735 { 1736 VM_BUG_ON(addr & ~HPAGE_MASK); 1737 1738 entry = pmd_mkyoung(entry); 1739 if (dirty) 1740 entry = pmd_mkdirty(entry); 1741 if (pmd_val(*pmdp) == pmd_val(entry)) 1742 return 0; 1743 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1744 return 1; 1745 } 1746 1747 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1748 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1749 unsigned long addr, pmd_t *pmdp) 1750 { 1751 pmd_t pmd = *pmdp; 1752 1753 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1754 return pmd_young(pmd); 1755 } 1756 1757 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1758 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1759 unsigned long addr, pmd_t *pmdp) 1760 { 1761 VM_BUG_ON(addr & ~HPAGE_MASK); 1762 return pmdp_test_and_clear_young(vma, addr, pmdp); 1763 } 1764 1765 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1766 pmd_t *pmdp, pmd_t entry) 1767 { 1768 if (!MACHINE_HAS_NX) 1769 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1770 set_pmd(pmdp, entry); 1771 } 1772 1773 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1774 { 1775 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1776 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1777 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1778 } 1779 1780 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1781 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1782 unsigned long addr, pmd_t *pmdp) 1783 { 1784 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1785 } 1786 1787 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1788 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1789 unsigned long addr, 1790 pmd_t *pmdp, int full) 1791 { 1792 if (full) { 1793 pmd_t pmd = *pmdp; 1794 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1795 return pmd; 1796 } 1797 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1798 } 1799 1800 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1801 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1802 unsigned long addr, pmd_t *pmdp) 1803 { 1804 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1805 } 1806 1807 #define __HAVE_ARCH_PMDP_INVALIDATE 1808 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1809 unsigned long addr, pmd_t *pmdp) 1810 { 1811 pmd_t pmd; 1812 1813 VM_WARN_ON_ONCE(!pmd_present(*pmdp)); 1814 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1815 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1816 } 1817 1818 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1819 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1820 unsigned long addr, pmd_t *pmdp) 1821 { 1822 pmd_t pmd = *pmdp; 1823 1824 if (pmd_write(pmd)) 1825 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1826 } 1827 1828 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1829 unsigned long address, 1830 pmd_t *pmdp) 1831 { 1832 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1833 } 1834 #define pmdp_collapse_flush pmdp_collapse_flush 1835 1836 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1837 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1838 1839 static inline int pmd_trans_huge(pmd_t pmd) 1840 { 1841 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1842 } 1843 1844 #define has_transparent_hugepage has_transparent_hugepage 1845 static inline int has_transparent_hugepage(void) 1846 { 1847 return MACHINE_HAS_EDAT1 ? 1 : 0; 1848 } 1849 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1850 1851 /* 1852 * 64 bit swap entry format: 1853 * A page-table entry has some bits we have to treat in a special way. 1854 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1855 * as invalid. 1856 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1857 * | offset |E11XX|type |S0| 1858 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1859 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1860 * 1861 * Bits 0-51 store the offset. 1862 * Bit 52 (E) is used to remember PG_anon_exclusive. 1863 * Bits 57-61 store the type. 1864 * Bit 62 (S) is used for softdirty tracking. 1865 * Bits 55 and 56 (X) are unused. 1866 */ 1867 1868 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1869 #define __SWP_OFFSET_SHIFT 12 1870 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1871 #define __SWP_TYPE_SHIFT 2 1872 1873 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1874 { 1875 unsigned long pteval; 1876 1877 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1878 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1879 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1880 return __pte(pteval); 1881 } 1882 1883 static inline unsigned long __swp_type(swp_entry_t entry) 1884 { 1885 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1886 } 1887 1888 static inline unsigned long __swp_offset(swp_entry_t entry) 1889 { 1890 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1891 } 1892 1893 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1894 { 1895 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1896 } 1897 1898 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1899 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1900 1901 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1902 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1903 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1904 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1905 extern void vmem_unmap_4k_page(unsigned long addr); 1906 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1907 extern int s390_enable_sie(void); 1908 extern int s390_enable_skey(void); 1909 extern void s390_reset_cmma(struct mm_struct *mm); 1910 1911 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1912 #define HAVE_ARCH_UNMAPPED_AREA 1913 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1914 1915 #define pmd_pgtable(pmd) \ 1916 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1917 1918 #endif /* _S390_PAGE_H */ 1919