1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/ctlreg.h> 22 #include <asm/bug.h> 23 #include <asm/page.h> 24 #include <asm/uv.h> 25 26 extern pgd_t swapper_pg_dir[]; 27 extern pgd_t invalid_pg_dir[]; 28 extern void paging_init(void); 29 extern struct ctlreg s390_invalid_asce; 30 31 enum { 32 PG_DIRECT_MAP_4K = 0, 33 PG_DIRECT_MAP_1M, 34 PG_DIRECT_MAP_2G, 35 PG_DIRECT_MAP_MAX 36 }; 37 38 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 39 40 static inline void update_page_count(int level, long count) 41 { 42 if (IS_ENABLED(CONFIG_PROC_FS)) 43 atomic_long_add(count, &direct_pages_count[level]); 44 } 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 52 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 53 54 /* 55 * ZERO_PAGE is a global shared page that is always zero; used 56 * for zero-mapped memory areas etc.. 57 */ 58 59 extern unsigned long empty_zero_page; 60 extern unsigned long zero_page_mask; 61 62 #define ZERO_PAGE(vaddr) \ 63 (virt_to_page((void *)(empty_zero_page + \ 64 (((unsigned long)(vaddr)) &zero_page_mask)))) 65 #define __HAVE_COLOR_ZERO_PAGE 66 67 /* TODO: s390 cannot support io_remap_pfn_range... */ 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 71 #define pmd_ERROR(e) \ 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 73 #define pud_ERROR(e) \ 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 75 #define p4d_ERROR(e) \ 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 77 #define pgd_ERROR(e) \ 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 79 80 /* 81 * The vmalloc and module area will always be on the topmost area of the 82 * kernel mapping. 512GB are reserved for vmalloc by default. 83 * At the top of the vmalloc area a 2GB area is reserved where modules 84 * will reside. That makes sure that inter module branches always 85 * happen without trampolines and in addition the placement within a 86 * 2GB frame is branch prediction unit friendly. 87 */ 88 extern unsigned long __bootdata_preserved(VMALLOC_START); 89 extern unsigned long __bootdata_preserved(VMALLOC_END); 90 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 91 extern struct page *__bootdata_preserved(vmemmap); 92 extern unsigned long __bootdata_preserved(vmemmap_size); 93 94 extern unsigned long __bootdata_preserved(MODULES_VADDR); 95 extern unsigned long __bootdata_preserved(MODULES_END); 96 #define MODULES_VADDR MODULES_VADDR 97 #define MODULES_END MODULES_END 98 #define MODULES_LEN (1UL << 31) 99 100 static inline int is_module_addr(void *addr) 101 { 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 103 if (addr < (void *)MODULES_VADDR) 104 return 0; 105 if (addr > (void *)MODULES_END) 106 return 0; 107 return 1; 108 } 109 110 #ifdef CONFIG_RANDOMIZE_BASE 111 #define KASLR_LEN (1UL << 31) 112 #else 113 #define KASLR_LEN 0UL 114 #endif 115 116 /* 117 * A 64 bit pagetable entry of S390 has following format: 118 * | PFRA |0IPC| OS | 119 * 0000000000111111111122222222223333333333444444444455555555556666 120 * 0123456789012345678901234567890123456789012345678901234567890123 121 * 122 * I Page-Invalid Bit: Page is not available for address-translation 123 * P Page-Protection Bit: Store access not possible for page 124 * C Change-bit override: HW is not required to set change bit 125 * 126 * A 64 bit segmenttable entry of S390 has following format: 127 * | P-table origin | TT 128 * 0000000000111111111122222222223333333333444444444455555555556666 129 * 0123456789012345678901234567890123456789012345678901234567890123 130 * 131 * I Segment-Invalid Bit: Segment is not available for address-translation 132 * C Common-Segment Bit: Segment is not private (PoP 3-30) 133 * P Page-Protection Bit: Store access not possible for page 134 * TT Type 00 135 * 136 * A 64 bit region table entry of S390 has following format: 137 * | S-table origin | TF TTTL 138 * 0000000000111111111122222222223333333333444444444455555555556666 139 * 0123456789012345678901234567890123456789012345678901234567890123 140 * 141 * I Segment-Invalid Bit: Segment is not available for address-translation 142 * TT Type 01 143 * TF 144 * TL Table length 145 * 146 * The 64 bit regiontable origin of S390 has following format: 147 * | region table origon | DTTL 148 * 0000000000111111111122222222223333333333444444444455555555556666 149 * 0123456789012345678901234567890123456789012345678901234567890123 150 * 151 * X Space-Switch event: 152 * G Segment-Invalid Bit: 153 * P Private-Space Bit: 154 * S Storage-Alteration: 155 * R Real space 156 * TL Table-Length: 157 * 158 * A storage key has the following format: 159 * | ACC |F|R|C|0| 160 * 0 3 4 5 6 7 161 * ACC: access key 162 * F : fetch protection bit 163 * R : referenced bit 164 * C : changed bit 165 */ 166 167 /* Hardware bits in the page table entry */ 168 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 169 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 170 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 171 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 172 173 /* Software bits in the page table entry */ 174 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 175 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 176 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 177 #define _PAGE_READ 0x010 /* SW pte read bit */ 178 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 179 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 180 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 181 182 #ifdef CONFIG_MEM_SOFT_DIRTY 183 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 184 #else 185 #define _PAGE_SOFT_DIRTY 0x000 186 #endif 187 188 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 189 190 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 191 192 /* Set of bits not changed in pte_modify */ 193 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 194 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 195 196 /* 197 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 198 * HW bit and all SW bits. 199 */ 200 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 201 202 /* 203 * handle_pte_fault uses pte_present and pte_none to find out the pte type 204 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 205 * distinguish present from not-present ptes. It is changed only with the page 206 * table lock held. 207 * 208 * The following table gives the different possible bit combinations for 209 * the pte hardware and software bits in the last 12 bits of a pte 210 * (. unassigned bit, x don't care, t swap type): 211 * 212 * 842100000000 213 * 000084210000 214 * 000000008421 215 * .IR.uswrdy.p 216 * empty .10.00000000 217 * swap .11..ttttt.0 218 * prot-none, clean, old .11.xx0000.1 219 * prot-none, clean, young .11.xx0001.1 220 * prot-none, dirty, old .11.xx0010.1 221 * prot-none, dirty, young .11.xx0011.1 222 * read-only, clean, old .11.xx0100.1 223 * read-only, clean, young .01.xx0101.1 224 * read-only, dirty, old .11.xx0110.1 225 * read-only, dirty, young .01.xx0111.1 226 * read-write, clean, old .11.xx1100.1 227 * read-write, clean, young .01.xx1101.1 228 * read-write, dirty, old .10.xx1110.1 229 * read-write, dirty, young .00.xx1111.1 230 * HW-bits: R read-only, I invalid 231 * SW-bits: p present, y young, d dirty, r read, w write, s special, 232 * u unused, l large 233 * 234 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 235 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 236 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 237 */ 238 239 /* Bits in the segment/region table address-space-control-element */ 240 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 241 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 242 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 243 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 244 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 245 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 246 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 247 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 248 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 249 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 250 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 251 252 /* Bits in the region table entry */ 253 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 254 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 255 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 256 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 257 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 258 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 259 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 260 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 261 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 262 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 263 264 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 265 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 266 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 267 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 268 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 269 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 270 271 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 272 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 273 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 274 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 275 #define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */ 276 #define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */ 277 278 #ifdef CONFIG_MEM_SOFT_DIRTY 279 #define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */ 280 #else 281 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 282 #endif 283 284 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 285 286 /* Bits in the segment table entry */ 287 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL 288 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL 289 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL 290 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 291 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 292 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 293 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 294 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 295 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 296 297 #define _SEGMENT_ENTRY (0) 298 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 299 300 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 301 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 302 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 303 #define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */ 304 #define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */ 305 306 #ifdef CONFIG_MEM_SOFT_DIRTY 307 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */ 308 #else 309 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 310 #endif 311 312 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 313 #define _PAGE_ENTRIES 256 /* number of page table entries */ 314 315 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 316 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 317 318 #define _REGION1_SHIFT 53 319 #define _REGION2_SHIFT 42 320 #define _REGION3_SHIFT 31 321 #define _SEGMENT_SHIFT 20 322 323 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 324 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 325 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 326 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 327 #define _PAGE_INDEX (0xffUL << _PAGE_SHIFT) 328 329 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 330 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 331 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 332 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 333 334 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 335 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 336 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 337 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 338 339 #define PMD_SHIFT _SEGMENT_SHIFT 340 #define PUD_SHIFT _REGION3_SHIFT 341 #define P4D_SHIFT _REGION2_SHIFT 342 #define PGDIR_SHIFT _REGION1_SHIFT 343 344 #define PMD_SIZE _SEGMENT_SIZE 345 #define PUD_SIZE _REGION3_SIZE 346 #define P4D_SIZE _REGION2_SIZE 347 #define PGDIR_SIZE _REGION1_SIZE 348 349 #define PMD_MASK _SEGMENT_MASK 350 #define PUD_MASK _REGION3_MASK 351 #define P4D_MASK _REGION2_MASK 352 #define PGDIR_MASK _REGION1_MASK 353 354 #define PTRS_PER_PTE _PAGE_ENTRIES 355 #define PTRS_PER_PMD _CRST_ENTRIES 356 #define PTRS_PER_PUD _CRST_ENTRIES 357 #define PTRS_PER_P4D _CRST_ENTRIES 358 #define PTRS_PER_PGD _CRST_ENTRIES 359 360 /* 361 * Segment table and region3 table entry encoding 362 * (R = read-only, I = invalid, y = young bit): 363 * dy..R...I...wr 364 * prot-none, clean, old 00..1...1...00 365 * prot-none, clean, young 01..1...1...00 366 * prot-none, dirty, old 10..1...1...00 367 * prot-none, dirty, young 11..1...1...00 368 * read-only, clean, old 00..1...1...01 369 * read-only, clean, young 01..1...0...01 370 * read-only, dirty, old 10..1...1...01 371 * read-only, dirty, young 11..1...0...01 372 * read-write, clean, old 00..1...1...11 373 * read-write, clean, young 01..1...0...11 374 * read-write, dirty, old 10..0...1...11 375 * read-write, dirty, young 11..0...0...11 376 * The segment table origin is used to distinguish empty (origin==0) from 377 * read-write, old segment table entries (origin!=0) 378 * HW-bits: R read-only, I invalid 379 * SW-bits: y young, d dirty, r read, w write 380 */ 381 382 /* Page status table bits for virtualization */ 383 #define PGSTE_ACC_BITS 0xf000000000000000UL 384 #define PGSTE_FP_BIT 0x0800000000000000UL 385 #define PGSTE_PCL_BIT 0x0080000000000000UL 386 #define PGSTE_HR_BIT 0x0040000000000000UL 387 #define PGSTE_HC_BIT 0x0020000000000000UL 388 #define PGSTE_GR_BIT 0x0004000000000000UL 389 #define PGSTE_GC_BIT 0x0002000000000000UL 390 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 391 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 392 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 393 394 /* Guest Page State used for virtualization */ 395 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 396 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 397 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 398 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 399 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 400 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 401 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 402 403 /* 404 * A user page table pointer has the space-switch-event bit, the 405 * private-space-control bit and the storage-alteration-event-control 406 * bit set. A kernel page table pointer doesn't need them. 407 */ 408 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 409 _ASCE_ALT_EVENT) 410 411 /* 412 * Page protection definitions. 413 */ 414 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 415 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 416 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 417 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 418 _PAGE_INVALID | _PAGE_PROTECT) 419 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 420 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 421 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 422 _PAGE_INVALID | _PAGE_PROTECT) 423 424 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 425 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 426 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 427 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 428 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 429 _PAGE_PROTECT | _PAGE_NOEXEC) 430 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 431 _PAGE_YOUNG | _PAGE_DIRTY) 432 433 /* 434 * On s390 the page table entry has an invalid bit and a read-only bit. 435 * Read permission implies execute permission and write permission 436 * implies read permission. 437 */ 438 /*xwr*/ 439 440 /* 441 * Segment entry (large page) protection definitions. 442 */ 443 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \ 444 _SEGMENT_ENTRY_PROTECT) 445 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \ 446 _SEGMENT_ENTRY_READ | \ 447 _SEGMENT_ENTRY_NOEXEC) 448 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \ 449 _SEGMENT_ENTRY_READ) 450 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \ 451 _SEGMENT_ENTRY_WRITE | \ 452 _SEGMENT_ENTRY_NOEXEC) 453 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \ 454 _SEGMENT_ENTRY_WRITE) 455 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 456 _SEGMENT_ENTRY_LARGE | \ 457 _SEGMENT_ENTRY_READ | \ 458 _SEGMENT_ENTRY_WRITE | \ 459 _SEGMENT_ENTRY_YOUNG | \ 460 _SEGMENT_ENTRY_DIRTY | \ 461 _SEGMENT_ENTRY_NOEXEC) 462 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 463 _SEGMENT_ENTRY_LARGE | \ 464 _SEGMENT_ENTRY_READ | \ 465 _SEGMENT_ENTRY_YOUNG | \ 466 _SEGMENT_ENTRY_PROTECT | \ 467 _SEGMENT_ENTRY_NOEXEC) 468 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 469 _SEGMENT_ENTRY_LARGE | \ 470 _SEGMENT_ENTRY_READ | \ 471 _SEGMENT_ENTRY_WRITE | \ 472 _SEGMENT_ENTRY_YOUNG | \ 473 _SEGMENT_ENTRY_DIRTY) 474 475 /* 476 * Region3 entry (large page) protection definitions. 477 */ 478 479 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 480 _REGION3_ENTRY_LARGE | \ 481 _REGION3_ENTRY_READ | \ 482 _REGION3_ENTRY_WRITE | \ 483 _REGION3_ENTRY_YOUNG | \ 484 _REGION3_ENTRY_DIRTY | \ 485 _REGION_ENTRY_NOEXEC) 486 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 487 _REGION3_ENTRY_LARGE | \ 488 _REGION3_ENTRY_READ | \ 489 _REGION3_ENTRY_YOUNG | \ 490 _REGION_ENTRY_PROTECT | \ 491 _REGION_ENTRY_NOEXEC) 492 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 493 _REGION3_ENTRY_LARGE | \ 494 _REGION3_ENTRY_READ | \ 495 _REGION3_ENTRY_WRITE | \ 496 _REGION3_ENTRY_YOUNG | \ 497 _REGION3_ENTRY_DIRTY) 498 499 static inline bool mm_p4d_folded(struct mm_struct *mm) 500 { 501 return mm->context.asce_limit <= _REGION1_SIZE; 502 } 503 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 504 505 static inline bool mm_pud_folded(struct mm_struct *mm) 506 { 507 return mm->context.asce_limit <= _REGION2_SIZE; 508 } 509 #define mm_pud_folded(mm) mm_pud_folded(mm) 510 511 static inline bool mm_pmd_folded(struct mm_struct *mm) 512 { 513 return mm->context.asce_limit <= _REGION3_SIZE; 514 } 515 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 516 517 static inline int mm_has_pgste(struct mm_struct *mm) 518 { 519 #ifdef CONFIG_PGSTE 520 if (unlikely(mm->context.has_pgste)) 521 return 1; 522 #endif 523 return 0; 524 } 525 526 static inline int mm_is_protected(struct mm_struct *mm) 527 { 528 #ifdef CONFIG_PGSTE 529 if (unlikely(atomic_read(&mm->context.protected_count))) 530 return 1; 531 #endif 532 return 0; 533 } 534 535 static inline int mm_alloc_pgste(struct mm_struct *mm) 536 { 537 #ifdef CONFIG_PGSTE 538 if (unlikely(mm->context.alloc_pgste)) 539 return 1; 540 #endif 541 return 0; 542 } 543 544 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 545 { 546 return __pte(pte_val(pte) & ~pgprot_val(prot)); 547 } 548 549 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 550 { 551 return __pte(pte_val(pte) | pgprot_val(prot)); 552 } 553 554 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 555 { 556 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 557 } 558 559 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 560 { 561 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 562 } 563 564 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 565 { 566 return __pud(pud_val(pud) & ~pgprot_val(prot)); 567 } 568 569 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 570 { 571 return __pud(pud_val(pud) | pgprot_val(prot)); 572 } 573 574 /* 575 * As soon as the guest uses storage keys or enables PV, we deduplicate all 576 * mapped shared zeropages and prevent new shared zeropages from getting 577 * mapped. 578 */ 579 #define mm_forbids_zeropage mm_forbids_zeropage 580 static inline int mm_forbids_zeropage(struct mm_struct *mm) 581 { 582 #ifdef CONFIG_PGSTE 583 if (!mm->context.allow_cow_sharing) 584 return 1; 585 #endif 586 return 0; 587 } 588 589 static inline int mm_uses_skeys(struct mm_struct *mm) 590 { 591 #ifdef CONFIG_PGSTE 592 if (mm->context.uses_skeys) 593 return 1; 594 #endif 595 return 0; 596 } 597 598 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 599 { 600 union register_pair r1 = { .even = old, .odd = new, }; 601 unsigned long address = (unsigned long)ptr | 1; 602 603 asm volatile( 604 " csp %[r1],%[address]" 605 : [r1] "+&d" (r1.pair), "+m" (*ptr) 606 : [address] "d" (address) 607 : "cc"); 608 } 609 610 static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new) 611 { 612 union register_pair r1 = { .even = old, .odd = new, }; 613 unsigned long address = (unsigned long)ptr | 1; 614 615 asm volatile( 616 " cspg %[r1],%[address]" 617 : [r1] "+&d" (r1.pair), "+m" (*ptr) 618 : [address] "d" (address) 619 : "cc"); 620 } 621 622 #define CRDTE_DTT_PAGE 0x00UL 623 #define CRDTE_DTT_SEGMENT 0x10UL 624 #define CRDTE_DTT_REGION3 0x14UL 625 #define CRDTE_DTT_REGION2 0x18UL 626 #define CRDTE_DTT_REGION1 0x1cUL 627 628 static inline void crdte(unsigned long old, unsigned long new, 629 unsigned long *table, unsigned long dtt, 630 unsigned long address, unsigned long asce) 631 { 632 union register_pair r1 = { .even = old, .odd = new, }; 633 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 634 635 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 636 : [r1] "+&d" (r1.pair) 637 : [r2] "d" (r2.pair), [asce] "a" (asce) 638 : "memory", "cc"); 639 } 640 641 /* 642 * pgd/p4d/pud/pmd/pte query functions 643 */ 644 static inline int pgd_folded(pgd_t pgd) 645 { 646 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 647 } 648 649 static inline int pgd_present(pgd_t pgd) 650 { 651 if (pgd_folded(pgd)) 652 return 1; 653 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 654 } 655 656 static inline int pgd_none(pgd_t pgd) 657 { 658 if (pgd_folded(pgd)) 659 return 0; 660 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 661 } 662 663 static inline int pgd_bad(pgd_t pgd) 664 { 665 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 666 return 0; 667 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 668 } 669 670 static inline unsigned long pgd_pfn(pgd_t pgd) 671 { 672 unsigned long origin_mask; 673 674 origin_mask = _REGION_ENTRY_ORIGIN; 675 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 676 } 677 678 static inline int p4d_folded(p4d_t p4d) 679 { 680 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 681 } 682 683 static inline int p4d_present(p4d_t p4d) 684 { 685 if (p4d_folded(p4d)) 686 return 1; 687 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 688 } 689 690 static inline int p4d_none(p4d_t p4d) 691 { 692 if (p4d_folded(p4d)) 693 return 0; 694 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 695 } 696 697 static inline unsigned long p4d_pfn(p4d_t p4d) 698 { 699 unsigned long origin_mask; 700 701 origin_mask = _REGION_ENTRY_ORIGIN; 702 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 703 } 704 705 static inline int pud_folded(pud_t pud) 706 { 707 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 708 } 709 710 static inline int pud_present(pud_t pud) 711 { 712 if (pud_folded(pud)) 713 return 1; 714 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 715 } 716 717 static inline int pud_none(pud_t pud) 718 { 719 if (pud_folded(pud)) 720 return 0; 721 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 722 } 723 724 #define pud_leaf pud_leaf 725 static inline bool pud_leaf(pud_t pud) 726 { 727 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 728 return 0; 729 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 730 } 731 732 #define pmd_leaf pmd_leaf 733 static inline bool pmd_leaf(pmd_t pmd) 734 { 735 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0; 736 } 737 738 static inline int pmd_bad(pmd_t pmd) 739 { 740 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 741 return 1; 742 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 743 } 744 745 static inline int pud_bad(pud_t pud) 746 { 747 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 748 749 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 750 return 1; 751 if (type < _REGION_ENTRY_TYPE_R3) 752 return 0; 753 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 754 } 755 756 static inline int p4d_bad(p4d_t p4d) 757 { 758 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 759 760 if (type > _REGION_ENTRY_TYPE_R2) 761 return 1; 762 if (type < _REGION_ENTRY_TYPE_R2) 763 return 0; 764 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 765 } 766 767 static inline int pmd_present(pmd_t pmd) 768 { 769 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY; 770 } 771 772 static inline int pmd_none(pmd_t pmd) 773 { 774 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 775 } 776 777 #define pmd_write pmd_write 778 static inline int pmd_write(pmd_t pmd) 779 { 780 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 781 } 782 783 #define pud_write pud_write 784 static inline int pud_write(pud_t pud) 785 { 786 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 787 } 788 789 #define pmd_dirty pmd_dirty 790 static inline int pmd_dirty(pmd_t pmd) 791 { 792 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 793 } 794 795 #define pmd_young pmd_young 796 static inline int pmd_young(pmd_t pmd) 797 { 798 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 799 } 800 801 static inline int pte_present(pte_t pte) 802 { 803 /* Bit pattern: (pte & 0x001) == 0x001 */ 804 return (pte_val(pte) & _PAGE_PRESENT) != 0; 805 } 806 807 static inline int pte_none(pte_t pte) 808 { 809 /* Bit pattern: pte == 0x400 */ 810 return pte_val(pte) == _PAGE_INVALID; 811 } 812 813 static inline int pte_swap(pte_t pte) 814 { 815 /* Bit pattern: (pte & 0x201) == 0x200 */ 816 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 817 == _PAGE_PROTECT; 818 } 819 820 static inline int pte_special(pte_t pte) 821 { 822 return (pte_val(pte) & _PAGE_SPECIAL); 823 } 824 825 #define __HAVE_ARCH_PTE_SAME 826 static inline int pte_same(pte_t a, pte_t b) 827 { 828 return pte_val(a) == pte_val(b); 829 } 830 831 #ifdef CONFIG_NUMA_BALANCING 832 static inline int pte_protnone(pte_t pte) 833 { 834 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 835 } 836 837 static inline int pmd_protnone(pmd_t pmd) 838 { 839 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 840 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 841 } 842 #endif 843 844 static inline int pte_swp_exclusive(pte_t pte) 845 { 846 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 847 } 848 849 static inline pte_t pte_swp_mkexclusive(pte_t pte) 850 { 851 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 852 } 853 854 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 855 { 856 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 857 } 858 859 static inline int pte_soft_dirty(pte_t pte) 860 { 861 return pte_val(pte) & _PAGE_SOFT_DIRTY; 862 } 863 #define pte_swp_soft_dirty pte_soft_dirty 864 865 static inline pte_t pte_mksoft_dirty(pte_t pte) 866 { 867 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 868 } 869 #define pte_swp_mksoft_dirty pte_mksoft_dirty 870 871 static inline pte_t pte_clear_soft_dirty(pte_t pte) 872 { 873 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 874 } 875 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 876 877 static inline int pmd_soft_dirty(pmd_t pmd) 878 { 879 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 880 } 881 882 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 883 { 884 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 885 } 886 887 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 888 { 889 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 890 } 891 892 /* 893 * query functions pte_write/pte_dirty/pte_young only work if 894 * pte_present() is true. Undefined behaviour if not.. 895 */ 896 static inline int pte_write(pte_t pte) 897 { 898 return (pte_val(pte) & _PAGE_WRITE) != 0; 899 } 900 901 static inline int pte_dirty(pte_t pte) 902 { 903 return (pte_val(pte) & _PAGE_DIRTY) != 0; 904 } 905 906 static inline int pte_young(pte_t pte) 907 { 908 return (pte_val(pte) & _PAGE_YOUNG) != 0; 909 } 910 911 #define __HAVE_ARCH_PTE_UNUSED 912 static inline int pte_unused(pte_t pte) 913 { 914 return pte_val(pte) & _PAGE_UNUSED; 915 } 916 917 /* 918 * Extract the pgprot value from the given pte while at the same time making it 919 * usable for kernel address space mappings where fault driven dirty and 920 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 921 * must not be set. 922 */ 923 static inline pgprot_t pte_pgprot(pte_t pte) 924 { 925 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 926 927 if (pte_write(pte)) 928 pte_flags |= pgprot_val(PAGE_KERNEL); 929 else 930 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 931 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 932 933 return __pgprot(pte_flags); 934 } 935 936 /* 937 * pgd/pmd/pte modification functions 938 */ 939 940 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 941 { 942 WRITE_ONCE(*pgdp, pgd); 943 } 944 945 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 946 { 947 WRITE_ONCE(*p4dp, p4d); 948 } 949 950 static inline void set_pud(pud_t *pudp, pud_t pud) 951 { 952 WRITE_ONCE(*pudp, pud); 953 } 954 955 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 956 { 957 WRITE_ONCE(*pmdp, pmd); 958 } 959 960 static inline void set_pte(pte_t *ptep, pte_t pte) 961 { 962 WRITE_ONCE(*ptep, pte); 963 } 964 965 static inline void pgd_clear(pgd_t *pgd) 966 { 967 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 968 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 969 } 970 971 static inline void p4d_clear(p4d_t *p4d) 972 { 973 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 974 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 975 } 976 977 static inline void pud_clear(pud_t *pud) 978 { 979 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 980 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 981 } 982 983 static inline void pmd_clear(pmd_t *pmdp) 984 { 985 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 986 } 987 988 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 989 { 990 set_pte(ptep, __pte(_PAGE_INVALID)); 991 } 992 993 /* 994 * The following pte modification functions only work if 995 * pte_present() is true. Undefined behaviour if not.. 996 */ 997 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 998 { 999 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 1000 pte = set_pte_bit(pte, newprot); 1001 /* 1002 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 1003 * has the invalid bit set, clear it again for readable, young pages 1004 */ 1005 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 1006 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1007 /* 1008 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1009 * protection bit set, clear it again for writable, dirty pages 1010 */ 1011 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1012 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1013 return pte; 1014 } 1015 1016 static inline pte_t pte_wrprotect(pte_t pte) 1017 { 1018 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1019 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1020 } 1021 1022 static inline pte_t pte_mkwrite_novma(pte_t pte) 1023 { 1024 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1025 if (pte_val(pte) & _PAGE_DIRTY) 1026 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1027 return pte; 1028 } 1029 1030 static inline pte_t pte_mkclean(pte_t pte) 1031 { 1032 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1033 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1034 } 1035 1036 static inline pte_t pte_mkdirty(pte_t pte) 1037 { 1038 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1039 if (pte_val(pte) & _PAGE_WRITE) 1040 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1041 return pte; 1042 } 1043 1044 static inline pte_t pte_mkold(pte_t pte) 1045 { 1046 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1047 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1048 } 1049 1050 static inline pte_t pte_mkyoung(pte_t pte) 1051 { 1052 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1053 if (pte_val(pte) & _PAGE_READ) 1054 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1055 return pte; 1056 } 1057 1058 static inline pte_t pte_mkspecial(pte_t pte) 1059 { 1060 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1061 } 1062 1063 #ifdef CONFIG_HUGETLB_PAGE 1064 static inline pte_t pte_mkhuge(pte_t pte) 1065 { 1066 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1067 } 1068 #endif 1069 1070 #define IPTE_GLOBAL 0 1071 #define IPTE_LOCAL 1 1072 1073 #define IPTE_NODAT 0x400 1074 #define IPTE_GUEST_ASCE 0x800 1075 1076 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1077 unsigned long opt, unsigned long asce, 1078 int local) 1079 { 1080 unsigned long pto; 1081 1082 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1083 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1084 : "+m" (*ptep) 1085 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1086 [asce] "a" (asce), [m4] "i" (local)); 1087 } 1088 1089 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1090 unsigned long opt, unsigned long asce, 1091 int local) 1092 { 1093 unsigned long pto = __pa(ptep); 1094 1095 if (__builtin_constant_p(opt) && opt == 0) { 1096 /* Invalidation + TLB flush for the pte */ 1097 asm volatile( 1098 " ipte %[r1],%[r2],0,%[m4]" 1099 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1100 [m4] "i" (local)); 1101 return; 1102 } 1103 1104 /* Invalidate ptes with options + TLB flush of the ptes */ 1105 opt = opt | (asce & _ASCE_ORIGIN); 1106 asm volatile( 1107 " ipte %[r1],%[r2],%[r3],%[m4]" 1108 : [r2] "+a" (address), [r3] "+a" (opt) 1109 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1110 } 1111 1112 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1113 pte_t *ptep, int local) 1114 { 1115 unsigned long pto = __pa(ptep); 1116 1117 /* Invalidate a range of ptes + TLB flush of the ptes */ 1118 do { 1119 asm volatile( 1120 " ipte %[r1],%[r2],%[r3],%[m4]" 1121 : [r2] "+a" (address), [r3] "+a" (nr) 1122 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1123 } while (nr != 255); 1124 } 1125 1126 /* 1127 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1128 * both clear the TLB for the unmapped pte. The reason is that 1129 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1130 * to modify an active pte. The sequence is 1131 * 1) ptep_get_and_clear 1132 * 2) set_pte_at 1133 * 3) flush_tlb_range 1134 * On s390 the tlb needs to get flushed with the modification of the pte 1135 * if the pte is active. The only way how this can be implemented is to 1136 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1137 * is a nop. 1138 */ 1139 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1140 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1141 1142 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1143 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1144 unsigned long addr, pte_t *ptep) 1145 { 1146 pte_t pte = *ptep; 1147 1148 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1149 return pte_young(pte); 1150 } 1151 1152 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1153 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1154 unsigned long address, pte_t *ptep) 1155 { 1156 return ptep_test_and_clear_young(vma, address, ptep); 1157 } 1158 1159 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1160 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1161 unsigned long addr, pte_t *ptep) 1162 { 1163 pte_t res; 1164 1165 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1166 /* At this point the reference through the mapping is still present */ 1167 if (mm_is_protected(mm) && pte_present(res)) 1168 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1169 return res; 1170 } 1171 1172 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1173 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1174 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1175 pte_t *, pte_t, pte_t); 1176 1177 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1178 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1179 unsigned long addr, pte_t *ptep) 1180 { 1181 pte_t res; 1182 1183 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1184 /* At this point the reference through the mapping is still present */ 1185 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1186 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1187 return res; 1188 } 1189 1190 /* 1191 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1192 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1193 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1194 * cannot be accessed while the batched unmap is running. In this case 1195 * full==1 and a simple pte_clear is enough. See tlb.h. 1196 */ 1197 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1198 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1199 unsigned long addr, 1200 pte_t *ptep, int full) 1201 { 1202 pte_t res; 1203 1204 if (full) { 1205 res = *ptep; 1206 set_pte(ptep, __pte(_PAGE_INVALID)); 1207 } else { 1208 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1209 } 1210 /* Nothing to do */ 1211 if (!mm_is_protected(mm) || !pte_present(res)) 1212 return res; 1213 /* 1214 * At this point the reference through the mapping is still present. 1215 * The notifier should have destroyed all protected vCPUs at this 1216 * point, so the destroy should be successful. 1217 */ 1218 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK)) 1219 return res; 1220 /* 1221 * If something went wrong and the page could not be destroyed, or 1222 * if this is not a mm teardown, the slower export is used as 1223 * fallback instead. 1224 */ 1225 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK); 1226 return res; 1227 } 1228 1229 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1230 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1231 unsigned long addr, pte_t *ptep) 1232 { 1233 pte_t pte = *ptep; 1234 1235 if (pte_write(pte)) 1236 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1237 } 1238 1239 /* 1240 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1241 * bits in the comparison. Those might change e.g. because of dirty and young 1242 * tracking. 1243 */ 1244 static inline int pte_allow_rdp(pte_t old, pte_t new) 1245 { 1246 /* 1247 * Only allow changes from RO to RW 1248 */ 1249 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1250 return 0; 1251 1252 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1253 } 1254 1255 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1256 unsigned long address, 1257 pte_t *ptep) 1258 { 1259 /* 1260 * RDP might not have propagated the PTE protection reset to all CPUs, 1261 * so there could be spurious TLB protection faults. 1262 * NOTE: This will also be called when a racing pagetable update on 1263 * another thread already installed the correct PTE. Both cases cannot 1264 * really be distinguished. 1265 * Therefore, only do the local TLB flush when RDP can be used, and the 1266 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1267 * A local RDP can be used to do the flush. 1268 */ 1269 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1270 __ptep_rdp(address, ptep, 0, 0, 1); 1271 } 1272 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1273 1274 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1275 pte_t new); 1276 1277 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1278 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1279 unsigned long addr, pte_t *ptep, 1280 pte_t entry, int dirty) 1281 { 1282 if (pte_same(*ptep, entry)) 1283 return 0; 1284 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1285 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1286 else 1287 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1288 return 1; 1289 } 1290 1291 /* 1292 * Additional functions to handle KVM guest page tables 1293 */ 1294 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1295 pte_t *ptep, pte_t entry); 1296 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1297 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1298 pte_t *ptep, unsigned long bits); 1299 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1300 pte_t *ptep, int prot, unsigned long bit); 1301 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1302 pte_t *ptep , int reset); 1303 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1304 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1305 pte_t *sptep, pte_t *tptep, pte_t pte); 1306 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1307 1308 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1309 pte_t *ptep); 1310 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1311 unsigned char key, bool nq); 1312 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1313 unsigned char key, unsigned char *oldkey, 1314 bool nq, bool mr, bool mc); 1315 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1316 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1317 unsigned char *key); 1318 1319 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1320 unsigned long bits, unsigned long value); 1321 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1322 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1323 unsigned long *oldpte, unsigned long *oldpgste); 1324 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1325 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1326 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1327 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1328 1329 #define pgprot_writecombine pgprot_writecombine 1330 pgprot_t pgprot_writecombine(pgprot_t prot); 1331 1332 #define pgprot_writethrough pgprot_writethrough 1333 pgprot_t pgprot_writethrough(pgprot_t prot); 1334 1335 #define PFN_PTE_SHIFT PAGE_SHIFT 1336 1337 /* 1338 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1339 * are within the same folio, PMD and VMA. 1340 */ 1341 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1342 pte_t *ptep, pte_t entry, unsigned int nr) 1343 { 1344 if (pte_present(entry)) 1345 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1346 if (mm_has_pgste(mm)) { 1347 for (;;) { 1348 ptep_set_pte_at(mm, addr, ptep, entry); 1349 if (--nr == 0) 1350 break; 1351 ptep++; 1352 entry = __pte(pte_val(entry) + PAGE_SIZE); 1353 addr += PAGE_SIZE; 1354 } 1355 } else { 1356 for (;;) { 1357 set_pte(ptep, entry); 1358 if (--nr == 0) 1359 break; 1360 ptep++; 1361 entry = __pte(pte_val(entry) + PAGE_SIZE); 1362 } 1363 } 1364 } 1365 #define set_ptes set_ptes 1366 1367 /* 1368 * Conversion functions: convert a page and protection to a page entry, 1369 * and a page entry and page directory to the page they refer to. 1370 */ 1371 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1372 { 1373 pte_t __pte; 1374 1375 __pte = __pte(physpage | pgprot_val(pgprot)); 1376 if (!MACHINE_HAS_NX) 1377 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1378 return pte_mkyoung(__pte); 1379 } 1380 1381 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1382 { 1383 unsigned long physpage = page_to_phys(page); 1384 pte_t __pte = mk_pte_phys(physpage, pgprot); 1385 1386 if (pte_write(__pte) && PageDirty(page)) 1387 __pte = pte_mkdirty(__pte); 1388 return __pte; 1389 } 1390 1391 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1392 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1393 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1394 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1395 1396 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1397 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1398 1399 static inline unsigned long pmd_deref(pmd_t pmd) 1400 { 1401 unsigned long origin_mask; 1402 1403 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1404 if (pmd_leaf(pmd)) 1405 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1406 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1407 } 1408 1409 static inline unsigned long pmd_pfn(pmd_t pmd) 1410 { 1411 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1412 } 1413 1414 static inline unsigned long pud_deref(pud_t pud) 1415 { 1416 unsigned long origin_mask; 1417 1418 origin_mask = _REGION_ENTRY_ORIGIN; 1419 if (pud_leaf(pud)) 1420 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1421 return (unsigned long)__va(pud_val(pud) & origin_mask); 1422 } 1423 1424 static inline unsigned long pud_pfn(pud_t pud) 1425 { 1426 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1427 } 1428 1429 /* 1430 * The pgd_offset function *always* adds the index for the top-level 1431 * region/segment table. This is done to get a sequence like the 1432 * following to work: 1433 * pgdp = pgd_offset(current->mm, addr); 1434 * pgd = READ_ONCE(*pgdp); 1435 * p4dp = p4d_offset(&pgd, addr); 1436 * ... 1437 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1438 * only add an index if they dereferenced the pointer. 1439 */ 1440 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1441 { 1442 unsigned long rste; 1443 unsigned int shift; 1444 1445 /* Get the first entry of the top level table */ 1446 rste = pgd_val(*pgd); 1447 /* Pick up the shift from the table type of the first entry */ 1448 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1449 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1450 } 1451 1452 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1453 1454 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1455 { 1456 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1457 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1458 return (p4d_t *) pgdp; 1459 } 1460 #define p4d_offset_lockless p4d_offset_lockless 1461 1462 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1463 { 1464 return p4d_offset_lockless(pgdp, *pgdp, address); 1465 } 1466 1467 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1468 { 1469 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1470 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1471 return (pud_t *) p4dp; 1472 } 1473 #define pud_offset_lockless pud_offset_lockless 1474 1475 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1476 { 1477 return pud_offset_lockless(p4dp, *p4dp, address); 1478 } 1479 #define pud_offset pud_offset 1480 1481 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1482 { 1483 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1484 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1485 return (pmd_t *) pudp; 1486 } 1487 #define pmd_offset_lockless pmd_offset_lockless 1488 1489 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1490 { 1491 return pmd_offset_lockless(pudp, *pudp, address); 1492 } 1493 #define pmd_offset pmd_offset 1494 1495 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1496 { 1497 return (unsigned long) pmd_deref(pmd); 1498 } 1499 1500 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1501 { 1502 return end <= current->mm->context.asce_limit; 1503 } 1504 #define gup_fast_permitted gup_fast_permitted 1505 1506 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1507 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1508 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1509 1510 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1511 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1512 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1513 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1514 1515 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1516 { 1517 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1518 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1519 } 1520 1521 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1522 { 1523 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1524 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1525 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1526 return pmd; 1527 } 1528 1529 static inline pmd_t pmd_mkclean(pmd_t pmd) 1530 { 1531 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1532 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1533 } 1534 1535 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1536 { 1537 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1538 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1539 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1540 return pmd; 1541 } 1542 1543 static inline pud_t pud_wrprotect(pud_t pud) 1544 { 1545 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1546 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1547 } 1548 1549 static inline pud_t pud_mkwrite(pud_t pud) 1550 { 1551 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1552 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1553 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1554 return pud; 1555 } 1556 1557 static inline pud_t pud_mkclean(pud_t pud) 1558 { 1559 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1560 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1561 } 1562 1563 static inline pud_t pud_mkdirty(pud_t pud) 1564 { 1565 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1566 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1567 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1568 return pud; 1569 } 1570 1571 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1572 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1573 { 1574 /* 1575 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1576 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1577 */ 1578 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1579 return pgprot_val(SEGMENT_NONE); 1580 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1581 return pgprot_val(SEGMENT_RO); 1582 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1583 return pgprot_val(SEGMENT_RX); 1584 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1585 return pgprot_val(SEGMENT_RW); 1586 return pgprot_val(SEGMENT_RWX); 1587 } 1588 1589 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1590 { 1591 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1592 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1593 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1594 return pmd; 1595 } 1596 1597 static inline pmd_t pmd_mkold(pmd_t pmd) 1598 { 1599 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1600 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1601 } 1602 1603 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1604 { 1605 unsigned long mask; 1606 1607 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1608 mask |= _SEGMENT_ENTRY_DIRTY; 1609 mask |= _SEGMENT_ENTRY_YOUNG; 1610 mask |= _SEGMENT_ENTRY_LARGE; 1611 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1612 pmd = __pmd(pmd_val(pmd) & mask); 1613 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1614 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1615 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1616 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1617 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1618 return pmd; 1619 } 1620 1621 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1622 { 1623 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1624 } 1625 1626 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1627 1628 static inline void __pmdp_csp(pmd_t *pmdp) 1629 { 1630 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1631 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1632 } 1633 1634 #define IDTE_GLOBAL 0 1635 #define IDTE_LOCAL 1 1636 1637 #define IDTE_PTOA 0x0800 1638 #define IDTE_NODAT 0x1000 1639 #define IDTE_GUEST_ASCE 0x2000 1640 1641 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1642 unsigned long opt, unsigned long asce, 1643 int local) 1644 { 1645 unsigned long sto; 1646 1647 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1648 if (__builtin_constant_p(opt) && opt == 0) { 1649 /* flush without guest asce */ 1650 asm volatile( 1651 " idte %[r1],0,%[r2],%[m4]" 1652 : "+m" (*pmdp) 1653 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1654 [m4] "i" (local) 1655 : "cc" ); 1656 } else { 1657 /* flush with guest asce */ 1658 asm volatile( 1659 " idte %[r1],%[r3],%[r2],%[m4]" 1660 : "+m" (*pmdp) 1661 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1662 [r3] "a" (asce), [m4] "i" (local) 1663 : "cc" ); 1664 } 1665 } 1666 1667 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1668 unsigned long opt, unsigned long asce, 1669 int local) 1670 { 1671 unsigned long r3o; 1672 1673 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1674 r3o |= _ASCE_TYPE_REGION3; 1675 if (__builtin_constant_p(opt) && opt == 0) { 1676 /* flush without guest asce */ 1677 asm volatile( 1678 " idte %[r1],0,%[r2],%[m4]" 1679 : "+m" (*pudp) 1680 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1681 [m4] "i" (local) 1682 : "cc"); 1683 } else { 1684 /* flush with guest asce */ 1685 asm volatile( 1686 " idte %[r1],%[r3],%[r2],%[m4]" 1687 : "+m" (*pudp) 1688 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1689 [r3] "a" (asce), [m4] "i" (local) 1690 : "cc" ); 1691 } 1692 } 1693 1694 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1695 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1696 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1697 1698 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1699 1700 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1701 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1702 pgtable_t pgtable); 1703 1704 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1705 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1706 1707 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1708 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1709 unsigned long addr, pmd_t *pmdp, 1710 pmd_t entry, int dirty) 1711 { 1712 VM_BUG_ON(addr & ~HPAGE_MASK); 1713 1714 entry = pmd_mkyoung(entry); 1715 if (dirty) 1716 entry = pmd_mkdirty(entry); 1717 if (pmd_val(*pmdp) == pmd_val(entry)) 1718 return 0; 1719 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1720 return 1; 1721 } 1722 1723 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1724 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1725 unsigned long addr, pmd_t *pmdp) 1726 { 1727 pmd_t pmd = *pmdp; 1728 1729 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1730 return pmd_young(pmd); 1731 } 1732 1733 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1734 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1735 unsigned long addr, pmd_t *pmdp) 1736 { 1737 VM_BUG_ON(addr & ~HPAGE_MASK); 1738 return pmdp_test_and_clear_young(vma, addr, pmdp); 1739 } 1740 1741 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1742 pmd_t *pmdp, pmd_t entry) 1743 { 1744 if (!MACHINE_HAS_NX) 1745 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1746 set_pmd(pmdp, entry); 1747 } 1748 1749 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1750 { 1751 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1752 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1753 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1754 } 1755 1756 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1757 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1758 unsigned long addr, pmd_t *pmdp) 1759 { 1760 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1761 } 1762 1763 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1764 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1765 unsigned long addr, 1766 pmd_t *pmdp, int full) 1767 { 1768 if (full) { 1769 pmd_t pmd = *pmdp; 1770 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1771 return pmd; 1772 } 1773 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1774 } 1775 1776 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1777 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1778 unsigned long addr, pmd_t *pmdp) 1779 { 1780 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1781 } 1782 1783 #define __HAVE_ARCH_PMDP_INVALIDATE 1784 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1785 unsigned long addr, pmd_t *pmdp) 1786 { 1787 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1788 1789 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1790 } 1791 1792 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1793 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1794 unsigned long addr, pmd_t *pmdp) 1795 { 1796 pmd_t pmd = *pmdp; 1797 1798 if (pmd_write(pmd)) 1799 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1800 } 1801 1802 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1803 unsigned long address, 1804 pmd_t *pmdp) 1805 { 1806 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1807 } 1808 #define pmdp_collapse_flush pmdp_collapse_flush 1809 1810 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1811 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1812 1813 static inline int pmd_trans_huge(pmd_t pmd) 1814 { 1815 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1816 } 1817 1818 #define has_transparent_hugepage has_transparent_hugepage 1819 static inline int has_transparent_hugepage(void) 1820 { 1821 return MACHINE_HAS_EDAT1 ? 1 : 0; 1822 } 1823 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1824 1825 /* 1826 * 64 bit swap entry format: 1827 * A page-table entry has some bits we have to treat in a special way. 1828 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1829 * as invalid. 1830 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1831 * | offset |E11XX|type |S0| 1832 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1833 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1834 * 1835 * Bits 0-51 store the offset. 1836 * Bit 52 (E) is used to remember PG_anon_exclusive. 1837 * Bits 57-61 store the type. 1838 * Bit 62 (S) is used for softdirty tracking. 1839 * Bits 55 and 56 (X) are unused. 1840 */ 1841 1842 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1843 #define __SWP_OFFSET_SHIFT 12 1844 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1845 #define __SWP_TYPE_SHIFT 2 1846 1847 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1848 { 1849 unsigned long pteval; 1850 1851 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1852 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1853 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1854 return __pte(pteval); 1855 } 1856 1857 static inline unsigned long __swp_type(swp_entry_t entry) 1858 { 1859 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1860 } 1861 1862 static inline unsigned long __swp_offset(swp_entry_t entry) 1863 { 1864 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1865 } 1866 1867 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1868 { 1869 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1870 } 1871 1872 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1873 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1874 1875 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1876 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1877 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1878 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1879 extern void vmem_unmap_4k_page(unsigned long addr); 1880 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1881 extern int s390_enable_sie(void); 1882 extern int s390_enable_skey(void); 1883 extern void s390_reset_cmma(struct mm_struct *mm); 1884 1885 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1886 #define HAVE_ARCH_UNMAPPED_AREA 1887 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1888 1889 #define pmd_pgtable(pmd) \ 1890 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1891 1892 #endif /* _S390_PAGE_H */ 1893