1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/ctlreg.h> 21 #include <asm/bug.h> 22 #include <asm/page.h> 23 #include <asm/uv.h> 24 25 extern pgd_t swapper_pg_dir[]; 26 extern pgd_t invalid_pg_dir[]; 27 extern void paging_init(void); 28 extern struct ctlreg s390_invalid_asce; 29 30 enum { 31 PG_DIRECT_MAP_4K = 0, 32 PG_DIRECT_MAP_1M, 33 PG_DIRECT_MAP_2G, 34 PG_DIRECT_MAP_MAX 35 }; 36 37 extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; 38 39 static inline void update_page_count(int level, long count) 40 { 41 if (IS_ENABLED(CONFIG_PROC_FS)) 42 atomic_long_add(count, &direct_pages_count[level]); 43 } 44 45 /* 46 * The S390 doesn't have any external MMU info: the kernel page 47 * tables contain all the necessary information. 48 */ 49 #define update_mmu_cache(vma, address, ptep) do { } while (0) 50 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 51 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 52 53 /* 54 * ZERO_PAGE is a global shared page that is always zero; used 55 * for zero-mapped memory areas etc.. 56 */ 57 58 extern unsigned long empty_zero_page; 59 extern unsigned long zero_page_mask; 60 61 #define ZERO_PAGE(vaddr) \ 62 (virt_to_page((void *)(empty_zero_page + \ 63 (((unsigned long)(vaddr)) &zero_page_mask)))) 64 #define __HAVE_COLOR_ZERO_PAGE 65 66 /* TODO: s390 cannot support io_remap_pfn_range... */ 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 70 #define pmd_ERROR(e) \ 71 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 72 #define pud_ERROR(e) \ 73 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 74 #define p4d_ERROR(e) \ 75 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 76 #define pgd_ERROR(e) \ 77 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 78 79 /* 80 * The vmalloc and module area will always be on the topmost area of the 81 * kernel mapping. 512GB are reserved for vmalloc by default. 82 * At the top of the vmalloc area a 2GB area is reserved where modules 83 * will reside. That makes sure that inter module branches always 84 * happen without trampolines and in addition the placement within a 85 * 2GB frame is branch prediction unit friendly. 86 */ 87 extern unsigned long VMALLOC_START; 88 extern unsigned long VMALLOC_END; 89 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 90 extern struct page *vmemmap; 91 extern unsigned long vmemmap_size; 92 93 extern unsigned long MODULES_VADDR; 94 extern unsigned long MODULES_END; 95 #define MODULES_VADDR MODULES_VADDR 96 #define MODULES_END MODULES_END 97 #define MODULES_LEN (1UL << 31) 98 99 static inline int is_module_addr(void *addr) 100 { 101 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 102 if (addr < (void *)MODULES_VADDR) 103 return 0; 104 if (addr > (void *)MODULES_END) 105 return 0; 106 return 1; 107 } 108 109 #ifdef CONFIG_KMSAN 110 #define KMSAN_VMALLOC_SIZE (VMALLOC_END - VMALLOC_START) 111 #define KMSAN_VMALLOC_SHADOW_START VMALLOC_END 112 #define KMSAN_VMALLOC_SHADOW_END (KMSAN_VMALLOC_SHADOW_START + KMSAN_VMALLOC_SIZE) 113 #define KMSAN_VMALLOC_ORIGIN_START KMSAN_VMALLOC_SHADOW_END 114 #define KMSAN_VMALLOC_ORIGIN_END (KMSAN_VMALLOC_ORIGIN_START + KMSAN_VMALLOC_SIZE) 115 #define KMSAN_MODULES_SHADOW_START KMSAN_VMALLOC_ORIGIN_END 116 #define KMSAN_MODULES_SHADOW_END (KMSAN_MODULES_SHADOW_START + MODULES_LEN) 117 #define KMSAN_MODULES_ORIGIN_START KMSAN_MODULES_SHADOW_END 118 #define KMSAN_MODULES_ORIGIN_END (KMSAN_MODULES_ORIGIN_START + MODULES_LEN) 119 #endif 120 121 #ifdef CONFIG_RANDOMIZE_BASE 122 #define KASLR_LEN (1UL << 31) 123 #else 124 #define KASLR_LEN 0UL 125 #endif 126 127 void setup_protection_map(void); 128 129 /* 130 * A 64 bit pagetable entry of S390 has following format: 131 * | PFRA |0IPC| OS | 132 * 0000000000111111111122222222223333333333444444444455555555556666 133 * 0123456789012345678901234567890123456789012345678901234567890123 134 * 135 * I Page-Invalid Bit: Page is not available for address-translation 136 * P Page-Protection Bit: Store access not possible for page 137 * C Change-bit override: HW is not required to set change bit 138 * 139 * A 64 bit segmenttable entry of S390 has following format: 140 * | P-table origin | TT 141 * 0000000000111111111122222222223333333333444444444455555555556666 142 * 0123456789012345678901234567890123456789012345678901234567890123 143 * 144 * I Segment-Invalid Bit: Segment is not available for address-translation 145 * C Common-Segment Bit: Segment is not private (PoP 3-30) 146 * P Page-Protection Bit: Store access not possible for page 147 * TT Type 00 148 * 149 * A 64 bit region table entry of S390 has following format: 150 * | S-table origin | TF TTTL 151 * 0000000000111111111122222222223333333333444444444455555555556666 152 * 0123456789012345678901234567890123456789012345678901234567890123 153 * 154 * I Segment-Invalid Bit: Segment is not available for address-translation 155 * TT Type 01 156 * TF 157 * TL Table length 158 * 159 * The 64 bit regiontable origin of S390 has following format: 160 * | region table origon | DTTL 161 * 0000000000111111111122222222223333333333444444444455555555556666 162 * 0123456789012345678901234567890123456789012345678901234567890123 163 * 164 * X Space-Switch event: 165 * G Segment-Invalid Bit: 166 * P Private-Space Bit: 167 * S Storage-Alteration: 168 * R Real space 169 * TL Table-Length: 170 * 171 * A storage key has the following format: 172 * | ACC |F|R|C|0| 173 * 0 3 4 5 6 7 174 * ACC: access key 175 * F : fetch protection bit 176 * R : referenced bit 177 * C : changed bit 178 */ 179 180 /* Hardware bits in the page table entry */ 181 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 182 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 183 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 184 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 185 186 /* Software bits in the page table entry */ 187 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 188 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 189 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 190 #define _PAGE_READ 0x010 /* SW pte read bit */ 191 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 192 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 193 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 194 195 #ifdef CONFIG_MEM_SOFT_DIRTY 196 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 197 #else 198 #define _PAGE_SOFT_DIRTY 0x000 199 #endif 200 201 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 202 203 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 204 205 /* Set of bits not changed in pte_modify */ 206 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 207 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 208 209 /* 210 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 211 * HW bit and all SW bits. 212 */ 213 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 214 215 /* 216 * handle_pte_fault uses pte_present and pte_none to find out the pte type 217 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 218 * distinguish present from not-present ptes. It is changed only with the page 219 * table lock held. 220 * 221 * The following table gives the different possible bit combinations for 222 * the pte hardware and software bits in the last 12 bits of a pte 223 * (. unassigned bit, x don't care, t swap type): 224 * 225 * 842100000000 226 * 000084210000 227 * 000000008421 228 * .IR.uswrdy.p 229 * empty .10.00000000 230 * swap .11..ttttt.0 231 * prot-none, clean, old .11.xx0000.1 232 * prot-none, clean, young .11.xx0001.1 233 * prot-none, dirty, old .11.xx0010.1 234 * prot-none, dirty, young .11.xx0011.1 235 * read-only, clean, old .11.xx0100.1 236 * read-only, clean, young .01.xx0101.1 237 * read-only, dirty, old .11.xx0110.1 238 * read-only, dirty, young .01.xx0111.1 239 * read-write, clean, old .11.xx1100.1 240 * read-write, clean, young .01.xx1101.1 241 * read-write, dirty, old .10.xx1110.1 242 * read-write, dirty, young .00.xx1111.1 243 * HW-bits: R read-only, I invalid 244 * SW-bits: p present, y young, d dirty, r read, w write, s special, 245 * u unused, l large 246 * 247 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 248 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 249 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 250 */ 251 252 /* Bits in the segment/region table address-space-control-element */ 253 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 254 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 255 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 256 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 257 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 258 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 259 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 260 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 261 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 262 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 263 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 264 265 /* Bits in the region table entry */ 266 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 267 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 268 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 269 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 270 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 271 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 272 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 273 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 274 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 275 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 276 277 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 278 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 279 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 280 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 281 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH | \ 282 _REGION3_ENTRY_PRESENT) 283 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 284 285 #define _REGION3_ENTRY_HARDWARE_BITS 0xfffffffffffff6ffUL 286 #define _REGION3_ENTRY_HARDWARE_BITS_LARGE 0xffffffff8001073cUL 287 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 288 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 289 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 290 #define _REGION3_ENTRY_COMM 0x0010 /* Common-Region, marks swap entry */ 291 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 292 #define _REGION3_ENTRY_WRITE 0x8000 /* SW region write bit */ 293 #define _REGION3_ENTRY_READ 0x4000 /* SW region read bit */ 294 295 #ifdef CONFIG_MEM_SOFT_DIRTY 296 #define _REGION3_ENTRY_SOFT_DIRTY 0x0002 /* SW region soft dirty bit */ 297 #else 298 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 299 #endif 300 301 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 302 303 /* 304 * SW region present bit. For non-leaf region-third-table entries, bits 62-63 305 * indicate the TABLE LENGTH and both must be set to 1. But such entries 306 * would always be considered as present, so it is safe to use bit 63 as 307 * PRESENT bit for PUD. 308 */ 309 #define _REGION3_ENTRY_PRESENT 0x0001 310 311 /* Bits in the segment table entry */ 312 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe3fUL 313 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe3cUL 314 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff1073cUL 315 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 316 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 317 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 318 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 319 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 320 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 321 322 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PRESENT) 323 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 324 325 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 326 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 327 328 #define _SEGMENT_ENTRY_COMM 0x0010 /* Common-Segment, marks swap entry */ 329 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 330 #define _SEGMENT_ENTRY_WRITE 0x8000 /* SW segment write bit */ 331 #define _SEGMENT_ENTRY_READ 0x4000 /* SW segment read bit */ 332 333 #ifdef CONFIG_MEM_SOFT_DIRTY 334 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0002 /* SW segment soft dirty bit */ 335 #else 336 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 337 #endif 338 339 #define _SEGMENT_ENTRY_PRESENT 0x0001 /* SW segment present bit */ 340 341 /* Common bits in region and segment table entries, for swap entries */ 342 #define _RST_ENTRY_COMM 0x0010 /* Common-Region/Segment, marks swap entry */ 343 #define _RST_ENTRY_INVALID 0x0020 /* invalid region/segment table entry */ 344 345 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 346 #define _PAGE_ENTRIES 256 /* number of page table entries */ 347 348 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 349 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 350 351 #define _REGION1_SHIFT 53 352 #define _REGION2_SHIFT 42 353 #define _REGION3_SHIFT 31 354 #define _SEGMENT_SHIFT 20 355 356 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 357 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 358 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 359 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 360 #define _PAGE_INDEX (0xffUL << PAGE_SHIFT) 361 362 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 363 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 364 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 365 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 366 367 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 368 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 369 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 370 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 371 372 #define PMD_SHIFT _SEGMENT_SHIFT 373 #define PUD_SHIFT _REGION3_SHIFT 374 #define P4D_SHIFT _REGION2_SHIFT 375 #define PGDIR_SHIFT _REGION1_SHIFT 376 377 #define PMD_SIZE _SEGMENT_SIZE 378 #define PUD_SIZE _REGION3_SIZE 379 #define P4D_SIZE _REGION2_SIZE 380 #define PGDIR_SIZE _REGION1_SIZE 381 382 #define PMD_MASK _SEGMENT_MASK 383 #define PUD_MASK _REGION3_MASK 384 #define P4D_MASK _REGION2_MASK 385 #define PGDIR_MASK _REGION1_MASK 386 387 #define PTRS_PER_PTE _PAGE_ENTRIES 388 #define PTRS_PER_PMD _CRST_ENTRIES 389 #define PTRS_PER_PUD _CRST_ENTRIES 390 #define PTRS_PER_P4D _CRST_ENTRIES 391 #define PTRS_PER_PGD _CRST_ENTRIES 392 393 /* 394 * Segment table and region3 table entry encoding 395 * (R = read-only, I = invalid, y = young bit): 396 * dy..R...I...wr 397 * prot-none, clean, old 00..1...1...00 398 * prot-none, clean, young 01..1...1...00 399 * prot-none, dirty, old 10..1...1...00 400 * prot-none, dirty, young 11..1...1...00 401 * read-only, clean, old 00..1...1...01 402 * read-only, clean, young 01..1...0...01 403 * read-only, dirty, old 10..1...1...01 404 * read-only, dirty, young 11..1...0...01 405 * read-write, clean, old 00..1...1...11 406 * read-write, clean, young 01..1...0...11 407 * read-write, dirty, old 10..0...1...11 408 * read-write, dirty, young 11..0...0...11 409 * The segment table origin is used to distinguish empty (origin==0) from 410 * read-write, old segment table entries (origin!=0) 411 * HW-bits: R read-only, I invalid 412 * SW-bits: y young, d dirty, r read, w write 413 */ 414 415 /* Page status table bits for virtualization */ 416 #define PGSTE_ACC_BITS 0xf000000000000000UL 417 #define PGSTE_FP_BIT 0x0800000000000000UL 418 #define PGSTE_PCL_BIT 0x0080000000000000UL 419 #define PGSTE_HR_BIT 0x0040000000000000UL 420 #define PGSTE_HC_BIT 0x0020000000000000UL 421 #define PGSTE_GR_BIT 0x0004000000000000UL 422 #define PGSTE_GC_BIT 0x0002000000000000UL 423 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 424 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 425 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 426 427 /* Guest Page State used for virtualization */ 428 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 429 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 430 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 431 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 432 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 433 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 434 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 435 436 /* 437 * A user page table pointer has the space-switch-event bit, the 438 * private-space-control bit and the storage-alteration-event-control 439 * bit set. A kernel page table pointer doesn't need them. 440 */ 441 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 442 _ASCE_ALT_EVENT) 443 444 /* 445 * Page protection definitions. 446 */ 447 #define __PAGE_NONE (_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 448 #define __PAGE_RO (_PAGE_PRESENT | _PAGE_READ | \ 449 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 450 #define __PAGE_RX (_PAGE_PRESENT | _PAGE_READ | \ 451 _PAGE_INVALID | _PAGE_PROTECT) 452 #define __PAGE_RW (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 453 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 454 #define __PAGE_RWX (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 455 _PAGE_INVALID | _PAGE_PROTECT) 456 #define __PAGE_SHARED (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 457 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 458 #define __PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 459 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 460 #define __PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 461 _PAGE_PROTECT | _PAGE_NOEXEC) 462 463 extern unsigned long page_noexec_mask; 464 465 #define __pgprot_page_mask(x) __pgprot((x) & page_noexec_mask) 466 467 #define PAGE_NONE __pgprot_page_mask(__PAGE_NONE) 468 #define PAGE_RO __pgprot_page_mask(__PAGE_RO) 469 #define PAGE_RX __pgprot_page_mask(__PAGE_RX) 470 #define PAGE_RW __pgprot_page_mask(__PAGE_RW) 471 #define PAGE_RWX __pgprot_page_mask(__PAGE_RWX) 472 #define PAGE_SHARED __pgprot_page_mask(__PAGE_SHARED) 473 #define PAGE_KERNEL __pgprot_page_mask(__PAGE_KERNEL) 474 #define PAGE_KERNEL_RO __pgprot_page_mask(__PAGE_KERNEL_RO) 475 476 /* 477 * Segment entry (large page) protection definitions. 478 */ 479 #define __SEGMENT_NONE (_SEGMENT_ENTRY_PRESENT | \ 480 _SEGMENT_ENTRY_INVALID | \ 481 _SEGMENT_ENTRY_PROTECT) 482 #define __SEGMENT_RO (_SEGMENT_ENTRY_PRESENT | \ 483 _SEGMENT_ENTRY_PROTECT | \ 484 _SEGMENT_ENTRY_READ | \ 485 _SEGMENT_ENTRY_NOEXEC) 486 #define __SEGMENT_RX (_SEGMENT_ENTRY_PRESENT | \ 487 _SEGMENT_ENTRY_PROTECT | \ 488 _SEGMENT_ENTRY_READ) 489 #define __SEGMENT_RW (_SEGMENT_ENTRY_PRESENT | \ 490 _SEGMENT_ENTRY_READ | \ 491 _SEGMENT_ENTRY_WRITE | \ 492 _SEGMENT_ENTRY_NOEXEC) 493 #define __SEGMENT_RWX (_SEGMENT_ENTRY_PRESENT | \ 494 _SEGMENT_ENTRY_READ | \ 495 _SEGMENT_ENTRY_WRITE) 496 #define __SEGMENT_KERNEL (_SEGMENT_ENTRY | \ 497 _SEGMENT_ENTRY_LARGE | \ 498 _SEGMENT_ENTRY_READ | \ 499 _SEGMENT_ENTRY_WRITE | \ 500 _SEGMENT_ENTRY_YOUNG | \ 501 _SEGMENT_ENTRY_DIRTY | \ 502 _SEGMENT_ENTRY_NOEXEC) 503 #define __SEGMENT_KERNEL_RO (_SEGMENT_ENTRY | \ 504 _SEGMENT_ENTRY_LARGE | \ 505 _SEGMENT_ENTRY_READ | \ 506 _SEGMENT_ENTRY_YOUNG | \ 507 _SEGMENT_ENTRY_PROTECT | \ 508 _SEGMENT_ENTRY_NOEXEC) 509 510 extern unsigned long segment_noexec_mask; 511 512 #define __pgprot_segment_mask(x) __pgprot((x) & segment_noexec_mask) 513 514 #define SEGMENT_NONE __pgprot_segment_mask(__SEGMENT_NONE) 515 #define SEGMENT_RO __pgprot_segment_mask(__SEGMENT_RO) 516 #define SEGMENT_RX __pgprot_segment_mask(__SEGMENT_RX) 517 #define SEGMENT_RW __pgprot_segment_mask(__SEGMENT_RW) 518 #define SEGMENT_RWX __pgprot_segment_mask(__SEGMENT_RWX) 519 #define SEGMENT_KERNEL __pgprot_segment_mask(__SEGMENT_KERNEL) 520 #define SEGMENT_KERNEL_RO __pgprot_segment_mask(__SEGMENT_KERNEL_RO) 521 522 /* 523 * Region3 entry (large page) protection definitions. 524 */ 525 526 #define __REGION3_KERNEL (_REGION_ENTRY_TYPE_R3 | \ 527 _REGION3_ENTRY_PRESENT | \ 528 _REGION3_ENTRY_LARGE | \ 529 _REGION3_ENTRY_READ | \ 530 _REGION3_ENTRY_WRITE | \ 531 _REGION3_ENTRY_YOUNG | \ 532 _REGION3_ENTRY_DIRTY | \ 533 _REGION_ENTRY_NOEXEC) 534 #define __REGION3_KERNEL_RO (_REGION_ENTRY_TYPE_R3 | \ 535 _REGION3_ENTRY_PRESENT | \ 536 _REGION3_ENTRY_LARGE | \ 537 _REGION3_ENTRY_READ | \ 538 _REGION3_ENTRY_YOUNG | \ 539 _REGION_ENTRY_PROTECT | \ 540 _REGION_ENTRY_NOEXEC) 541 542 extern unsigned long region_noexec_mask; 543 544 #define __pgprot_region_mask(x) __pgprot((x) & region_noexec_mask) 545 546 #define REGION3_KERNEL __pgprot_region_mask(__REGION3_KERNEL) 547 #define REGION3_KERNEL_RO __pgprot_region_mask(__REGION3_KERNEL_RO) 548 549 static inline bool mm_p4d_folded(struct mm_struct *mm) 550 { 551 return mm->context.asce_limit <= _REGION1_SIZE; 552 } 553 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 554 555 static inline bool mm_pud_folded(struct mm_struct *mm) 556 { 557 return mm->context.asce_limit <= _REGION2_SIZE; 558 } 559 #define mm_pud_folded(mm) mm_pud_folded(mm) 560 561 static inline bool mm_pmd_folded(struct mm_struct *mm) 562 { 563 return mm->context.asce_limit <= _REGION3_SIZE; 564 } 565 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 566 567 static inline int mm_has_pgste(struct mm_struct *mm) 568 { 569 #ifdef CONFIG_PGSTE 570 if (unlikely(mm->context.has_pgste)) 571 return 1; 572 #endif 573 return 0; 574 } 575 576 static inline int mm_is_protected(struct mm_struct *mm) 577 { 578 #ifdef CONFIG_PGSTE 579 if (unlikely(atomic_read(&mm->context.protected_count))) 580 return 1; 581 #endif 582 return 0; 583 } 584 585 static inline int mm_alloc_pgste(struct mm_struct *mm) 586 { 587 #ifdef CONFIG_PGSTE 588 if (unlikely(mm->context.alloc_pgste)) 589 return 1; 590 #endif 591 return 0; 592 } 593 594 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 595 { 596 return __pte(pte_val(pte) & ~pgprot_val(prot)); 597 } 598 599 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 600 { 601 return __pte(pte_val(pte) | pgprot_val(prot)); 602 } 603 604 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 605 { 606 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 607 } 608 609 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 610 { 611 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 612 } 613 614 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 615 { 616 return __pud(pud_val(pud) & ~pgprot_val(prot)); 617 } 618 619 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 620 { 621 return __pud(pud_val(pud) | pgprot_val(prot)); 622 } 623 624 /* 625 * As soon as the guest uses storage keys or enables PV, we deduplicate all 626 * mapped shared zeropages and prevent new shared zeropages from getting 627 * mapped. 628 */ 629 #define mm_forbids_zeropage mm_forbids_zeropage 630 static inline int mm_forbids_zeropage(struct mm_struct *mm) 631 { 632 #ifdef CONFIG_PGSTE 633 if (!mm->context.allow_cow_sharing) 634 return 1; 635 #endif 636 return 0; 637 } 638 639 static inline int mm_uses_skeys(struct mm_struct *mm) 640 { 641 #ifdef CONFIG_PGSTE 642 if (mm->context.uses_skeys) 643 return 1; 644 #endif 645 return 0; 646 } 647 648 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 649 { 650 union register_pair r1 = { .even = old, .odd = new, }; 651 unsigned long address = (unsigned long)ptr | 1; 652 653 asm volatile( 654 " csp %[r1],%[address]" 655 : [r1] "+&d" (r1.pair), "+m" (*ptr) 656 : [address] "d" (address) 657 : "cc"); 658 } 659 660 /** 661 * cspg() - Compare and Swap and Purge (CSPG) 662 * @ptr: Pointer to the value to be exchanged 663 * @old: The expected old value 664 * @new: The new value 665 * 666 * Return: True if compare and swap was successful, otherwise false. 667 */ 668 static inline bool cspg(unsigned long *ptr, unsigned long old, unsigned long new) 669 { 670 union register_pair r1 = { .even = old, .odd = new, }; 671 unsigned long address = (unsigned long)ptr | 1; 672 673 asm volatile( 674 " cspg %[r1],%[address]" 675 : [r1] "+&d" (r1.pair), "+m" (*ptr) 676 : [address] "d" (address) 677 : "cc"); 678 return old == r1.even; 679 } 680 681 #define CRDTE_DTT_PAGE 0x00UL 682 #define CRDTE_DTT_SEGMENT 0x10UL 683 #define CRDTE_DTT_REGION3 0x14UL 684 #define CRDTE_DTT_REGION2 0x18UL 685 #define CRDTE_DTT_REGION1 0x1cUL 686 687 /** 688 * crdte() - Compare and Replace DAT Table Entry 689 * @old: The expected old value 690 * @new: The new value 691 * @table: Pointer to the value to be exchanged 692 * @dtt: Table type of the table to be exchanged 693 * @address: The address mapped by the entry to be replaced 694 * @asce: The ASCE of this entry 695 * 696 * Return: True if compare and replace was successful, otherwise false. 697 */ 698 static inline bool crdte(unsigned long old, unsigned long new, 699 unsigned long *table, unsigned long dtt, 700 unsigned long address, unsigned long asce) 701 { 702 union register_pair r1 = { .even = old, .odd = new, }; 703 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 704 705 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 706 : [r1] "+&d" (r1.pair) 707 : [r2] "d" (r2.pair), [asce] "a" (asce) 708 : "memory", "cc"); 709 return old == r1.even; 710 } 711 712 /* 713 * pgd/p4d/pud/pmd/pte query functions 714 */ 715 static inline int pgd_folded(pgd_t pgd) 716 { 717 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 718 } 719 720 static inline int pgd_present(pgd_t pgd) 721 { 722 if (pgd_folded(pgd)) 723 return 1; 724 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 725 } 726 727 static inline int pgd_none(pgd_t pgd) 728 { 729 if (pgd_folded(pgd)) 730 return 0; 731 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 732 } 733 734 static inline int pgd_bad(pgd_t pgd) 735 { 736 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 737 return 0; 738 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 739 } 740 741 static inline unsigned long pgd_pfn(pgd_t pgd) 742 { 743 unsigned long origin_mask; 744 745 origin_mask = _REGION_ENTRY_ORIGIN; 746 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 747 } 748 749 static inline int p4d_folded(p4d_t p4d) 750 { 751 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 752 } 753 754 static inline int p4d_present(p4d_t p4d) 755 { 756 if (p4d_folded(p4d)) 757 return 1; 758 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 759 } 760 761 static inline int p4d_none(p4d_t p4d) 762 { 763 if (p4d_folded(p4d)) 764 return 0; 765 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 766 } 767 768 static inline unsigned long p4d_pfn(p4d_t p4d) 769 { 770 unsigned long origin_mask; 771 772 origin_mask = _REGION_ENTRY_ORIGIN; 773 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 774 } 775 776 static inline int pud_folded(pud_t pud) 777 { 778 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 779 } 780 781 static inline int pud_present(pud_t pud) 782 { 783 if (pud_folded(pud)) 784 return 1; 785 return (pud_val(pud) & _REGION3_ENTRY_PRESENT) != 0; 786 } 787 788 static inline int pud_none(pud_t pud) 789 { 790 if (pud_folded(pud)) 791 return 0; 792 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 793 } 794 795 #define pud_leaf pud_leaf 796 static inline bool pud_leaf(pud_t pud) 797 { 798 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 799 return 0; 800 return (pud_present(pud) && (pud_val(pud) & _REGION3_ENTRY_LARGE) != 0); 801 } 802 803 static inline int pmd_present(pmd_t pmd) 804 { 805 return (pmd_val(pmd) & _SEGMENT_ENTRY_PRESENT) != 0; 806 } 807 808 #define pmd_leaf pmd_leaf 809 static inline bool pmd_leaf(pmd_t pmd) 810 { 811 return (pmd_present(pmd) && (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0); 812 } 813 814 static inline int pmd_bad(pmd_t pmd) 815 { 816 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 817 return 1; 818 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 819 } 820 821 static inline int pud_bad(pud_t pud) 822 { 823 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 824 825 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 826 return 1; 827 if (type < _REGION_ENTRY_TYPE_R3) 828 return 0; 829 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 830 } 831 832 static inline int p4d_bad(p4d_t p4d) 833 { 834 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 835 836 if (type > _REGION_ENTRY_TYPE_R2) 837 return 1; 838 if (type < _REGION_ENTRY_TYPE_R2) 839 return 0; 840 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 841 } 842 843 static inline int pmd_none(pmd_t pmd) 844 { 845 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 846 } 847 848 #define pmd_write pmd_write 849 static inline int pmd_write(pmd_t pmd) 850 { 851 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 852 } 853 854 #define pud_write pud_write 855 static inline int pud_write(pud_t pud) 856 { 857 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 858 } 859 860 #define pmd_dirty pmd_dirty 861 static inline int pmd_dirty(pmd_t pmd) 862 { 863 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 864 } 865 866 #define pmd_young pmd_young 867 static inline int pmd_young(pmd_t pmd) 868 { 869 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 870 } 871 872 static inline int pte_present(pte_t pte) 873 { 874 /* Bit pattern: (pte & 0x001) == 0x001 */ 875 return (pte_val(pte) & _PAGE_PRESENT) != 0; 876 } 877 878 static inline int pte_none(pte_t pte) 879 { 880 /* Bit pattern: pte == 0x400 */ 881 return pte_val(pte) == _PAGE_INVALID; 882 } 883 884 static inline int pte_swap(pte_t pte) 885 { 886 /* Bit pattern: (pte & 0x201) == 0x200 */ 887 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 888 == _PAGE_PROTECT; 889 } 890 891 static inline int pte_special(pte_t pte) 892 { 893 return (pte_val(pte) & _PAGE_SPECIAL); 894 } 895 896 #define __HAVE_ARCH_PTE_SAME 897 static inline int pte_same(pte_t a, pte_t b) 898 { 899 return pte_val(a) == pte_val(b); 900 } 901 902 #ifdef CONFIG_NUMA_BALANCING 903 static inline int pte_protnone(pte_t pte) 904 { 905 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 906 } 907 908 static inline int pmd_protnone(pmd_t pmd) 909 { 910 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 911 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 912 } 913 #endif 914 915 static inline int pte_swp_exclusive(pte_t pte) 916 { 917 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 918 } 919 920 static inline pte_t pte_swp_mkexclusive(pte_t pte) 921 { 922 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 923 } 924 925 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 926 { 927 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 928 } 929 930 static inline int pte_soft_dirty(pte_t pte) 931 { 932 return pte_val(pte) & _PAGE_SOFT_DIRTY; 933 } 934 #define pte_swp_soft_dirty pte_soft_dirty 935 936 static inline pte_t pte_mksoft_dirty(pte_t pte) 937 { 938 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 939 } 940 #define pte_swp_mksoft_dirty pte_mksoft_dirty 941 942 static inline pte_t pte_clear_soft_dirty(pte_t pte) 943 { 944 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 945 } 946 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 947 948 static inline int pmd_soft_dirty(pmd_t pmd) 949 { 950 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 951 } 952 953 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 954 { 955 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 956 } 957 958 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 959 { 960 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 961 } 962 963 /* 964 * query functions pte_write/pte_dirty/pte_young only work if 965 * pte_present() is true. Undefined behaviour if not.. 966 */ 967 static inline int pte_write(pte_t pte) 968 { 969 return (pte_val(pte) & _PAGE_WRITE) != 0; 970 } 971 972 static inline int pte_dirty(pte_t pte) 973 { 974 return (pte_val(pte) & _PAGE_DIRTY) != 0; 975 } 976 977 static inline int pte_young(pte_t pte) 978 { 979 return (pte_val(pte) & _PAGE_YOUNG) != 0; 980 } 981 982 #define __HAVE_ARCH_PTE_UNUSED 983 static inline int pte_unused(pte_t pte) 984 { 985 return pte_val(pte) & _PAGE_UNUSED; 986 } 987 988 /* 989 * Extract the pgprot value from the given pte while at the same time making it 990 * usable for kernel address space mappings where fault driven dirty and 991 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 992 * must not be set. 993 */ 994 #define pte_pgprot pte_pgprot 995 static inline pgprot_t pte_pgprot(pte_t pte) 996 { 997 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 998 999 if (pte_write(pte)) 1000 pte_flags |= pgprot_val(PAGE_KERNEL); 1001 else 1002 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 1003 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 1004 1005 return __pgprot(pte_flags); 1006 } 1007 1008 /* 1009 * pgd/pmd/pte modification functions 1010 */ 1011 1012 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1013 { 1014 WRITE_ONCE(*pgdp, pgd); 1015 } 1016 1017 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 1018 { 1019 WRITE_ONCE(*p4dp, p4d); 1020 } 1021 1022 static inline void set_pud(pud_t *pudp, pud_t pud) 1023 { 1024 WRITE_ONCE(*pudp, pud); 1025 } 1026 1027 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 1028 { 1029 WRITE_ONCE(*pmdp, pmd); 1030 } 1031 1032 static inline void set_pte(pte_t *ptep, pte_t pte) 1033 { 1034 WRITE_ONCE(*ptep, pte); 1035 } 1036 1037 static inline void pgd_clear(pgd_t *pgd) 1038 { 1039 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 1040 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 1041 } 1042 1043 static inline void p4d_clear(p4d_t *p4d) 1044 { 1045 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1046 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 1047 } 1048 1049 static inline void pud_clear(pud_t *pud) 1050 { 1051 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1052 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 1053 } 1054 1055 static inline void pmd_clear(pmd_t *pmdp) 1056 { 1057 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1058 } 1059 1060 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 1061 { 1062 set_pte(ptep, __pte(_PAGE_INVALID)); 1063 } 1064 1065 /* 1066 * The following pte modification functions only work if 1067 * pte_present() is true. Undefined behaviour if not.. 1068 */ 1069 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1070 { 1071 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 1072 pte = set_pte_bit(pte, newprot); 1073 /* 1074 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 1075 * has the invalid bit set, clear it again for readable, young pages 1076 */ 1077 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 1078 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1079 /* 1080 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1081 * protection bit set, clear it again for writable, dirty pages 1082 */ 1083 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1084 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1085 return pte; 1086 } 1087 1088 static inline pte_t pte_wrprotect(pte_t pte) 1089 { 1090 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1091 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1092 } 1093 1094 static inline pte_t pte_mkwrite_novma(pte_t pte) 1095 { 1096 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1097 if (pte_val(pte) & _PAGE_DIRTY) 1098 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1099 return pte; 1100 } 1101 1102 static inline pte_t pte_mkclean(pte_t pte) 1103 { 1104 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1105 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1106 } 1107 1108 static inline pte_t pte_mkdirty(pte_t pte) 1109 { 1110 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1111 if (pte_val(pte) & _PAGE_WRITE) 1112 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1113 return pte; 1114 } 1115 1116 static inline pte_t pte_mkold(pte_t pte) 1117 { 1118 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1119 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1120 } 1121 1122 static inline pte_t pte_mkyoung(pte_t pte) 1123 { 1124 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1125 if (pte_val(pte) & _PAGE_READ) 1126 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1127 return pte; 1128 } 1129 1130 static inline pte_t pte_mkspecial(pte_t pte) 1131 { 1132 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1133 } 1134 1135 #ifdef CONFIG_HUGETLB_PAGE 1136 static inline pte_t pte_mkhuge(pte_t pte) 1137 { 1138 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1139 } 1140 #endif 1141 1142 #define IPTE_GLOBAL 0 1143 #define IPTE_LOCAL 1 1144 1145 #define IPTE_NODAT 0x400 1146 #define IPTE_GUEST_ASCE 0x800 1147 1148 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1149 unsigned long opt, unsigned long asce, 1150 int local) 1151 { 1152 unsigned long pto; 1153 1154 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1155 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1156 : "+m" (*ptep) 1157 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1158 [asce] "a" (asce), [m4] "i" (local)); 1159 } 1160 1161 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1162 unsigned long opt, unsigned long asce, 1163 int local) 1164 { 1165 unsigned long pto = __pa(ptep); 1166 1167 if (__builtin_constant_p(opt) && opt == 0) { 1168 /* Invalidation + TLB flush for the pte */ 1169 asm volatile( 1170 " ipte %[r1],%[r2],0,%[m4]" 1171 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1172 [m4] "i" (local)); 1173 return; 1174 } 1175 1176 /* Invalidate ptes with options + TLB flush of the ptes */ 1177 opt = opt | (asce & _ASCE_ORIGIN); 1178 asm volatile( 1179 " ipte %[r1],%[r2],%[r3],%[m4]" 1180 : [r2] "+a" (address), [r3] "+a" (opt) 1181 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1182 } 1183 1184 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1185 pte_t *ptep, int local) 1186 { 1187 unsigned long pto = __pa(ptep); 1188 1189 /* Invalidate a range of ptes + TLB flush of the ptes */ 1190 do { 1191 asm volatile( 1192 " ipte %[r1],%[r2],%[r3],%[m4]" 1193 : [r2] "+a" (address), [r3] "+a" (nr) 1194 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1195 } while (nr != 255); 1196 } 1197 1198 /* 1199 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1200 * both clear the TLB for the unmapped pte. The reason is that 1201 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1202 * to modify an active pte. The sequence is 1203 * 1) ptep_get_and_clear 1204 * 2) set_pte_at 1205 * 3) flush_tlb_range 1206 * On s390 the tlb needs to get flushed with the modification of the pte 1207 * if the pte is active. The only way how this can be implemented is to 1208 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1209 * is a nop. 1210 */ 1211 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1212 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1213 1214 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1215 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1216 unsigned long addr, pte_t *ptep) 1217 { 1218 pte_t pte = *ptep; 1219 1220 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1221 return pte_young(pte); 1222 } 1223 1224 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1225 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1226 unsigned long address, pte_t *ptep) 1227 { 1228 return ptep_test_and_clear_young(vma, address, ptep); 1229 } 1230 1231 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1232 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1233 unsigned long addr, pte_t *ptep) 1234 { 1235 pte_t res; 1236 1237 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1238 /* At this point the reference through the mapping is still present */ 1239 if (mm_is_protected(mm) && pte_present(res)) 1240 uv_convert_from_secure_pte(res); 1241 return res; 1242 } 1243 1244 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1245 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1246 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1247 pte_t *, pte_t, pte_t); 1248 1249 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1250 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1251 unsigned long addr, pte_t *ptep) 1252 { 1253 pte_t res; 1254 1255 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1256 /* At this point the reference through the mapping is still present */ 1257 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1258 uv_convert_from_secure_pte(res); 1259 return res; 1260 } 1261 1262 /* 1263 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1264 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1265 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1266 * cannot be accessed while the batched unmap is running. In this case 1267 * full==1 and a simple pte_clear is enough. See tlb.h. 1268 */ 1269 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1270 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1271 unsigned long addr, 1272 pte_t *ptep, int full) 1273 { 1274 pte_t res; 1275 1276 if (full) { 1277 res = *ptep; 1278 set_pte(ptep, __pte(_PAGE_INVALID)); 1279 } else { 1280 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1281 } 1282 /* Nothing to do */ 1283 if (!mm_is_protected(mm) || !pte_present(res)) 1284 return res; 1285 /* 1286 * At this point the reference through the mapping is still present. 1287 * The notifier should have destroyed all protected vCPUs at this 1288 * point, so the destroy should be successful. 1289 */ 1290 if (full && !uv_destroy_pte(res)) 1291 return res; 1292 /* 1293 * If something went wrong and the page could not be destroyed, or 1294 * if this is not a mm teardown, the slower export is used as 1295 * fallback instead. 1296 */ 1297 uv_convert_from_secure_pte(res); 1298 return res; 1299 } 1300 1301 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1302 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1303 unsigned long addr, pte_t *ptep) 1304 { 1305 pte_t pte = *ptep; 1306 1307 if (pte_write(pte)) 1308 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1309 } 1310 1311 /* 1312 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1313 * bits in the comparison. Those might change e.g. because of dirty and young 1314 * tracking. 1315 */ 1316 static inline int pte_allow_rdp(pte_t old, pte_t new) 1317 { 1318 /* 1319 * Only allow changes from RO to RW 1320 */ 1321 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1322 return 0; 1323 1324 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1325 } 1326 1327 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1328 unsigned long address, 1329 pte_t *ptep) 1330 { 1331 /* 1332 * RDP might not have propagated the PTE protection reset to all CPUs, 1333 * so there could be spurious TLB protection faults. 1334 * NOTE: This will also be called when a racing pagetable update on 1335 * another thread already installed the correct PTE. Both cases cannot 1336 * really be distinguished. 1337 * Therefore, only do the local TLB flush when RDP can be used, and the 1338 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1339 * A local RDP can be used to do the flush. 1340 */ 1341 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1342 __ptep_rdp(address, ptep, 0, 0, 1); 1343 } 1344 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1345 1346 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1347 pte_t new); 1348 1349 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1350 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1351 unsigned long addr, pte_t *ptep, 1352 pte_t entry, int dirty) 1353 { 1354 if (pte_same(*ptep, entry)) 1355 return 0; 1356 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1357 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1358 else 1359 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1360 return 1; 1361 } 1362 1363 /* 1364 * Additional functions to handle KVM guest page tables 1365 */ 1366 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1367 pte_t *ptep, pte_t entry); 1368 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1369 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1370 pte_t *ptep, unsigned long bits); 1371 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1372 pte_t *ptep, int prot, unsigned long bit); 1373 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1374 pte_t *ptep , int reset); 1375 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1376 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1377 pte_t *sptep, pte_t *tptep, pte_t pte); 1378 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1379 1380 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1381 pte_t *ptep); 1382 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1383 unsigned char key, bool nq); 1384 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1385 unsigned char key, unsigned char *oldkey, 1386 bool nq, bool mr, bool mc); 1387 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1388 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1389 unsigned char *key); 1390 1391 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1392 unsigned long bits, unsigned long value); 1393 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1394 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1395 unsigned long *oldpte, unsigned long *oldpgste); 1396 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1397 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1398 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1399 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1400 1401 #define pgprot_writecombine pgprot_writecombine 1402 pgprot_t pgprot_writecombine(pgprot_t prot); 1403 1404 #define pgprot_writethrough pgprot_writethrough 1405 pgprot_t pgprot_writethrough(pgprot_t prot); 1406 1407 #define PFN_PTE_SHIFT PAGE_SHIFT 1408 1409 /* 1410 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1411 * are within the same folio, PMD and VMA. 1412 */ 1413 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1414 pte_t *ptep, pte_t entry, unsigned int nr) 1415 { 1416 if (pte_present(entry)) 1417 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1418 if (mm_has_pgste(mm)) { 1419 for (;;) { 1420 ptep_set_pte_at(mm, addr, ptep, entry); 1421 if (--nr == 0) 1422 break; 1423 ptep++; 1424 entry = __pte(pte_val(entry) + PAGE_SIZE); 1425 addr += PAGE_SIZE; 1426 } 1427 } else { 1428 for (;;) { 1429 set_pte(ptep, entry); 1430 if (--nr == 0) 1431 break; 1432 ptep++; 1433 entry = __pte(pte_val(entry) + PAGE_SIZE); 1434 } 1435 } 1436 } 1437 #define set_ptes set_ptes 1438 1439 /* 1440 * Conversion functions: convert a page and protection to a page entry, 1441 * and a page entry and page directory to the page they refer to. 1442 */ 1443 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1444 { 1445 pte_t __pte; 1446 1447 __pte = __pte(physpage | pgprot_val(pgprot)); 1448 return pte_mkyoung(__pte); 1449 } 1450 1451 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1452 { 1453 unsigned long physpage = page_to_phys(page); 1454 pte_t __pte = mk_pte_phys(physpage, pgprot); 1455 1456 if (pte_write(__pte) && PageDirty(page)) 1457 __pte = pte_mkdirty(__pte); 1458 return __pte; 1459 } 1460 1461 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1462 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1463 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1464 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1465 1466 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1467 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1468 1469 static inline unsigned long pmd_deref(pmd_t pmd) 1470 { 1471 unsigned long origin_mask; 1472 1473 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1474 if (pmd_leaf(pmd)) 1475 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1476 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1477 } 1478 1479 static inline unsigned long pmd_pfn(pmd_t pmd) 1480 { 1481 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1482 } 1483 1484 static inline unsigned long pud_deref(pud_t pud) 1485 { 1486 unsigned long origin_mask; 1487 1488 origin_mask = _REGION_ENTRY_ORIGIN; 1489 if (pud_leaf(pud)) 1490 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1491 return (unsigned long)__va(pud_val(pud) & origin_mask); 1492 } 1493 1494 #define pud_pfn pud_pfn 1495 static inline unsigned long pud_pfn(pud_t pud) 1496 { 1497 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1498 } 1499 1500 /* 1501 * The pgd_offset function *always* adds the index for the top-level 1502 * region/segment table. This is done to get a sequence like the 1503 * following to work: 1504 * pgdp = pgd_offset(current->mm, addr); 1505 * pgd = READ_ONCE(*pgdp); 1506 * p4dp = p4d_offset(&pgd, addr); 1507 * ... 1508 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1509 * only add an index if they dereferenced the pointer. 1510 */ 1511 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1512 { 1513 unsigned long rste; 1514 unsigned int shift; 1515 1516 /* Get the first entry of the top level table */ 1517 rste = pgd_val(*pgd); 1518 /* Pick up the shift from the table type of the first entry */ 1519 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1520 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1521 } 1522 1523 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1524 1525 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1526 { 1527 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1528 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1529 return (p4d_t *) pgdp; 1530 } 1531 #define p4d_offset_lockless p4d_offset_lockless 1532 1533 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1534 { 1535 return p4d_offset_lockless(pgdp, *pgdp, address); 1536 } 1537 1538 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1539 { 1540 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1541 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1542 return (pud_t *) p4dp; 1543 } 1544 #define pud_offset_lockless pud_offset_lockless 1545 1546 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1547 { 1548 return pud_offset_lockless(p4dp, *p4dp, address); 1549 } 1550 #define pud_offset pud_offset 1551 1552 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1553 { 1554 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1555 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1556 return (pmd_t *) pudp; 1557 } 1558 #define pmd_offset_lockless pmd_offset_lockless 1559 1560 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1561 { 1562 return pmd_offset_lockless(pudp, *pudp, address); 1563 } 1564 #define pmd_offset pmd_offset 1565 1566 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1567 { 1568 return (unsigned long) pmd_deref(pmd); 1569 } 1570 1571 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1572 { 1573 return end <= current->mm->context.asce_limit; 1574 } 1575 #define gup_fast_permitted gup_fast_permitted 1576 1577 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1578 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1579 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1580 1581 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1582 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1583 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1584 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1585 1586 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1587 { 1588 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1589 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1590 } 1591 1592 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1593 { 1594 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1595 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1596 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1597 return pmd; 1598 } 1599 1600 static inline pmd_t pmd_mkclean(pmd_t pmd) 1601 { 1602 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1603 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1604 } 1605 1606 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1607 { 1608 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1609 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1610 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1611 return pmd; 1612 } 1613 1614 static inline pud_t pud_wrprotect(pud_t pud) 1615 { 1616 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1617 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1618 } 1619 1620 static inline pud_t pud_mkwrite(pud_t pud) 1621 { 1622 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1623 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1624 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1625 return pud; 1626 } 1627 1628 static inline pud_t pud_mkclean(pud_t pud) 1629 { 1630 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1631 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1632 } 1633 1634 static inline pud_t pud_mkdirty(pud_t pud) 1635 { 1636 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1637 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1638 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1639 return pud; 1640 } 1641 1642 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1643 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1644 { 1645 /* 1646 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1647 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1648 */ 1649 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1650 return pgprot_val(SEGMENT_NONE); 1651 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1652 return pgprot_val(SEGMENT_RO); 1653 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1654 return pgprot_val(SEGMENT_RX); 1655 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1656 return pgprot_val(SEGMENT_RW); 1657 return pgprot_val(SEGMENT_RWX); 1658 } 1659 1660 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1661 { 1662 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1663 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1664 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1665 return pmd; 1666 } 1667 1668 static inline pmd_t pmd_mkold(pmd_t pmd) 1669 { 1670 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1671 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1672 } 1673 1674 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1675 { 1676 unsigned long mask; 1677 1678 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1679 mask |= _SEGMENT_ENTRY_DIRTY; 1680 mask |= _SEGMENT_ENTRY_YOUNG; 1681 mask |= _SEGMENT_ENTRY_LARGE; 1682 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1683 pmd = __pmd(pmd_val(pmd) & mask); 1684 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1685 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1686 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1687 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1688 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1689 return pmd; 1690 } 1691 1692 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1693 { 1694 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1695 } 1696 1697 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1698 1699 static inline void __pmdp_csp(pmd_t *pmdp) 1700 { 1701 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1702 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1703 } 1704 1705 #define IDTE_GLOBAL 0 1706 #define IDTE_LOCAL 1 1707 1708 #define IDTE_PTOA 0x0800 1709 #define IDTE_NODAT 0x1000 1710 #define IDTE_GUEST_ASCE 0x2000 1711 1712 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1713 unsigned long opt, unsigned long asce, 1714 int local) 1715 { 1716 unsigned long sto; 1717 1718 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1719 if (__builtin_constant_p(opt) && opt == 0) { 1720 /* flush without guest asce */ 1721 asm volatile( 1722 " idte %[r1],0,%[r2],%[m4]" 1723 : "+m" (*pmdp) 1724 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1725 [m4] "i" (local) 1726 : "cc" ); 1727 } else { 1728 /* flush with guest asce */ 1729 asm volatile( 1730 " idte %[r1],%[r3],%[r2],%[m4]" 1731 : "+m" (*pmdp) 1732 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1733 [r3] "a" (asce), [m4] "i" (local) 1734 : "cc" ); 1735 } 1736 } 1737 1738 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1739 unsigned long opt, unsigned long asce, 1740 int local) 1741 { 1742 unsigned long r3o; 1743 1744 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1745 r3o |= _ASCE_TYPE_REGION3; 1746 if (__builtin_constant_p(opt) && opt == 0) { 1747 /* flush without guest asce */ 1748 asm volatile( 1749 " idte %[r1],0,%[r2],%[m4]" 1750 : "+m" (*pudp) 1751 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1752 [m4] "i" (local) 1753 : "cc"); 1754 } else { 1755 /* flush with guest asce */ 1756 asm volatile( 1757 " idte %[r1],%[r3],%[r2],%[m4]" 1758 : "+m" (*pudp) 1759 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1760 [r3] "a" (asce), [m4] "i" (local) 1761 : "cc" ); 1762 } 1763 } 1764 1765 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1766 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1767 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1768 1769 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1770 1771 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1772 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1773 pgtable_t pgtable); 1774 1775 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1776 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1777 1778 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1779 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1780 unsigned long addr, pmd_t *pmdp, 1781 pmd_t entry, int dirty) 1782 { 1783 VM_BUG_ON(addr & ~HPAGE_MASK); 1784 1785 entry = pmd_mkyoung(entry); 1786 if (dirty) 1787 entry = pmd_mkdirty(entry); 1788 if (pmd_val(*pmdp) == pmd_val(entry)) 1789 return 0; 1790 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1791 return 1; 1792 } 1793 1794 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1795 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1796 unsigned long addr, pmd_t *pmdp) 1797 { 1798 pmd_t pmd = *pmdp; 1799 1800 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1801 return pmd_young(pmd); 1802 } 1803 1804 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1805 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1806 unsigned long addr, pmd_t *pmdp) 1807 { 1808 VM_BUG_ON(addr & ~HPAGE_MASK); 1809 return pmdp_test_and_clear_young(vma, addr, pmdp); 1810 } 1811 1812 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1813 pmd_t *pmdp, pmd_t entry) 1814 { 1815 set_pmd(pmdp, entry); 1816 } 1817 1818 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1819 { 1820 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1821 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1822 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1823 } 1824 1825 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1826 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1827 unsigned long addr, pmd_t *pmdp) 1828 { 1829 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1830 } 1831 1832 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1833 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1834 unsigned long addr, 1835 pmd_t *pmdp, int full) 1836 { 1837 if (full) { 1838 pmd_t pmd = *pmdp; 1839 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1840 return pmd; 1841 } 1842 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1843 } 1844 1845 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1846 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1847 unsigned long addr, pmd_t *pmdp) 1848 { 1849 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1850 } 1851 1852 #define __HAVE_ARCH_PMDP_INVALIDATE 1853 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1854 unsigned long addr, pmd_t *pmdp) 1855 { 1856 pmd_t pmd; 1857 1858 VM_WARN_ON_ONCE(!pmd_present(*pmdp)); 1859 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1860 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1861 } 1862 1863 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1864 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1865 unsigned long addr, pmd_t *pmdp) 1866 { 1867 pmd_t pmd = *pmdp; 1868 1869 if (pmd_write(pmd)) 1870 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1871 } 1872 1873 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1874 unsigned long address, 1875 pmd_t *pmdp) 1876 { 1877 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1878 } 1879 #define pmdp_collapse_flush pmdp_collapse_flush 1880 1881 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1882 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1883 1884 static inline int pmd_trans_huge(pmd_t pmd) 1885 { 1886 return pmd_leaf(pmd); 1887 } 1888 1889 #define has_transparent_hugepage has_transparent_hugepage 1890 static inline int has_transparent_hugepage(void) 1891 { 1892 return MACHINE_HAS_EDAT1 ? 1 : 0; 1893 } 1894 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1895 1896 /* 1897 * 64 bit swap entry format: 1898 * A page-table entry has some bits we have to treat in a special way. 1899 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1900 * as invalid. 1901 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1902 * | offset |E11XX|type |S0| 1903 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1904 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1905 * 1906 * Bits 0-51 store the offset. 1907 * Bit 52 (E) is used to remember PG_anon_exclusive. 1908 * Bits 57-61 store the type. 1909 * Bit 62 (S) is used for softdirty tracking. 1910 * Bits 55 and 56 (X) are unused. 1911 */ 1912 1913 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1914 #define __SWP_OFFSET_SHIFT 12 1915 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1916 #define __SWP_TYPE_SHIFT 2 1917 1918 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1919 { 1920 unsigned long pteval; 1921 1922 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1923 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1924 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1925 return __pte(pteval); 1926 } 1927 1928 static inline unsigned long __swp_type(swp_entry_t entry) 1929 { 1930 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1931 } 1932 1933 static inline unsigned long __swp_offset(swp_entry_t entry) 1934 { 1935 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1936 } 1937 1938 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1939 { 1940 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1941 } 1942 1943 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1944 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1945 1946 /* 1947 * 64 bit swap entry format for REGION3 and SEGMENT table entries (RSTE) 1948 * Bits 59 and 63 are used to indicate the swap entry. Bit 58 marks the rste 1949 * as invalid. 1950 * A swap entry is indicated by bit pattern (rste & 0x011) == 0x010 1951 * | offset |Xtype |11TT|S0| 1952 * |0000000000111111111122222222223333333333444444444455|555555|5566|66| 1953 * |0123456789012345678901234567890123456789012345678901|234567|8901|23| 1954 * 1955 * Bits 0-51 store the offset. 1956 * Bits 53-57 store the type. 1957 * Bit 62 (S) is used for softdirty tracking. 1958 * Bits 60-61 (TT) indicate the table type: 0x01 for REGION3 and 0x00 for SEGMENT. 1959 * Bit 52 (X) is unused. 1960 */ 1961 1962 #define __SWP_OFFSET_MASK_RSTE ((1UL << 52) - 1) 1963 #define __SWP_OFFSET_SHIFT_RSTE 12 1964 #define __SWP_TYPE_MASK_RSTE ((1UL << 5) - 1) 1965 #define __SWP_TYPE_SHIFT_RSTE 6 1966 1967 /* 1968 * TT bits set to 0x00 == SEGMENT. For REGION3 entries, caller must add R3 1969 * bits 0x01. See also __set_huge_pte_at(). 1970 */ 1971 static inline unsigned long mk_swap_rste(unsigned long type, unsigned long offset) 1972 { 1973 unsigned long rste; 1974 1975 rste = _RST_ENTRY_INVALID | _RST_ENTRY_COMM; 1976 rste |= (offset & __SWP_OFFSET_MASK_RSTE) << __SWP_OFFSET_SHIFT_RSTE; 1977 rste |= (type & __SWP_TYPE_MASK_RSTE) << __SWP_TYPE_SHIFT_RSTE; 1978 return rste; 1979 } 1980 1981 static inline unsigned long __swp_type_rste(swp_entry_t entry) 1982 { 1983 return (entry.val >> __SWP_TYPE_SHIFT_RSTE) & __SWP_TYPE_MASK_RSTE; 1984 } 1985 1986 static inline unsigned long __swp_offset_rste(swp_entry_t entry) 1987 { 1988 return (entry.val >> __SWP_OFFSET_SHIFT_RSTE) & __SWP_OFFSET_MASK_RSTE; 1989 } 1990 1991 #define __rste_to_swp_entry(rste) ((swp_entry_t) { rste }) 1992 1993 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1994 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1995 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1996 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1997 extern void vmem_unmap_4k_page(unsigned long addr); 1998 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1999 extern int s390_enable_sie(void); 2000 extern int s390_enable_skey(void); 2001 extern void s390_reset_cmma(struct mm_struct *mm); 2002 2003 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 2004 #define HAVE_ARCH_UNMAPPED_AREA 2005 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 2006 2007 #define pmd_pgtable(pmd) \ 2008 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 2009 2010 #endif /* _S390_PAGE_H */ 2011