1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <linux/page-flags.h> 33 #include <asm/bug.h> 34 #include <asm/page.h> 35 36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 37 extern void paging_init(void); 38 extern void vmem_map_init(void); 39 40 /* 41 * The S390 doesn't have any external MMU info: the kernel page 42 * tables contain all the necessary information. 43 */ 44 #define update_mmu_cache(vma, address, ptep) do { } while (0) 45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 46 47 /* 48 * ZERO_PAGE is a global shared page that is always zero; used 49 * for zero-mapped memory areas etc.. 50 */ 51 52 extern unsigned long empty_zero_page; 53 extern unsigned long zero_page_mask; 54 55 #define ZERO_PAGE(vaddr) \ 56 (virt_to_page((void *)(empty_zero_page + \ 57 (((unsigned long)(vaddr)) &zero_page_mask)))) 58 #define __HAVE_COLOR_ZERO_PAGE 59 60 /* TODO: s390 cannot support io_remap_pfn_range... */ 61 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 62 remap_pfn_range(vma, vaddr, pfn, size, prot) 63 64 #endif /* !__ASSEMBLY__ */ 65 66 /* 67 * PMD_SHIFT determines the size of the area a second-level page 68 * table can map 69 * PGDIR_SHIFT determines what a third-level page table entry can map 70 */ 71 #ifndef CONFIG_64BIT 72 # define PMD_SHIFT 20 73 # define PUD_SHIFT 20 74 # define PGDIR_SHIFT 20 75 #else /* CONFIG_64BIT */ 76 # define PMD_SHIFT 20 77 # define PUD_SHIFT 31 78 # define PGDIR_SHIFT 42 79 #endif /* CONFIG_64BIT */ 80 81 #define PMD_SIZE (1UL << PMD_SHIFT) 82 #define PMD_MASK (~(PMD_SIZE-1)) 83 #define PUD_SIZE (1UL << PUD_SHIFT) 84 #define PUD_MASK (~(PUD_SIZE-1)) 85 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 86 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 87 88 /* 89 * entries per page directory level: the S390 is two-level, so 90 * we don't really have any PMD directory physically. 91 * for S390 segment-table entries are combined to one PGD 92 * that leads to 1024 pte per pgd 93 */ 94 #define PTRS_PER_PTE 256 95 #ifndef CONFIG_64BIT 96 #define PTRS_PER_PMD 1 97 #define PTRS_PER_PUD 1 98 #else /* CONFIG_64BIT */ 99 #define PTRS_PER_PMD 2048 100 #define PTRS_PER_PUD 2048 101 #endif /* CONFIG_64BIT */ 102 #define PTRS_PER_PGD 2048 103 104 #define FIRST_USER_ADDRESS 0 105 106 #define pte_ERROR(e) \ 107 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 108 #define pmd_ERROR(e) \ 109 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 110 #define pud_ERROR(e) \ 111 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 112 #define pgd_ERROR(e) \ 113 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 114 115 #ifndef __ASSEMBLY__ 116 /* 117 * The vmalloc and module area will always be on the topmost area of the kernel 118 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 119 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 120 * modules will reside. That makes sure that inter module branches always 121 * happen without trampolines and in addition the placement within a 2GB frame 122 * is branch prediction unit friendly. 123 */ 124 extern unsigned long VMALLOC_START; 125 extern unsigned long VMALLOC_END; 126 extern struct page *vmemmap; 127 128 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 129 130 #ifdef CONFIG_64BIT 131 extern unsigned long MODULES_VADDR; 132 extern unsigned long MODULES_END; 133 #define MODULES_VADDR MODULES_VADDR 134 #define MODULES_END MODULES_END 135 #define MODULES_LEN (1UL << 31) 136 #endif 137 138 /* 139 * A 31 bit pagetable entry of S390 has following format: 140 * | PFRA | | OS | 141 * 0 0IP0 142 * 00000000001111111111222222222233 143 * 01234567890123456789012345678901 144 * 145 * I Page-Invalid Bit: Page is not available for address-translation 146 * P Page-Protection Bit: Store access not possible for page 147 * 148 * A 31 bit segmenttable entry of S390 has following format: 149 * | P-table origin | |PTL 150 * 0 IC 151 * 00000000001111111111222222222233 152 * 01234567890123456789012345678901 153 * 154 * I Segment-Invalid Bit: Segment is not available for address-translation 155 * C Common-Segment Bit: Segment is not private (PoP 3-30) 156 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 157 * 158 * The 31 bit segmenttable origin of S390 has following format: 159 * 160 * |S-table origin | | STL | 161 * X **GPS 162 * 00000000001111111111222222222233 163 * 01234567890123456789012345678901 164 * 165 * X Space-Switch event: 166 * G Segment-Invalid Bit: * 167 * P Private-Space Bit: Segment is not private (PoP 3-30) 168 * S Storage-Alteration: 169 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 170 * 171 * A 64 bit pagetable entry of S390 has following format: 172 * | PFRA |0IPC| OS | 173 * 0000000000111111111122222222223333333333444444444455555555556666 174 * 0123456789012345678901234567890123456789012345678901234567890123 175 * 176 * I Page-Invalid Bit: Page is not available for address-translation 177 * P Page-Protection Bit: Store access not possible for page 178 * C Change-bit override: HW is not required to set change bit 179 * 180 * A 64 bit segmenttable entry of S390 has following format: 181 * | P-table origin | TT 182 * 0000000000111111111122222222223333333333444444444455555555556666 183 * 0123456789012345678901234567890123456789012345678901234567890123 184 * 185 * I Segment-Invalid Bit: Segment is not available for address-translation 186 * C Common-Segment Bit: Segment is not private (PoP 3-30) 187 * P Page-Protection Bit: Store access not possible for page 188 * TT Type 00 189 * 190 * A 64 bit region table entry of S390 has following format: 191 * | S-table origin | TF TTTL 192 * 0000000000111111111122222222223333333333444444444455555555556666 193 * 0123456789012345678901234567890123456789012345678901234567890123 194 * 195 * I Segment-Invalid Bit: Segment is not available for address-translation 196 * TT Type 01 197 * TF 198 * TL Table length 199 * 200 * The 64 bit regiontable origin of S390 has following format: 201 * | region table origon | DTTL 202 * 0000000000111111111122222222223333333333444444444455555555556666 203 * 0123456789012345678901234567890123456789012345678901234567890123 204 * 205 * X Space-Switch event: 206 * G Segment-Invalid Bit: 207 * P Private-Space Bit: 208 * S Storage-Alteration: 209 * R Real space 210 * TL Table-Length: 211 * 212 * A storage key has the following format: 213 * | ACC |F|R|C|0| 214 * 0 3 4 5 6 7 215 * ACC: access key 216 * F : fetch protection bit 217 * R : referenced bit 218 * C : changed bit 219 */ 220 221 /* Hardware bits in the page table entry */ 222 #define _PAGE_CO 0x100 /* HW Change-bit override */ 223 #define _PAGE_RO 0x200 /* HW read-only bit */ 224 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 225 226 /* Software bits in the page table entry */ 227 #define _PAGE_SWT 0x001 /* SW pte type bit t */ 228 #define _PAGE_SWX 0x002 /* SW pte type bit x */ 229 #define _PAGE_SWC 0x004 /* SW pte changed bit */ 230 #define _PAGE_SWR 0x008 /* SW pte referenced bit */ 231 #define _PAGE_SWW 0x010 /* SW pte write bit */ 232 #define _PAGE_SPECIAL 0x020 /* SW associated with special page */ 233 #define __HAVE_ARCH_PTE_SPECIAL 234 235 /* Set of bits not changed in pte_modify */ 236 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \ 237 _PAGE_SWC | _PAGE_SWR) 238 239 /* Six different types of pages. */ 240 #define _PAGE_TYPE_EMPTY 0x400 241 #define _PAGE_TYPE_NONE 0x401 242 #define _PAGE_TYPE_SWAP 0x403 243 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ 244 #define _PAGE_TYPE_RO 0x200 245 #define _PAGE_TYPE_RW 0x000 246 247 /* 248 * Only four types for huge pages, using the invalid bit and protection bit 249 * of a segment table entry. 250 */ 251 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ 252 #define _HPAGE_TYPE_NONE 0x220 253 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ 254 #define _HPAGE_TYPE_RW 0x000 255 256 /* 257 * PTE type bits are rather complicated. handle_pte_fault uses pte_present, 258 * pte_none and pte_file to find out the pte type WITHOUT holding the page 259 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to 260 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs 261 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. 262 * This change is done while holding the lock, but the intermediate step 263 * of a previously valid pte with the hw invalid bit set can be observed by 264 * handle_pte_fault. That makes it necessary that all valid pte types with 265 * the hw invalid bit set must be distinguishable from the four pte types 266 * empty, none, swap and file. 267 * 268 * irxt ipte irxt 269 * _PAGE_TYPE_EMPTY 1000 -> 1000 270 * _PAGE_TYPE_NONE 1001 -> 1001 271 * _PAGE_TYPE_SWAP 1011 -> 1011 272 * _PAGE_TYPE_FILE 11?1 -> 11?1 273 * _PAGE_TYPE_RO 0100 -> 1100 274 * _PAGE_TYPE_RW 0000 -> 1000 275 * 276 * pte_none is true for bits combinations 1000, 1010, 1100, 1110 277 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 278 * pte_file is true for bits combinations 1101, 1111 279 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. 280 */ 281 282 #ifndef CONFIG_64BIT 283 284 /* Bits in the segment table address-space-control-element */ 285 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 286 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 287 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 288 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 289 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 290 291 /* Bits in the segment table entry */ 292 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 293 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 294 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 295 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 296 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 297 298 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 299 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 300 301 /* Page status table bits for virtualization */ 302 #define RCP_ACC_BITS 0xf0000000UL 303 #define RCP_FP_BIT 0x08000000UL 304 #define RCP_PCL_BIT 0x00800000UL 305 #define RCP_HR_BIT 0x00400000UL 306 #define RCP_HC_BIT 0x00200000UL 307 #define RCP_GR_BIT 0x00040000UL 308 #define RCP_GC_BIT 0x00020000UL 309 #define RCP_IN_BIT 0x00002000UL /* IPTE notify bit */ 310 311 /* User dirty / referenced bit for KVM's migration feature */ 312 #define KVM_UR_BIT 0x00008000UL 313 #define KVM_UC_BIT 0x00004000UL 314 315 #else /* CONFIG_64BIT */ 316 317 /* Bits in the segment/region table address-space-control-element */ 318 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 319 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 320 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 321 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 322 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 323 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 324 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 325 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 326 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 327 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 328 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 329 330 /* Bits in the region table entry */ 331 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 332 #define _REGION_ENTRY_RO 0x200 /* region protection bit */ 333 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 334 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 335 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 336 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 337 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 338 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 339 340 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 341 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) 342 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 343 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) 344 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 345 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) 346 347 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 348 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */ 349 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */ 350 351 /* Bits in the segment table entry */ 352 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 353 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 354 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 355 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 356 357 #define _SEGMENT_ENTRY (0) 358 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 359 360 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 361 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 362 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 363 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT) 364 365 /* Set of bits not changed in pmd_modify */ 366 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 367 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 368 369 /* Page status table bits for virtualization */ 370 #define RCP_ACC_BITS 0xf000000000000000UL 371 #define RCP_FP_BIT 0x0800000000000000UL 372 #define RCP_PCL_BIT 0x0080000000000000UL 373 #define RCP_HR_BIT 0x0040000000000000UL 374 #define RCP_HC_BIT 0x0020000000000000UL 375 #define RCP_GR_BIT 0x0004000000000000UL 376 #define RCP_GC_BIT 0x0002000000000000UL 377 #define RCP_IN_BIT 0x0000200000000000UL /* IPTE notify bit */ 378 379 /* User dirty / referenced bit for KVM's migration feature */ 380 #define KVM_UR_BIT 0x0000800000000000UL 381 #define KVM_UC_BIT 0x0000400000000000UL 382 383 #endif /* CONFIG_64BIT */ 384 385 /* 386 * A user page table pointer has the space-switch-event bit, the 387 * private-space-control bit and the storage-alteration-event-control 388 * bit set. A kernel page table pointer doesn't need them. 389 */ 390 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 391 _ASCE_ALT_EVENT) 392 393 /* 394 * Page protection definitions. 395 */ 396 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) 397 #define PAGE_RO __pgprot(_PAGE_TYPE_RO) 398 #define PAGE_RW __pgprot(_PAGE_TYPE_RO | _PAGE_SWW) 399 #define PAGE_RWC __pgprot(_PAGE_TYPE_RW | _PAGE_SWW | _PAGE_SWC) 400 401 #define PAGE_KERNEL PAGE_RWC 402 #define PAGE_SHARED PAGE_KERNEL 403 #define PAGE_COPY PAGE_RO 404 405 /* 406 * On s390 the page table entry has an invalid bit and a read-only bit. 407 * Read permission implies execute permission and write permission 408 * implies read permission. 409 */ 410 /*xwr*/ 411 #define __P000 PAGE_NONE 412 #define __P001 PAGE_RO 413 #define __P010 PAGE_RO 414 #define __P011 PAGE_RO 415 #define __P100 PAGE_RO 416 #define __P101 PAGE_RO 417 #define __P110 PAGE_RO 418 #define __P111 PAGE_RO 419 420 #define __S000 PAGE_NONE 421 #define __S001 PAGE_RO 422 #define __S010 PAGE_RW 423 #define __S011 PAGE_RW 424 #define __S100 PAGE_RO 425 #define __S101 PAGE_RO 426 #define __S110 PAGE_RW 427 #define __S111 PAGE_RW 428 429 /* 430 * Segment entry (large page) protection definitions. 431 */ 432 #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE) 433 #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO) 434 #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW) 435 436 static inline int mm_exclusive(struct mm_struct *mm) 437 { 438 return likely(mm == current->active_mm && 439 atomic_read(&mm->context.attach_count) <= 1); 440 } 441 442 static inline int mm_has_pgste(struct mm_struct *mm) 443 { 444 #ifdef CONFIG_PGSTE 445 if (unlikely(mm->context.has_pgste)) 446 return 1; 447 #endif 448 return 0; 449 } 450 /* 451 * pgd/pmd/pte query functions 452 */ 453 #ifndef CONFIG_64BIT 454 455 static inline int pgd_present(pgd_t pgd) { return 1; } 456 static inline int pgd_none(pgd_t pgd) { return 0; } 457 static inline int pgd_bad(pgd_t pgd) { return 0; } 458 459 static inline int pud_present(pud_t pud) { return 1; } 460 static inline int pud_none(pud_t pud) { return 0; } 461 static inline int pud_large(pud_t pud) { return 0; } 462 static inline int pud_bad(pud_t pud) { return 0; } 463 464 #else /* CONFIG_64BIT */ 465 466 static inline int pgd_present(pgd_t pgd) 467 { 468 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 469 return 1; 470 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 471 } 472 473 static inline int pgd_none(pgd_t pgd) 474 { 475 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 476 return 0; 477 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; 478 } 479 480 static inline int pgd_bad(pgd_t pgd) 481 { 482 /* 483 * With dynamic page table levels the pgd can be a region table 484 * entry or a segment table entry. Check for the bit that are 485 * invalid for either table entry. 486 */ 487 unsigned long mask = 488 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 489 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 490 return (pgd_val(pgd) & mask) != 0; 491 } 492 493 static inline int pud_present(pud_t pud) 494 { 495 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 496 return 1; 497 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 498 } 499 500 static inline int pud_none(pud_t pud) 501 { 502 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 503 return 0; 504 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; 505 } 506 507 static inline int pud_large(pud_t pud) 508 { 509 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 510 return 0; 511 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 512 } 513 514 static inline int pud_bad(pud_t pud) 515 { 516 /* 517 * With dynamic page table levels the pud can be a region table 518 * entry or a segment table entry. Check for the bit that are 519 * invalid for either table entry. 520 */ 521 unsigned long mask = 522 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 523 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 524 return (pud_val(pud) & mask) != 0; 525 } 526 527 #endif /* CONFIG_64BIT */ 528 529 static inline int pmd_present(pmd_t pmd) 530 { 531 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO; 532 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE || 533 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV); 534 } 535 536 static inline int pmd_none(pmd_t pmd) 537 { 538 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) && 539 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO); 540 } 541 542 static inline int pmd_large(pmd_t pmd) 543 { 544 #ifdef CONFIG_64BIT 545 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE); 546 #else 547 return 0; 548 #endif 549 } 550 551 static inline int pmd_bad(pmd_t pmd) 552 { 553 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; 554 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; 555 } 556 557 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 558 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 559 unsigned long addr, pmd_t *pmdp); 560 561 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 562 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 563 unsigned long address, pmd_t *pmdp, 564 pmd_t entry, int dirty); 565 566 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 567 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 568 unsigned long address, pmd_t *pmdp); 569 570 #define __HAVE_ARCH_PMD_WRITE 571 static inline int pmd_write(pmd_t pmd) 572 { 573 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0; 574 } 575 576 static inline int pmd_young(pmd_t pmd) 577 { 578 return 0; 579 } 580 581 static inline int pte_none(pte_t pte) 582 { 583 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); 584 } 585 586 static inline int pte_present(pte_t pte) 587 { 588 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; 589 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || 590 (!(pte_val(pte) & _PAGE_INVALID) && 591 !(pte_val(pte) & _PAGE_SWT)); 592 } 593 594 static inline int pte_file(pte_t pte) 595 { 596 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; 597 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; 598 } 599 600 static inline int pte_special(pte_t pte) 601 { 602 return (pte_val(pte) & _PAGE_SPECIAL); 603 } 604 605 #define __HAVE_ARCH_PTE_SAME 606 static inline int pte_same(pte_t a, pte_t b) 607 { 608 return pte_val(a) == pte_val(b); 609 } 610 611 static inline pgste_t pgste_get_lock(pte_t *ptep) 612 { 613 unsigned long new = 0; 614 #ifdef CONFIG_PGSTE 615 unsigned long old; 616 617 preempt_disable(); 618 asm( 619 " lg %0,%2\n" 620 "0: lgr %1,%0\n" 621 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */ 622 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */ 623 " csg %0,%1,%2\n" 624 " jl 0b\n" 625 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 626 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory"); 627 #endif 628 return __pgste(new); 629 } 630 631 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 632 { 633 #ifdef CONFIG_PGSTE 634 asm( 635 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ 636 " stg %1,%0\n" 637 : "=Q" (ptep[PTRS_PER_PTE]) 638 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) 639 : "cc", "memory"); 640 preempt_enable(); 641 #endif 642 } 643 644 static inline void pgste_set(pte_t *ptep, pgste_t pgste) 645 { 646 #ifdef CONFIG_PGSTE 647 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste; 648 #endif 649 } 650 651 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 652 { 653 #ifdef CONFIG_PGSTE 654 unsigned long address, bits; 655 unsigned char skey; 656 657 if (pte_val(*ptep) & _PAGE_INVALID) 658 return pgste; 659 address = pte_val(*ptep) & PAGE_MASK; 660 skey = page_get_storage_key(address); 661 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 662 /* Clear page changed & referenced bit in the storage key */ 663 if (bits & _PAGE_CHANGED) 664 page_set_storage_key(address, skey ^ bits, 0); 665 else if (bits) 666 page_reset_referenced(address); 667 /* Transfer page changed & referenced bit to guest bits in pgste */ 668 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */ 669 /* Get host changed & referenced bits from pgste */ 670 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52; 671 /* Transfer page changed & referenced bit to kvm user bits */ 672 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */ 673 /* Clear relevant host bits in pgste. */ 674 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT); 675 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT); 676 /* Copy page access key and fetch protection bit to pgste */ 677 pgste_val(pgste) |= 678 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 679 /* Transfer referenced bit to pte */ 680 pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1; 681 #endif 682 return pgste; 683 684 } 685 686 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) 687 { 688 #ifdef CONFIG_PGSTE 689 int young; 690 691 if (pte_val(*ptep) & _PAGE_INVALID) 692 return pgste; 693 /* Get referenced bit from storage key */ 694 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); 695 if (young) 696 pgste_val(pgste) |= RCP_GR_BIT; 697 /* Get host referenced bit from pgste */ 698 if (pgste_val(pgste) & RCP_HR_BIT) { 699 pgste_val(pgste) &= ~RCP_HR_BIT; 700 young = 1; 701 } 702 /* Transfer referenced bit to kvm user bits and pte */ 703 if (young) { 704 pgste_val(pgste) |= KVM_UR_BIT; 705 pte_val(*ptep) |= _PAGE_SWR; 706 } 707 #endif 708 return pgste; 709 } 710 711 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) 712 { 713 #ifdef CONFIG_PGSTE 714 unsigned long address; 715 unsigned long nkey; 716 717 if (pte_val(entry) & _PAGE_INVALID) 718 return; 719 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); 720 address = pte_val(entry) & PAGE_MASK; 721 /* 722 * Set page access key and fetch protection bit from pgste. 723 * The guest C/R information is still in the PGSTE, set real 724 * key C/R to 0. 725 */ 726 nkey = (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; 727 page_set_storage_key(address, nkey, 0); 728 #endif 729 } 730 731 static inline void pgste_set_pte(pte_t *ptep, pte_t entry) 732 { 733 if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_SWW)) { 734 /* 735 * Without enhanced suppression-on-protection force 736 * the dirty bit on for all writable ptes. 737 */ 738 pte_val(entry) |= _PAGE_SWC; 739 pte_val(entry) &= ~_PAGE_RO; 740 } 741 *ptep = entry; 742 } 743 744 /** 745 * struct gmap_struct - guest address space 746 * @mm: pointer to the parent mm_struct 747 * @table: pointer to the page directory 748 * @asce: address space control element for gmap page table 749 * @crst_list: list of all crst tables used in the guest address space 750 */ 751 struct gmap { 752 struct list_head list; 753 struct mm_struct *mm; 754 unsigned long *table; 755 unsigned long asce; 756 struct list_head crst_list; 757 }; 758 759 /** 760 * struct gmap_rmap - reverse mapping for segment table entries 761 * @gmap: pointer to the gmap_struct 762 * @entry: pointer to a segment table entry 763 * @vmaddr: virtual address in the guest address space 764 */ 765 struct gmap_rmap { 766 struct list_head list; 767 struct gmap *gmap; 768 unsigned long *entry; 769 unsigned long vmaddr; 770 }; 771 772 /** 773 * struct gmap_pgtable - gmap information attached to a page table 774 * @vmaddr: address of the 1MB segment in the process virtual memory 775 * @mapper: list of segment table entries mapping a page table 776 */ 777 struct gmap_pgtable { 778 unsigned long vmaddr; 779 struct list_head mapper; 780 }; 781 782 /** 783 * struct gmap_notifier - notify function block for page invalidation 784 * @notifier_call: address of callback function 785 */ 786 struct gmap_notifier { 787 struct list_head list; 788 void (*notifier_call)(struct gmap *gmap, unsigned long address); 789 }; 790 791 struct gmap *gmap_alloc(struct mm_struct *mm); 792 void gmap_free(struct gmap *gmap); 793 void gmap_enable(struct gmap *gmap); 794 void gmap_disable(struct gmap *gmap); 795 int gmap_map_segment(struct gmap *gmap, unsigned long from, 796 unsigned long to, unsigned long len); 797 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 798 unsigned long __gmap_translate(unsigned long address, struct gmap *); 799 unsigned long gmap_translate(unsigned long address, struct gmap *); 800 unsigned long __gmap_fault(unsigned long address, struct gmap *); 801 unsigned long gmap_fault(unsigned long address, struct gmap *); 802 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 803 804 void gmap_register_ipte_notifier(struct gmap_notifier *); 805 void gmap_unregister_ipte_notifier(struct gmap_notifier *); 806 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len); 807 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *); 808 809 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm, 810 unsigned long addr, 811 pte_t *ptep, pgste_t pgste) 812 { 813 #ifdef CONFIG_PGSTE 814 if (pgste_val(pgste) & RCP_IN_BIT) { 815 pgste_val(pgste) &= ~RCP_IN_BIT; 816 gmap_do_ipte_notify(mm, addr, ptep); 817 } 818 #endif 819 return pgste; 820 } 821 822 /* 823 * Certain architectures need to do special things when PTEs 824 * within a page table are directly modified. Thus, the following 825 * hook is made available. 826 */ 827 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 828 pte_t *ptep, pte_t entry) 829 { 830 pgste_t pgste; 831 832 if (mm_has_pgste(mm)) { 833 pgste = pgste_get_lock(ptep); 834 pgste_set_key(ptep, pgste, entry); 835 pgste_set_pte(ptep, entry); 836 pgste_set_unlock(ptep, pgste); 837 } else { 838 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) 839 pte_val(entry) |= _PAGE_CO; 840 *ptep = entry; 841 } 842 } 843 844 /* 845 * query functions pte_write/pte_dirty/pte_young only work if 846 * pte_present() is true. Undefined behaviour if not.. 847 */ 848 static inline int pte_write(pte_t pte) 849 { 850 return (pte_val(pte) & _PAGE_SWW) != 0; 851 } 852 853 static inline int pte_dirty(pte_t pte) 854 { 855 return (pte_val(pte) & _PAGE_SWC) != 0; 856 } 857 858 static inline int pte_young(pte_t pte) 859 { 860 #ifdef CONFIG_PGSTE 861 if (pte_val(pte) & _PAGE_SWR) 862 return 1; 863 #endif 864 return 0; 865 } 866 867 /* 868 * pgd/pmd/pte modification functions 869 */ 870 871 static inline void pgd_clear(pgd_t *pgd) 872 { 873 #ifdef CONFIG_64BIT 874 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 875 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 876 #endif 877 } 878 879 static inline void pud_clear(pud_t *pud) 880 { 881 #ifdef CONFIG_64BIT 882 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 883 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 884 #endif 885 } 886 887 static inline void pmd_clear(pmd_t *pmdp) 888 { 889 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 890 } 891 892 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 893 { 894 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 895 } 896 897 /* 898 * The following pte modification functions only work if 899 * pte_present() is true. Undefined behaviour if not.. 900 */ 901 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 902 { 903 pte_val(pte) &= _PAGE_CHG_MASK; 904 pte_val(pte) |= pgprot_val(newprot); 905 if ((pte_val(pte) & _PAGE_SWC) && (pte_val(pte) & _PAGE_SWW)) 906 pte_val(pte) &= ~_PAGE_RO; 907 return pte; 908 } 909 910 static inline pte_t pte_wrprotect(pte_t pte) 911 { 912 pte_val(pte) &= ~_PAGE_SWW; 913 /* Do not clobber _PAGE_TYPE_NONE pages! */ 914 if (!(pte_val(pte) & _PAGE_INVALID)) 915 pte_val(pte) |= _PAGE_RO; 916 return pte; 917 } 918 919 static inline pte_t pte_mkwrite(pte_t pte) 920 { 921 pte_val(pte) |= _PAGE_SWW; 922 if (pte_val(pte) & _PAGE_SWC) 923 pte_val(pte) &= ~_PAGE_RO; 924 return pte; 925 } 926 927 static inline pte_t pte_mkclean(pte_t pte) 928 { 929 pte_val(pte) &= ~_PAGE_SWC; 930 /* Do not clobber _PAGE_TYPE_NONE pages! */ 931 if (!(pte_val(pte) & _PAGE_INVALID)) 932 pte_val(pte) |= _PAGE_RO; 933 return pte; 934 } 935 936 static inline pte_t pte_mkdirty(pte_t pte) 937 { 938 pte_val(pte) |= _PAGE_SWC; 939 if (pte_val(pte) & _PAGE_SWW) 940 pte_val(pte) &= ~_PAGE_RO; 941 return pte; 942 } 943 944 static inline pte_t pte_mkold(pte_t pte) 945 { 946 #ifdef CONFIG_PGSTE 947 pte_val(pte) &= ~_PAGE_SWR; 948 #endif 949 return pte; 950 } 951 952 static inline pte_t pte_mkyoung(pte_t pte) 953 { 954 return pte; 955 } 956 957 static inline pte_t pte_mkspecial(pte_t pte) 958 { 959 pte_val(pte) |= _PAGE_SPECIAL; 960 return pte; 961 } 962 963 #ifdef CONFIG_HUGETLB_PAGE 964 static inline pte_t pte_mkhuge(pte_t pte) 965 { 966 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO); 967 return pte; 968 } 969 #endif 970 971 /* 972 * Get (and clear) the user dirty bit for a pte. 973 */ 974 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 975 pte_t *ptep) 976 { 977 pgste_t pgste; 978 int dirty = 0; 979 980 if (mm_has_pgste(mm)) { 981 pgste = pgste_get_lock(ptep); 982 pgste = pgste_update_all(ptep, pgste); 983 dirty = !!(pgste_val(pgste) & KVM_UC_BIT); 984 pgste_val(pgste) &= ~KVM_UC_BIT; 985 pgste_set_unlock(ptep, pgste); 986 return dirty; 987 } 988 return dirty; 989 } 990 991 /* 992 * Get (and clear) the user referenced bit for a pte. 993 */ 994 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, 995 pte_t *ptep) 996 { 997 pgste_t pgste; 998 int young = 0; 999 1000 if (mm_has_pgste(mm)) { 1001 pgste = pgste_get_lock(ptep); 1002 pgste = pgste_update_young(ptep, pgste); 1003 young = !!(pgste_val(pgste) & KVM_UR_BIT); 1004 pgste_val(pgste) &= ~KVM_UR_BIT; 1005 pgste_set_unlock(ptep, pgste); 1006 } 1007 return young; 1008 } 1009 1010 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1011 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1012 unsigned long addr, pte_t *ptep) 1013 { 1014 pgste_t pgste; 1015 pte_t pte; 1016 1017 if (mm_has_pgste(vma->vm_mm)) { 1018 pgste = pgste_get_lock(ptep); 1019 pgste = pgste_update_young(ptep, pgste); 1020 pte = *ptep; 1021 *ptep = pte_mkold(pte); 1022 pgste_set_unlock(ptep, pgste); 1023 return pte_young(pte); 1024 } 1025 return 0; 1026 } 1027 1028 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1029 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1030 unsigned long address, pte_t *ptep) 1031 { 1032 /* No need to flush TLB 1033 * On s390 reference bits are in storage key and never in TLB 1034 * With virtualization we handle the reference bit, without we 1035 * we can simply return */ 1036 return ptep_test_and_clear_young(vma, address, ptep); 1037 } 1038 1039 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 1040 { 1041 if (!(pte_val(*ptep) & _PAGE_INVALID)) { 1042 #ifndef CONFIG_64BIT 1043 /* pto must point to the start of the segment table */ 1044 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); 1045 #else 1046 /* ipte in zarch mode can do the math */ 1047 pte_t *pto = ptep; 1048 #endif 1049 asm volatile( 1050 " ipte %2,%3" 1051 : "=m" (*ptep) : "m" (*ptep), 1052 "a" (pto), "a" (address)); 1053 } 1054 } 1055 1056 /* 1057 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1058 * both clear the TLB for the unmapped pte. The reason is that 1059 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1060 * to modify an active pte. The sequence is 1061 * 1) ptep_get_and_clear 1062 * 2) set_pte_at 1063 * 3) flush_tlb_range 1064 * On s390 the tlb needs to get flushed with the modification of the pte 1065 * if the pte is active. The only way how this can be implemented is to 1066 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1067 * is a nop. 1068 */ 1069 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1070 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1071 unsigned long address, pte_t *ptep) 1072 { 1073 pgste_t pgste; 1074 pte_t pte; 1075 1076 mm->context.flush_mm = 1; 1077 if (mm_has_pgste(mm)) { 1078 pgste = pgste_get_lock(ptep); 1079 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1080 } 1081 1082 pte = *ptep; 1083 if (!mm_exclusive(mm)) 1084 __ptep_ipte(address, ptep); 1085 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1086 1087 if (mm_has_pgste(mm)) { 1088 pgste = pgste_update_all(&pte, pgste); 1089 pgste_set_unlock(ptep, pgste); 1090 } 1091 return pte; 1092 } 1093 1094 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1095 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1096 unsigned long address, 1097 pte_t *ptep) 1098 { 1099 pgste_t pgste; 1100 pte_t pte; 1101 1102 mm->context.flush_mm = 1; 1103 if (mm_has_pgste(mm)) { 1104 pgste = pgste_get_lock(ptep); 1105 pgste_ipte_notify(mm, address, ptep, pgste); 1106 } 1107 1108 pte = *ptep; 1109 if (!mm_exclusive(mm)) 1110 __ptep_ipte(address, ptep); 1111 1112 if (mm_has_pgste(mm)) { 1113 pgste = pgste_update_all(&pte, pgste); 1114 pgste_set(ptep, pgste); 1115 } 1116 return pte; 1117 } 1118 1119 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1120 unsigned long address, 1121 pte_t *ptep, pte_t pte) 1122 { 1123 pgste_t pgste; 1124 1125 if (mm_has_pgste(mm)) { 1126 pgste = *(pgste_t *)(ptep + PTRS_PER_PTE); 1127 pgste_set_key(ptep, pgste, pte); 1128 pgste_set_pte(ptep, pte); 1129 pgste_set_unlock(ptep, pgste); 1130 } else 1131 *ptep = pte; 1132 } 1133 1134 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1135 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1136 unsigned long address, pte_t *ptep) 1137 { 1138 pgste_t pgste; 1139 pte_t pte; 1140 1141 if (mm_has_pgste(vma->vm_mm)) { 1142 pgste = pgste_get_lock(ptep); 1143 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1144 } 1145 1146 pte = *ptep; 1147 __ptep_ipte(address, ptep); 1148 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1149 1150 if (mm_has_pgste(vma->vm_mm)) { 1151 pgste = pgste_update_all(&pte, pgste); 1152 pgste_set_unlock(ptep, pgste); 1153 } 1154 return pte; 1155 } 1156 1157 /* 1158 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1159 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1160 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1161 * cannot be accessed while the batched unmap is running. In this case 1162 * full==1 and a simple pte_clear is enough. See tlb.h. 1163 */ 1164 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1165 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1166 unsigned long address, 1167 pte_t *ptep, int full) 1168 { 1169 pgste_t pgste; 1170 pte_t pte; 1171 1172 if (mm_has_pgste(mm)) { 1173 pgste = pgste_get_lock(ptep); 1174 if (!full) 1175 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1176 } 1177 1178 pte = *ptep; 1179 if (!full) 1180 __ptep_ipte(address, ptep); 1181 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1182 1183 if (mm_has_pgste(mm)) { 1184 pgste = pgste_update_all(&pte, pgste); 1185 pgste_set_unlock(ptep, pgste); 1186 } 1187 return pte; 1188 } 1189 1190 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1191 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1192 unsigned long address, pte_t *ptep) 1193 { 1194 pgste_t pgste; 1195 pte_t pte = *ptep; 1196 1197 if (pte_write(pte)) { 1198 mm->context.flush_mm = 1; 1199 if (mm_has_pgste(mm)) { 1200 pgste = pgste_get_lock(ptep); 1201 pgste = pgste_ipte_notify(mm, address, ptep, pgste); 1202 } 1203 1204 if (!mm_exclusive(mm)) 1205 __ptep_ipte(address, ptep); 1206 pte = pte_wrprotect(pte); 1207 1208 if (mm_has_pgste(mm)) { 1209 pgste_set_pte(ptep, pte); 1210 pgste_set_unlock(ptep, pgste); 1211 } else 1212 *ptep = pte; 1213 } 1214 return pte; 1215 } 1216 1217 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1218 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1219 unsigned long address, pte_t *ptep, 1220 pte_t entry, int dirty) 1221 { 1222 pgste_t pgste; 1223 1224 if (pte_same(*ptep, entry)) 1225 return 0; 1226 if (mm_has_pgste(vma->vm_mm)) { 1227 pgste = pgste_get_lock(ptep); 1228 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste); 1229 } 1230 1231 __ptep_ipte(address, ptep); 1232 1233 if (mm_has_pgste(vma->vm_mm)) { 1234 pgste_set_pte(ptep, entry); 1235 pgste_set_unlock(ptep, pgste); 1236 } else 1237 *ptep = entry; 1238 return 1; 1239 } 1240 1241 /* 1242 * Conversion functions: convert a page and protection to a page entry, 1243 * and a page entry and page directory to the page they refer to. 1244 */ 1245 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1246 { 1247 pte_t __pte; 1248 pte_val(__pte) = physpage + pgprot_val(pgprot); 1249 return __pte; 1250 } 1251 1252 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1253 { 1254 unsigned long physpage = page_to_phys(page); 1255 pte_t __pte = mk_pte_phys(physpage, pgprot); 1256 1257 if ((pte_val(__pte) & _PAGE_SWW) && PageDirty(page)) { 1258 pte_val(__pte) |= _PAGE_SWC; 1259 pte_val(__pte) &= ~_PAGE_RO; 1260 } 1261 return __pte; 1262 } 1263 1264 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1265 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1266 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1267 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1268 1269 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1270 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1271 1272 #ifndef CONFIG_64BIT 1273 1274 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1275 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1276 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1277 1278 #define pud_offset(pgd, address) ((pud_t *) pgd) 1279 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1280 1281 #else /* CONFIG_64BIT */ 1282 1283 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1284 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1285 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1286 1287 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1288 { 1289 pud_t *pud = (pud_t *) pgd; 1290 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1291 pud = (pud_t *) pgd_deref(*pgd); 1292 return pud + pud_index(address); 1293 } 1294 1295 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1296 { 1297 pmd_t *pmd = (pmd_t *) pud; 1298 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1299 pmd = (pmd_t *) pud_deref(*pud); 1300 return pmd + pmd_index(address); 1301 } 1302 1303 #endif /* CONFIG_64BIT */ 1304 1305 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1306 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1307 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1308 1309 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1310 1311 /* Find an entry in the lowest level page table.. */ 1312 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1313 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1314 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1315 #define pte_unmap(pte) do { } while (0) 1316 1317 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) 1318 { 1319 unsigned long sto = (unsigned long) pmdp - 1320 pmd_index(address) * sizeof(pmd_t); 1321 1322 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) { 1323 asm volatile( 1324 " .insn rrf,0xb98e0000,%2,%3,0,0" 1325 : "=m" (*pmdp) 1326 : "m" (*pmdp), "a" (sto), 1327 "a" ((address & HPAGE_MASK)) 1328 : "cc" 1329 ); 1330 } 1331 } 1332 1333 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1334 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1335 { 1336 /* 1337 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx) 1338 * Convert to segment table entry format. 1339 */ 1340 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1341 return pgprot_val(SEGMENT_NONE); 1342 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1343 return pgprot_val(SEGMENT_RO); 1344 return pgprot_val(SEGMENT_RW); 1345 } 1346 1347 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1348 { 1349 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1350 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1351 return pmd; 1352 } 1353 1354 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1355 { 1356 pmd_t __pmd; 1357 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1358 return __pmd; 1359 } 1360 1361 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1362 { 1363 /* Do not clobber _HPAGE_TYPE_NONE pages! */ 1364 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV)) 1365 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; 1366 return pmd; 1367 } 1368 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1369 1370 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1371 1372 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1373 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable); 1374 1375 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1376 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm); 1377 1378 static inline int pmd_trans_splitting(pmd_t pmd) 1379 { 1380 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1381 } 1382 1383 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1384 pmd_t *pmdp, pmd_t entry) 1385 { 1386 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1) 1387 pmd_val(entry) |= _SEGMENT_ENTRY_CO; 1388 *pmdp = entry; 1389 } 1390 1391 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1392 { 1393 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1394 return pmd; 1395 } 1396 1397 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1398 { 1399 pmd_val(pmd) |= _SEGMENT_ENTRY_RO; 1400 return pmd; 1401 } 1402 1403 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1404 { 1405 /* No dirty bit in the segment table entry. */ 1406 return pmd; 1407 } 1408 1409 static inline pmd_t pmd_mkold(pmd_t pmd) 1410 { 1411 /* No referenced bit in the segment table entry. */ 1412 return pmd; 1413 } 1414 1415 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1416 { 1417 /* No referenced bit in the segment table entry. */ 1418 return pmd; 1419 } 1420 1421 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1422 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1423 unsigned long address, pmd_t *pmdp) 1424 { 1425 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK; 1426 long tmp, rc; 1427 int counter; 1428 1429 rc = 0; 1430 if (MACHINE_HAS_RRBM) { 1431 counter = PTRS_PER_PTE >> 6; 1432 asm volatile( 1433 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */ 1434 " ogr %1,%0\n" 1435 " la %3,0(%4,%3)\n" 1436 " brct %2,0b\n" 1437 : "=&d" (tmp), "+&d" (rc), "+d" (counter), 1438 "+a" (pmd_addr) 1439 : "a" (64 * 4096UL) : "cc"); 1440 rc = !!rc; 1441 } else { 1442 counter = PTRS_PER_PTE; 1443 asm volatile( 1444 "0: rrbe 0,%2\n" 1445 " la %2,0(%3,%2)\n" 1446 " brc 12,1f\n" 1447 " lhi %0,1\n" 1448 "1: brct %1,0b\n" 1449 : "+d" (rc), "+d" (counter), "+a" (pmd_addr) 1450 : "a" (4096UL) : "cc"); 1451 } 1452 return rc; 1453 } 1454 1455 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1456 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1457 unsigned long address, pmd_t *pmdp) 1458 { 1459 pmd_t pmd = *pmdp; 1460 1461 __pmd_idte(address, pmdp); 1462 pmd_clear(pmdp); 1463 return pmd; 1464 } 1465 1466 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1467 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1468 unsigned long address, pmd_t *pmdp) 1469 { 1470 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1471 } 1472 1473 #define __HAVE_ARCH_PMDP_INVALIDATE 1474 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1475 unsigned long address, pmd_t *pmdp) 1476 { 1477 __pmd_idte(address, pmdp); 1478 } 1479 1480 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1481 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1482 unsigned long address, pmd_t *pmdp) 1483 { 1484 pmd_t pmd = *pmdp; 1485 1486 if (pmd_write(pmd)) { 1487 __pmd_idte(address, pmdp); 1488 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd)); 1489 } 1490 } 1491 1492 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1493 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1494 1495 static inline int pmd_trans_huge(pmd_t pmd) 1496 { 1497 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1498 } 1499 1500 static inline int has_transparent_hugepage(void) 1501 { 1502 return MACHINE_HAS_HPAGE ? 1 : 0; 1503 } 1504 1505 static inline unsigned long pmd_pfn(pmd_t pmd) 1506 { 1507 return pmd_val(pmd) >> PAGE_SHIFT; 1508 } 1509 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1510 1511 /* 1512 * 31 bit swap entry format: 1513 * A page-table entry has some bits we have to treat in a special way. 1514 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1515 * exception will occur instead of a page translation exception. The 1516 * specifiation exception has the bad habit not to store necessary 1517 * information in the lowcore. 1518 * Bit 21 and bit 22 are the page invalid bit and the page protection 1519 * bit. We set both to indicate a swapped page. 1520 * Bit 30 and 31 are used to distinguish the different page types. For 1521 * a swapped page these bits need to be zero. 1522 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1523 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1524 * plus 24 for the offset. 1525 * 0| offset |0110|o|type |00| 1526 * 0 0000000001111111111 2222 2 22222 33 1527 * 0 1234567890123456789 0123 4 56789 01 1528 * 1529 * 64 bit swap entry format: 1530 * A page-table entry has some bits we have to treat in a special way. 1531 * Bits 52 and bit 55 have to be zero, otherwise an specification 1532 * exception will occur instead of a page translation exception. The 1533 * specifiation exception has the bad habit not to store necessary 1534 * information in the lowcore. 1535 * Bit 53 and bit 54 are the page invalid bit and the page protection 1536 * bit. We set both to indicate a swapped page. 1537 * Bit 62 and 63 are used to distinguish the different page types. For 1538 * a swapped page these bits need to be zero. 1539 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1540 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1541 * plus 56 for the offset. 1542 * | offset |0110|o|type |00| 1543 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1544 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1545 */ 1546 #ifndef CONFIG_64BIT 1547 #define __SWP_OFFSET_MASK (~0UL >> 12) 1548 #else 1549 #define __SWP_OFFSET_MASK (~0UL >> 11) 1550 #endif 1551 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1552 { 1553 pte_t pte; 1554 offset &= __SWP_OFFSET_MASK; 1555 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | 1556 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1557 return pte; 1558 } 1559 1560 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1561 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1562 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1563 1564 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1565 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1566 1567 #ifndef CONFIG_64BIT 1568 # define PTE_FILE_MAX_BITS 26 1569 #else /* CONFIG_64BIT */ 1570 # define PTE_FILE_MAX_BITS 59 1571 #endif /* CONFIG_64BIT */ 1572 1573 #define pte_to_pgoff(__pte) \ 1574 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1575 1576 #define pgoff_to_pte(__off) \ 1577 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1578 | _PAGE_TYPE_FILE }) 1579 1580 #endif /* !__ASSEMBLY__ */ 1581 1582 #define kern_addr_valid(addr) (1) 1583 1584 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1585 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1586 extern int s390_enable_sie(void); 1587 1588 /* 1589 * No page table caches to initialise 1590 */ 1591 static inline void pgtable_cache_init(void) { } 1592 static inline void check_pgt_cache(void) { } 1593 1594 #include <asm-generic/pgtable.h> 1595 1596 #endif /* _S390_PAGE_H */ 1597