1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 19 #include <linux/atomic.h> 20 #include <asm/sections.h> 21 #include <asm/ctlreg.h> 22 #include <asm/bug.h> 23 #include <asm/page.h> 24 #include <asm/uv.h> 25 26 extern pgd_t swapper_pg_dir[]; 27 extern pgd_t invalid_pg_dir[]; 28 extern void paging_init(void); 29 extern struct ctlreg s390_invalid_asce; 30 31 enum { 32 PG_DIRECT_MAP_4K = 0, 33 PG_DIRECT_MAP_1M, 34 PG_DIRECT_MAP_2G, 35 PG_DIRECT_MAP_MAX 36 }; 37 38 extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]); 39 40 static inline void update_page_count(int level, long count) 41 { 42 if (IS_ENABLED(CONFIG_PROC_FS)) 43 atomic_long_add(count, &direct_pages_count[level]); 44 } 45 46 /* 47 * The S390 doesn't have any external MMU info: the kernel page 48 * tables contain all the necessary information. 49 */ 50 #define update_mmu_cache(vma, address, ptep) do { } while (0) 51 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 52 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 53 54 /* 55 * ZERO_PAGE is a global shared page that is always zero; used 56 * for zero-mapped memory areas etc.. 57 */ 58 59 extern unsigned long empty_zero_page; 60 extern unsigned long zero_page_mask; 61 62 #define ZERO_PAGE(vaddr) \ 63 (virt_to_page((void *)(empty_zero_page + \ 64 (((unsigned long)(vaddr)) &zero_page_mask)))) 65 #define __HAVE_COLOR_ZERO_PAGE 66 67 /* TODO: s390 cannot support io_remap_pfn_range... */ 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 71 #define pmd_ERROR(e) \ 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) 73 #define pud_ERROR(e) \ 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) 75 #define p4d_ERROR(e) \ 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) 77 #define pgd_ERROR(e) \ 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) 79 80 /* 81 * The vmalloc and module area will always be on the topmost area of the 82 * kernel mapping. 512GB are reserved for vmalloc by default. 83 * At the top of the vmalloc area a 2GB area is reserved where modules 84 * will reside. That makes sure that inter module branches always 85 * happen without trampolines and in addition the placement within a 86 * 2GB frame is branch prediction unit friendly. 87 */ 88 extern unsigned long __bootdata_preserved(VMALLOC_START); 89 extern unsigned long __bootdata_preserved(VMALLOC_END); 90 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 91 extern struct page *__bootdata_preserved(vmemmap); 92 extern unsigned long __bootdata_preserved(vmemmap_size); 93 94 extern unsigned long __bootdata_preserved(MODULES_VADDR); 95 extern unsigned long __bootdata_preserved(MODULES_END); 96 #define MODULES_VADDR MODULES_VADDR 97 #define MODULES_END MODULES_END 98 #define MODULES_LEN (1UL << 31) 99 100 static inline int is_module_addr(void *addr) 101 { 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 103 if (addr < (void *)MODULES_VADDR) 104 return 0; 105 if (addr > (void *)MODULES_END) 106 return 0; 107 return 1; 108 } 109 110 #ifdef CONFIG_KMSAN 111 #define KMSAN_VMALLOC_SIZE (VMALLOC_END - VMALLOC_START) 112 #define KMSAN_VMALLOC_SHADOW_START VMALLOC_END 113 #define KMSAN_VMALLOC_SHADOW_END (KMSAN_VMALLOC_SHADOW_START + KMSAN_VMALLOC_SIZE) 114 #define KMSAN_VMALLOC_ORIGIN_START KMSAN_VMALLOC_SHADOW_END 115 #define KMSAN_VMALLOC_ORIGIN_END (KMSAN_VMALLOC_ORIGIN_START + KMSAN_VMALLOC_SIZE) 116 #define KMSAN_MODULES_SHADOW_START KMSAN_VMALLOC_ORIGIN_END 117 #define KMSAN_MODULES_SHADOW_END (KMSAN_MODULES_SHADOW_START + MODULES_LEN) 118 #define KMSAN_MODULES_ORIGIN_START KMSAN_MODULES_SHADOW_END 119 #define KMSAN_MODULES_ORIGIN_END (KMSAN_MODULES_ORIGIN_START + MODULES_LEN) 120 #endif 121 122 #ifdef CONFIG_RANDOMIZE_BASE 123 #define KASLR_LEN (1UL << 31) 124 #else 125 #define KASLR_LEN 0UL 126 #endif 127 128 /* 129 * A 64 bit pagetable entry of S390 has following format: 130 * | PFRA |0IPC| OS | 131 * 0000000000111111111122222222223333333333444444444455555555556666 132 * 0123456789012345678901234567890123456789012345678901234567890123 133 * 134 * I Page-Invalid Bit: Page is not available for address-translation 135 * P Page-Protection Bit: Store access not possible for page 136 * C Change-bit override: HW is not required to set change bit 137 * 138 * A 64 bit segmenttable entry of S390 has following format: 139 * | P-table origin | TT 140 * 0000000000111111111122222222223333333333444444444455555555556666 141 * 0123456789012345678901234567890123456789012345678901234567890123 142 * 143 * I Segment-Invalid Bit: Segment is not available for address-translation 144 * C Common-Segment Bit: Segment is not private (PoP 3-30) 145 * P Page-Protection Bit: Store access not possible for page 146 * TT Type 00 147 * 148 * A 64 bit region table entry of S390 has following format: 149 * | S-table origin | TF TTTL 150 * 0000000000111111111122222222223333333333444444444455555555556666 151 * 0123456789012345678901234567890123456789012345678901234567890123 152 * 153 * I Segment-Invalid Bit: Segment is not available for address-translation 154 * TT Type 01 155 * TF 156 * TL Table length 157 * 158 * The 64 bit regiontable origin of S390 has following format: 159 * | region table origon | DTTL 160 * 0000000000111111111122222222223333333333444444444455555555556666 161 * 0123456789012345678901234567890123456789012345678901234567890123 162 * 163 * X Space-Switch event: 164 * G Segment-Invalid Bit: 165 * P Private-Space Bit: 166 * S Storage-Alteration: 167 * R Real space 168 * TL Table-Length: 169 * 170 * A storage key has the following format: 171 * | ACC |F|R|C|0| 172 * 0 3 4 5 6 7 173 * ACC: access key 174 * F : fetch protection bit 175 * R : referenced bit 176 * C : changed bit 177 */ 178 179 /* Hardware bits in the page table entry */ 180 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 181 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 182 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 183 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 184 185 /* Software bits in the page table entry */ 186 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 187 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 188 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 189 #define _PAGE_READ 0x010 /* SW pte read bit */ 190 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 191 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 192 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 193 194 #ifdef CONFIG_MEM_SOFT_DIRTY 195 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 196 #else 197 #define _PAGE_SOFT_DIRTY 0x000 198 #endif 199 200 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 201 202 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 203 204 /* Set of bits not changed in pte_modify */ 205 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 206 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 207 208 /* 209 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 210 * HW bit and all SW bits. 211 */ 212 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 213 214 /* 215 * handle_pte_fault uses pte_present and pte_none to find out the pte type 216 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 217 * distinguish present from not-present ptes. It is changed only with the page 218 * table lock held. 219 * 220 * The following table gives the different possible bit combinations for 221 * the pte hardware and software bits in the last 12 bits of a pte 222 * (. unassigned bit, x don't care, t swap type): 223 * 224 * 842100000000 225 * 000084210000 226 * 000000008421 227 * .IR.uswrdy.p 228 * empty .10.00000000 229 * swap .11..ttttt.0 230 * prot-none, clean, old .11.xx0000.1 231 * prot-none, clean, young .11.xx0001.1 232 * prot-none, dirty, old .11.xx0010.1 233 * prot-none, dirty, young .11.xx0011.1 234 * read-only, clean, old .11.xx0100.1 235 * read-only, clean, young .01.xx0101.1 236 * read-only, dirty, old .11.xx0110.1 237 * read-only, dirty, young .01.xx0111.1 238 * read-write, clean, old .11.xx1100.1 239 * read-write, clean, young .01.xx1101.1 240 * read-write, dirty, old .10.xx1110.1 241 * read-write, dirty, young .00.xx1111.1 242 * HW-bits: R read-only, I invalid 243 * SW-bits: p present, y young, d dirty, r read, w write, s special, 244 * u unused, l large 245 * 246 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 247 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 248 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 249 */ 250 251 /* Bits in the segment/region table address-space-control-element */ 252 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 253 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 254 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 255 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 256 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 257 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 258 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 259 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 260 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 261 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 262 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 263 264 /* Bits in the region table entry */ 265 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 266 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 267 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 268 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 269 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 270 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 271 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 272 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 273 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 274 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 275 276 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 277 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 278 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 279 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 280 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH | \ 281 _REGION3_ENTRY_PRESENT) 282 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 283 284 #define _REGION3_ENTRY_HARDWARE_BITS 0xfffffffffffff6ffUL 285 #define _REGION3_ENTRY_HARDWARE_BITS_LARGE 0xffffffff8001073cUL 286 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 287 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 288 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 289 #define _REGION3_ENTRY_COMM 0x0010 /* Common-Region, marks swap entry */ 290 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 291 #define _REGION3_ENTRY_WRITE 0x8000 /* SW region write bit */ 292 #define _REGION3_ENTRY_READ 0x4000 /* SW region read bit */ 293 294 #ifdef CONFIG_MEM_SOFT_DIRTY 295 #define _REGION3_ENTRY_SOFT_DIRTY 0x0002 /* SW region soft dirty bit */ 296 #else 297 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 298 #endif 299 300 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 301 302 /* 303 * SW region present bit. For non-leaf region-third-table entries, bits 62-63 304 * indicate the TABLE LENGTH and both must be set to 1. But such entries 305 * would always be considered as present, so it is safe to use bit 63 as 306 * PRESENT bit for PUD. 307 */ 308 #define _REGION3_ENTRY_PRESENT 0x0001 309 310 /* Bits in the segment table entry */ 311 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe3fUL 312 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe3cUL 313 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff1073cUL 314 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 315 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 316 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 317 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 318 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 319 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 320 321 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PRESENT) 322 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 323 324 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 325 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 326 327 #define _SEGMENT_ENTRY_COMM 0x0010 /* Common-Segment, marks swap entry */ 328 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 329 #define _SEGMENT_ENTRY_WRITE 0x8000 /* SW segment write bit */ 330 #define _SEGMENT_ENTRY_READ 0x4000 /* SW segment read bit */ 331 332 #ifdef CONFIG_MEM_SOFT_DIRTY 333 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0002 /* SW segment soft dirty bit */ 334 #else 335 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 336 #endif 337 338 #define _SEGMENT_ENTRY_PRESENT 0x0001 /* SW segment present bit */ 339 340 /* Common bits in region and segment table entries, for swap entries */ 341 #define _RST_ENTRY_COMM 0x0010 /* Common-Region/Segment, marks swap entry */ 342 #define _RST_ENTRY_INVALID 0x0020 /* invalid region/segment table entry */ 343 344 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 345 #define _PAGE_ENTRIES 256 /* number of page table entries */ 346 347 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 348 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 349 350 #define _REGION1_SHIFT 53 351 #define _REGION2_SHIFT 42 352 #define _REGION3_SHIFT 31 353 #define _SEGMENT_SHIFT 20 354 355 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 356 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 357 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 358 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 359 #define _PAGE_INDEX (0xffUL << PAGE_SHIFT) 360 361 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 362 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 363 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 364 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 365 366 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 367 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 368 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 369 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 370 371 #define PMD_SHIFT _SEGMENT_SHIFT 372 #define PUD_SHIFT _REGION3_SHIFT 373 #define P4D_SHIFT _REGION2_SHIFT 374 #define PGDIR_SHIFT _REGION1_SHIFT 375 376 #define PMD_SIZE _SEGMENT_SIZE 377 #define PUD_SIZE _REGION3_SIZE 378 #define P4D_SIZE _REGION2_SIZE 379 #define PGDIR_SIZE _REGION1_SIZE 380 381 #define PMD_MASK _SEGMENT_MASK 382 #define PUD_MASK _REGION3_MASK 383 #define P4D_MASK _REGION2_MASK 384 #define PGDIR_MASK _REGION1_MASK 385 386 #define PTRS_PER_PTE _PAGE_ENTRIES 387 #define PTRS_PER_PMD _CRST_ENTRIES 388 #define PTRS_PER_PUD _CRST_ENTRIES 389 #define PTRS_PER_P4D _CRST_ENTRIES 390 #define PTRS_PER_PGD _CRST_ENTRIES 391 392 /* 393 * Segment table and region3 table entry encoding 394 * (R = read-only, I = invalid, y = young bit): 395 * dy..R...I...wr 396 * prot-none, clean, old 00..1...1...00 397 * prot-none, clean, young 01..1...1...00 398 * prot-none, dirty, old 10..1...1...00 399 * prot-none, dirty, young 11..1...1...00 400 * read-only, clean, old 00..1...1...01 401 * read-only, clean, young 01..1...0...01 402 * read-only, dirty, old 10..1...1...01 403 * read-only, dirty, young 11..1...0...01 404 * read-write, clean, old 00..1...1...11 405 * read-write, clean, young 01..1...0...11 406 * read-write, dirty, old 10..0...1...11 407 * read-write, dirty, young 11..0...0...11 408 * The segment table origin is used to distinguish empty (origin==0) from 409 * read-write, old segment table entries (origin!=0) 410 * HW-bits: R read-only, I invalid 411 * SW-bits: y young, d dirty, r read, w write 412 */ 413 414 /* Page status table bits for virtualization */ 415 #define PGSTE_ACC_BITS 0xf000000000000000UL 416 #define PGSTE_FP_BIT 0x0800000000000000UL 417 #define PGSTE_PCL_BIT 0x0080000000000000UL 418 #define PGSTE_HR_BIT 0x0040000000000000UL 419 #define PGSTE_HC_BIT 0x0020000000000000UL 420 #define PGSTE_GR_BIT 0x0004000000000000UL 421 #define PGSTE_GC_BIT 0x0002000000000000UL 422 #define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ 423 #define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ 424 #define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */ 425 426 /* Guest Page State used for virtualization */ 427 #define _PGSTE_GPS_ZERO 0x0000000080000000UL 428 #define _PGSTE_GPS_NODAT 0x0000000040000000UL 429 #define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL 430 #define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL 431 #define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL 432 #define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL 433 #define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK 434 435 /* 436 * A user page table pointer has the space-switch-event bit, the 437 * private-space-control bit and the storage-alteration-event-control 438 * bit set. A kernel page table pointer doesn't need them. 439 */ 440 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 441 _ASCE_ALT_EVENT) 442 443 /* 444 * Page protection definitions. 445 */ 446 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 447 #define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 448 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 449 #define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 450 _PAGE_INVALID | _PAGE_PROTECT) 451 #define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 452 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 453 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 454 _PAGE_INVALID | _PAGE_PROTECT) 455 456 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 457 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 458 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 459 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 460 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 461 _PAGE_PROTECT | _PAGE_NOEXEC) 462 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 463 _PAGE_YOUNG | _PAGE_DIRTY) 464 465 /* 466 * On s390 the page table entry has an invalid bit and a read-only bit. 467 * Read permission implies execute permission and write permission 468 * implies read permission. 469 */ 470 /*xwr*/ 471 472 /* 473 * Segment entry (large page) protection definitions. 474 */ 475 #define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_PRESENT | \ 476 _SEGMENT_ENTRY_INVALID | \ 477 _SEGMENT_ENTRY_PROTECT) 478 #define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PRESENT | \ 479 _SEGMENT_ENTRY_PROTECT | \ 480 _SEGMENT_ENTRY_READ | \ 481 _SEGMENT_ENTRY_NOEXEC) 482 #define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PRESENT | \ 483 _SEGMENT_ENTRY_PROTECT | \ 484 _SEGMENT_ENTRY_READ) 485 #define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_PRESENT | \ 486 _SEGMENT_ENTRY_READ | \ 487 _SEGMENT_ENTRY_WRITE | \ 488 _SEGMENT_ENTRY_NOEXEC) 489 #define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_PRESENT | \ 490 _SEGMENT_ENTRY_READ | \ 491 _SEGMENT_ENTRY_WRITE) 492 #define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \ 493 _SEGMENT_ENTRY_LARGE | \ 494 _SEGMENT_ENTRY_READ | \ 495 _SEGMENT_ENTRY_WRITE | \ 496 _SEGMENT_ENTRY_YOUNG | \ 497 _SEGMENT_ENTRY_DIRTY | \ 498 _SEGMENT_ENTRY_NOEXEC) 499 #define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \ 500 _SEGMENT_ENTRY_LARGE | \ 501 _SEGMENT_ENTRY_READ | \ 502 _SEGMENT_ENTRY_YOUNG | \ 503 _SEGMENT_ENTRY_PROTECT | \ 504 _SEGMENT_ENTRY_NOEXEC) 505 #define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \ 506 _SEGMENT_ENTRY_LARGE | \ 507 _SEGMENT_ENTRY_READ | \ 508 _SEGMENT_ENTRY_WRITE | \ 509 _SEGMENT_ENTRY_YOUNG | \ 510 _SEGMENT_ENTRY_DIRTY) 511 512 /* 513 * Region3 entry (large page) protection definitions. 514 */ 515 516 #define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \ 517 _REGION3_ENTRY_PRESENT | \ 518 _REGION3_ENTRY_LARGE | \ 519 _REGION3_ENTRY_READ | \ 520 _REGION3_ENTRY_WRITE | \ 521 _REGION3_ENTRY_YOUNG | \ 522 _REGION3_ENTRY_DIRTY | \ 523 _REGION_ENTRY_NOEXEC) 524 #define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \ 525 _REGION3_ENTRY_PRESENT | \ 526 _REGION3_ENTRY_LARGE | \ 527 _REGION3_ENTRY_READ | \ 528 _REGION3_ENTRY_YOUNG | \ 529 _REGION_ENTRY_PROTECT | \ 530 _REGION_ENTRY_NOEXEC) 531 #define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \ 532 _REGION3_ENTRY_PRESENT | \ 533 _REGION3_ENTRY_LARGE | \ 534 _REGION3_ENTRY_READ | \ 535 _REGION3_ENTRY_WRITE | \ 536 _REGION3_ENTRY_YOUNG | \ 537 _REGION3_ENTRY_DIRTY) 538 539 static inline bool mm_p4d_folded(struct mm_struct *mm) 540 { 541 return mm->context.asce_limit <= _REGION1_SIZE; 542 } 543 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 544 545 static inline bool mm_pud_folded(struct mm_struct *mm) 546 { 547 return mm->context.asce_limit <= _REGION2_SIZE; 548 } 549 #define mm_pud_folded(mm) mm_pud_folded(mm) 550 551 static inline bool mm_pmd_folded(struct mm_struct *mm) 552 { 553 return mm->context.asce_limit <= _REGION3_SIZE; 554 } 555 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 556 557 static inline int mm_has_pgste(struct mm_struct *mm) 558 { 559 #ifdef CONFIG_PGSTE 560 if (unlikely(mm->context.has_pgste)) 561 return 1; 562 #endif 563 return 0; 564 } 565 566 static inline int mm_is_protected(struct mm_struct *mm) 567 { 568 #ifdef CONFIG_PGSTE 569 if (unlikely(atomic_read(&mm->context.protected_count))) 570 return 1; 571 #endif 572 return 0; 573 } 574 575 static inline int mm_alloc_pgste(struct mm_struct *mm) 576 { 577 #ifdef CONFIG_PGSTE 578 if (unlikely(mm->context.alloc_pgste)) 579 return 1; 580 #endif 581 return 0; 582 } 583 584 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 585 { 586 return __pte(pte_val(pte) & ~pgprot_val(prot)); 587 } 588 589 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 590 { 591 return __pte(pte_val(pte) | pgprot_val(prot)); 592 } 593 594 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 595 { 596 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 597 } 598 599 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 600 { 601 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 602 } 603 604 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 605 { 606 return __pud(pud_val(pud) & ~pgprot_val(prot)); 607 } 608 609 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 610 { 611 return __pud(pud_val(pud) | pgprot_val(prot)); 612 } 613 614 /* 615 * As soon as the guest uses storage keys or enables PV, we deduplicate all 616 * mapped shared zeropages and prevent new shared zeropages from getting 617 * mapped. 618 */ 619 #define mm_forbids_zeropage mm_forbids_zeropage 620 static inline int mm_forbids_zeropage(struct mm_struct *mm) 621 { 622 #ifdef CONFIG_PGSTE 623 if (!mm->context.allow_cow_sharing) 624 return 1; 625 #endif 626 return 0; 627 } 628 629 static inline int mm_uses_skeys(struct mm_struct *mm) 630 { 631 #ifdef CONFIG_PGSTE 632 if (mm->context.uses_skeys) 633 return 1; 634 #endif 635 return 0; 636 } 637 638 static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new) 639 { 640 union register_pair r1 = { .even = old, .odd = new, }; 641 unsigned long address = (unsigned long)ptr | 1; 642 643 asm volatile( 644 " csp %[r1],%[address]" 645 : [r1] "+&d" (r1.pair), "+m" (*ptr) 646 : [address] "d" (address) 647 : "cc"); 648 } 649 650 /** 651 * cspg() - Compare and Swap and Purge (CSPG) 652 * @ptr: Pointer to the value to be exchanged 653 * @old: The expected old value 654 * @new: The new value 655 * 656 * Return: True if compare and swap was successful, otherwise false. 657 */ 658 static inline bool cspg(unsigned long *ptr, unsigned long old, unsigned long new) 659 { 660 union register_pair r1 = { .even = old, .odd = new, }; 661 unsigned long address = (unsigned long)ptr | 1; 662 663 asm volatile( 664 " cspg %[r1],%[address]" 665 : [r1] "+&d" (r1.pair), "+m" (*ptr) 666 : [address] "d" (address) 667 : "cc"); 668 return old == r1.even; 669 } 670 671 #define CRDTE_DTT_PAGE 0x00UL 672 #define CRDTE_DTT_SEGMENT 0x10UL 673 #define CRDTE_DTT_REGION3 0x14UL 674 #define CRDTE_DTT_REGION2 0x18UL 675 #define CRDTE_DTT_REGION1 0x1cUL 676 677 /** 678 * crdte() - Compare and Replace DAT Table Entry 679 * @old: The expected old value 680 * @new: The new value 681 * @table: Pointer to the value to be exchanged 682 * @dtt: Table type of the table to be exchanged 683 * @address: The address mapped by the entry to be replaced 684 * @asce: The ASCE of this entry 685 * 686 * Return: True if compare and replace was successful, otherwise false. 687 */ 688 static inline bool crdte(unsigned long old, unsigned long new, 689 unsigned long *table, unsigned long dtt, 690 unsigned long address, unsigned long asce) 691 { 692 union register_pair r1 = { .even = old, .odd = new, }; 693 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 694 695 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 696 : [r1] "+&d" (r1.pair) 697 : [r2] "d" (r2.pair), [asce] "a" (asce) 698 : "memory", "cc"); 699 return old == r1.even; 700 } 701 702 /* 703 * pgd/p4d/pud/pmd/pte query functions 704 */ 705 static inline int pgd_folded(pgd_t pgd) 706 { 707 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 708 } 709 710 static inline int pgd_present(pgd_t pgd) 711 { 712 if (pgd_folded(pgd)) 713 return 1; 714 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 715 } 716 717 static inline int pgd_none(pgd_t pgd) 718 { 719 if (pgd_folded(pgd)) 720 return 0; 721 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 722 } 723 724 static inline int pgd_bad(pgd_t pgd) 725 { 726 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 727 return 0; 728 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 729 } 730 731 static inline unsigned long pgd_pfn(pgd_t pgd) 732 { 733 unsigned long origin_mask; 734 735 origin_mask = _REGION_ENTRY_ORIGIN; 736 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 737 } 738 739 static inline int p4d_folded(p4d_t p4d) 740 { 741 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 742 } 743 744 static inline int p4d_present(p4d_t p4d) 745 { 746 if (p4d_folded(p4d)) 747 return 1; 748 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 749 } 750 751 static inline int p4d_none(p4d_t p4d) 752 { 753 if (p4d_folded(p4d)) 754 return 0; 755 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 756 } 757 758 static inline unsigned long p4d_pfn(p4d_t p4d) 759 { 760 unsigned long origin_mask; 761 762 origin_mask = _REGION_ENTRY_ORIGIN; 763 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 764 } 765 766 static inline int pud_folded(pud_t pud) 767 { 768 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 769 } 770 771 static inline int pud_present(pud_t pud) 772 { 773 if (pud_folded(pud)) 774 return 1; 775 return (pud_val(pud) & _REGION3_ENTRY_PRESENT) != 0; 776 } 777 778 static inline int pud_none(pud_t pud) 779 { 780 if (pud_folded(pud)) 781 return 0; 782 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 783 } 784 785 #define pud_leaf pud_leaf 786 static inline bool pud_leaf(pud_t pud) 787 { 788 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 789 return 0; 790 return (pud_present(pud) && (pud_val(pud) & _REGION3_ENTRY_LARGE) != 0); 791 } 792 793 static inline int pmd_present(pmd_t pmd) 794 { 795 return (pmd_val(pmd) & _SEGMENT_ENTRY_PRESENT) != 0; 796 } 797 798 #define pmd_leaf pmd_leaf 799 static inline bool pmd_leaf(pmd_t pmd) 800 { 801 return (pmd_present(pmd) && (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0); 802 } 803 804 static inline int pmd_bad(pmd_t pmd) 805 { 806 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 807 return 1; 808 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 809 } 810 811 static inline int pud_bad(pud_t pud) 812 { 813 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 814 815 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 816 return 1; 817 if (type < _REGION_ENTRY_TYPE_R3) 818 return 0; 819 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 820 } 821 822 static inline int p4d_bad(p4d_t p4d) 823 { 824 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 825 826 if (type > _REGION_ENTRY_TYPE_R2) 827 return 1; 828 if (type < _REGION_ENTRY_TYPE_R2) 829 return 0; 830 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 831 } 832 833 static inline int pmd_none(pmd_t pmd) 834 { 835 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 836 } 837 838 #define pmd_write pmd_write 839 static inline int pmd_write(pmd_t pmd) 840 { 841 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 842 } 843 844 #define pud_write pud_write 845 static inline int pud_write(pud_t pud) 846 { 847 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 848 } 849 850 #define pmd_dirty pmd_dirty 851 static inline int pmd_dirty(pmd_t pmd) 852 { 853 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 854 } 855 856 #define pmd_young pmd_young 857 static inline int pmd_young(pmd_t pmd) 858 { 859 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 860 } 861 862 static inline int pte_present(pte_t pte) 863 { 864 /* Bit pattern: (pte & 0x001) == 0x001 */ 865 return (pte_val(pte) & _PAGE_PRESENT) != 0; 866 } 867 868 static inline int pte_none(pte_t pte) 869 { 870 /* Bit pattern: pte == 0x400 */ 871 return pte_val(pte) == _PAGE_INVALID; 872 } 873 874 static inline int pte_swap(pte_t pte) 875 { 876 /* Bit pattern: (pte & 0x201) == 0x200 */ 877 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 878 == _PAGE_PROTECT; 879 } 880 881 static inline int pte_special(pte_t pte) 882 { 883 return (pte_val(pte) & _PAGE_SPECIAL); 884 } 885 886 #define __HAVE_ARCH_PTE_SAME 887 static inline int pte_same(pte_t a, pte_t b) 888 { 889 return pte_val(a) == pte_val(b); 890 } 891 892 #ifdef CONFIG_NUMA_BALANCING 893 static inline int pte_protnone(pte_t pte) 894 { 895 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 896 } 897 898 static inline int pmd_protnone(pmd_t pmd) 899 { 900 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 901 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 902 } 903 #endif 904 905 static inline int pte_swp_exclusive(pte_t pte) 906 { 907 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 908 } 909 910 static inline pte_t pte_swp_mkexclusive(pte_t pte) 911 { 912 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 913 } 914 915 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 916 { 917 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 918 } 919 920 static inline int pte_soft_dirty(pte_t pte) 921 { 922 return pte_val(pte) & _PAGE_SOFT_DIRTY; 923 } 924 #define pte_swp_soft_dirty pte_soft_dirty 925 926 static inline pte_t pte_mksoft_dirty(pte_t pte) 927 { 928 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 929 } 930 #define pte_swp_mksoft_dirty pte_mksoft_dirty 931 932 static inline pte_t pte_clear_soft_dirty(pte_t pte) 933 { 934 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 935 } 936 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 937 938 static inline int pmd_soft_dirty(pmd_t pmd) 939 { 940 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 941 } 942 943 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 944 { 945 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 946 } 947 948 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 949 { 950 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 951 } 952 953 /* 954 * query functions pte_write/pte_dirty/pte_young only work if 955 * pte_present() is true. Undefined behaviour if not.. 956 */ 957 static inline int pte_write(pte_t pte) 958 { 959 return (pte_val(pte) & _PAGE_WRITE) != 0; 960 } 961 962 static inline int pte_dirty(pte_t pte) 963 { 964 return (pte_val(pte) & _PAGE_DIRTY) != 0; 965 } 966 967 static inline int pte_young(pte_t pte) 968 { 969 return (pte_val(pte) & _PAGE_YOUNG) != 0; 970 } 971 972 #define __HAVE_ARCH_PTE_UNUSED 973 static inline int pte_unused(pte_t pte) 974 { 975 return pte_val(pte) & _PAGE_UNUSED; 976 } 977 978 /* 979 * Extract the pgprot value from the given pte while at the same time making it 980 * usable for kernel address space mappings where fault driven dirty and 981 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 982 * must not be set. 983 */ 984 #define pte_pgprot pte_pgprot 985 static inline pgprot_t pte_pgprot(pte_t pte) 986 { 987 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 988 989 if (pte_write(pte)) 990 pte_flags |= pgprot_val(PAGE_KERNEL); 991 else 992 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 993 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 994 995 return __pgprot(pte_flags); 996 } 997 998 /* 999 * pgd/pmd/pte modification functions 1000 */ 1001 1002 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1003 { 1004 WRITE_ONCE(*pgdp, pgd); 1005 } 1006 1007 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 1008 { 1009 WRITE_ONCE(*p4dp, p4d); 1010 } 1011 1012 static inline void set_pud(pud_t *pudp, pud_t pud) 1013 { 1014 WRITE_ONCE(*pudp, pud); 1015 } 1016 1017 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 1018 { 1019 WRITE_ONCE(*pmdp, pmd); 1020 } 1021 1022 static inline void set_pte(pte_t *ptep, pte_t pte) 1023 { 1024 WRITE_ONCE(*ptep, pte); 1025 } 1026 1027 static inline void pgd_clear(pgd_t *pgd) 1028 { 1029 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 1030 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 1031 } 1032 1033 static inline void p4d_clear(p4d_t *p4d) 1034 { 1035 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1036 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 1037 } 1038 1039 static inline void pud_clear(pud_t *pud) 1040 { 1041 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1042 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 1043 } 1044 1045 static inline void pmd_clear(pmd_t *pmdp) 1046 { 1047 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1048 } 1049 1050 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 1051 { 1052 set_pte(ptep, __pte(_PAGE_INVALID)); 1053 } 1054 1055 /* 1056 * The following pte modification functions only work if 1057 * pte_present() is true. Undefined behaviour if not.. 1058 */ 1059 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1060 { 1061 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 1062 pte = set_pte_bit(pte, newprot); 1063 /* 1064 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 1065 * has the invalid bit set, clear it again for readable, young pages 1066 */ 1067 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 1068 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1069 /* 1070 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1071 * protection bit set, clear it again for writable, dirty pages 1072 */ 1073 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1074 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1075 return pte; 1076 } 1077 1078 static inline pte_t pte_wrprotect(pte_t pte) 1079 { 1080 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1081 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1082 } 1083 1084 static inline pte_t pte_mkwrite_novma(pte_t pte) 1085 { 1086 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1087 if (pte_val(pte) & _PAGE_DIRTY) 1088 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1089 return pte; 1090 } 1091 1092 static inline pte_t pte_mkclean(pte_t pte) 1093 { 1094 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1095 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1096 } 1097 1098 static inline pte_t pte_mkdirty(pte_t pte) 1099 { 1100 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1101 if (pte_val(pte) & _PAGE_WRITE) 1102 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1103 return pte; 1104 } 1105 1106 static inline pte_t pte_mkold(pte_t pte) 1107 { 1108 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1109 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1110 } 1111 1112 static inline pte_t pte_mkyoung(pte_t pte) 1113 { 1114 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1115 if (pte_val(pte) & _PAGE_READ) 1116 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1117 return pte; 1118 } 1119 1120 static inline pte_t pte_mkspecial(pte_t pte) 1121 { 1122 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1123 } 1124 1125 #ifdef CONFIG_HUGETLB_PAGE 1126 static inline pte_t pte_mkhuge(pte_t pte) 1127 { 1128 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1129 } 1130 #endif 1131 1132 #define IPTE_GLOBAL 0 1133 #define IPTE_LOCAL 1 1134 1135 #define IPTE_NODAT 0x400 1136 #define IPTE_GUEST_ASCE 0x800 1137 1138 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, 1139 unsigned long opt, unsigned long asce, 1140 int local) 1141 { 1142 unsigned long pto; 1143 1144 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1145 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]" 1146 : "+m" (*ptep) 1147 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt), 1148 [asce] "a" (asce), [m4] "i" (local)); 1149 } 1150 1151 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1152 unsigned long opt, unsigned long asce, 1153 int local) 1154 { 1155 unsigned long pto = __pa(ptep); 1156 1157 if (__builtin_constant_p(opt) && opt == 0) { 1158 /* Invalidation + TLB flush for the pte */ 1159 asm volatile( 1160 " ipte %[r1],%[r2],0,%[m4]" 1161 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1162 [m4] "i" (local)); 1163 return; 1164 } 1165 1166 /* Invalidate ptes with options + TLB flush of the ptes */ 1167 opt = opt | (asce & _ASCE_ORIGIN); 1168 asm volatile( 1169 " ipte %[r1],%[r2],%[r3],%[m4]" 1170 : [r2] "+a" (address), [r3] "+a" (opt) 1171 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1172 } 1173 1174 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1175 pte_t *ptep, int local) 1176 { 1177 unsigned long pto = __pa(ptep); 1178 1179 /* Invalidate a range of ptes + TLB flush of the ptes */ 1180 do { 1181 asm volatile( 1182 " ipte %[r1],%[r2],%[r3],%[m4]" 1183 : [r2] "+a" (address), [r3] "+a" (nr) 1184 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1185 } while (nr != 255); 1186 } 1187 1188 /* 1189 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1190 * both clear the TLB for the unmapped pte. The reason is that 1191 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1192 * to modify an active pte. The sequence is 1193 * 1) ptep_get_and_clear 1194 * 2) set_pte_at 1195 * 3) flush_tlb_range 1196 * On s390 the tlb needs to get flushed with the modification of the pte 1197 * if the pte is active. The only way how this can be implemented is to 1198 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1199 * is a nop. 1200 */ 1201 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1202 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1203 1204 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1205 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1206 unsigned long addr, pte_t *ptep) 1207 { 1208 pte_t pte = *ptep; 1209 1210 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1211 return pte_young(pte); 1212 } 1213 1214 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1215 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1216 unsigned long address, pte_t *ptep) 1217 { 1218 return ptep_test_and_clear_young(vma, address, ptep); 1219 } 1220 1221 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1222 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1223 unsigned long addr, pte_t *ptep) 1224 { 1225 pte_t res; 1226 1227 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1228 /* At this point the reference through the mapping is still present */ 1229 if (mm_is_protected(mm) && pte_present(res)) 1230 uv_convert_from_secure_pte(res); 1231 return res; 1232 } 1233 1234 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1235 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1236 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1237 pte_t *, pte_t, pte_t); 1238 1239 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1240 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1241 unsigned long addr, pte_t *ptep) 1242 { 1243 pte_t res; 1244 1245 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1246 /* At this point the reference through the mapping is still present */ 1247 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1248 uv_convert_from_secure_pte(res); 1249 return res; 1250 } 1251 1252 /* 1253 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1254 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1255 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1256 * cannot be accessed while the batched unmap is running. In this case 1257 * full==1 and a simple pte_clear is enough. See tlb.h. 1258 */ 1259 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1260 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1261 unsigned long addr, 1262 pte_t *ptep, int full) 1263 { 1264 pte_t res; 1265 1266 if (full) { 1267 res = *ptep; 1268 set_pte(ptep, __pte(_PAGE_INVALID)); 1269 } else { 1270 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1271 } 1272 /* Nothing to do */ 1273 if (!mm_is_protected(mm) || !pte_present(res)) 1274 return res; 1275 /* 1276 * At this point the reference through the mapping is still present. 1277 * The notifier should have destroyed all protected vCPUs at this 1278 * point, so the destroy should be successful. 1279 */ 1280 if (full && !uv_destroy_pte(res)) 1281 return res; 1282 /* 1283 * If something went wrong and the page could not be destroyed, or 1284 * if this is not a mm teardown, the slower export is used as 1285 * fallback instead. 1286 */ 1287 uv_convert_from_secure_pte(res); 1288 return res; 1289 } 1290 1291 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1292 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1293 unsigned long addr, pte_t *ptep) 1294 { 1295 pte_t pte = *ptep; 1296 1297 if (pte_write(pte)) 1298 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1299 } 1300 1301 /* 1302 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1303 * bits in the comparison. Those might change e.g. because of dirty and young 1304 * tracking. 1305 */ 1306 static inline int pte_allow_rdp(pte_t old, pte_t new) 1307 { 1308 /* 1309 * Only allow changes from RO to RW 1310 */ 1311 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1312 return 0; 1313 1314 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1315 } 1316 1317 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1318 unsigned long address, 1319 pte_t *ptep) 1320 { 1321 /* 1322 * RDP might not have propagated the PTE protection reset to all CPUs, 1323 * so there could be spurious TLB protection faults. 1324 * NOTE: This will also be called when a racing pagetable update on 1325 * another thread already installed the correct PTE. Both cases cannot 1326 * really be distinguished. 1327 * Therefore, only do the local TLB flush when RDP can be used, and the 1328 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1329 * A local RDP can be used to do the flush. 1330 */ 1331 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT)) 1332 __ptep_rdp(address, ptep, 0, 0, 1); 1333 } 1334 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1335 1336 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1337 pte_t new); 1338 1339 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1340 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1341 unsigned long addr, pte_t *ptep, 1342 pte_t entry, int dirty) 1343 { 1344 if (pte_same(*ptep, entry)) 1345 return 0; 1346 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry)) 1347 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1348 else 1349 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1350 return 1; 1351 } 1352 1353 /* 1354 * Additional functions to handle KVM guest page tables 1355 */ 1356 void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr, 1357 pte_t *ptep, pte_t entry); 1358 void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1359 void ptep_notify(struct mm_struct *mm, unsigned long addr, 1360 pte_t *ptep, unsigned long bits); 1361 int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr, 1362 pte_t *ptep, int prot, unsigned long bit); 1363 void ptep_zap_unused(struct mm_struct *mm, unsigned long addr, 1364 pte_t *ptep , int reset); 1365 void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep); 1366 int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr, 1367 pte_t *sptep, pte_t *tptep, pte_t pte); 1368 void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep); 1369 1370 bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address, 1371 pte_t *ptep); 1372 int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1373 unsigned char key, bool nq); 1374 int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1375 unsigned char key, unsigned char *oldkey, 1376 bool nq, bool mr, bool mc); 1377 int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr); 1378 int get_guest_storage_key(struct mm_struct *mm, unsigned long addr, 1379 unsigned char *key); 1380 1381 int set_pgste_bits(struct mm_struct *mm, unsigned long addr, 1382 unsigned long bits, unsigned long value); 1383 int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep); 1384 int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc, 1385 unsigned long *oldpte, unsigned long *oldpgste); 1386 void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr); 1387 void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr); 1388 void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr); 1389 void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr); 1390 1391 #define pgprot_writecombine pgprot_writecombine 1392 pgprot_t pgprot_writecombine(pgprot_t prot); 1393 1394 #define pgprot_writethrough pgprot_writethrough 1395 pgprot_t pgprot_writethrough(pgprot_t prot); 1396 1397 #define PFN_PTE_SHIFT PAGE_SHIFT 1398 1399 /* 1400 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1401 * are within the same folio, PMD and VMA. 1402 */ 1403 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1404 pte_t *ptep, pte_t entry, unsigned int nr) 1405 { 1406 if (pte_present(entry)) 1407 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED)); 1408 if (mm_has_pgste(mm)) { 1409 for (;;) { 1410 ptep_set_pte_at(mm, addr, ptep, entry); 1411 if (--nr == 0) 1412 break; 1413 ptep++; 1414 entry = __pte(pte_val(entry) + PAGE_SIZE); 1415 addr += PAGE_SIZE; 1416 } 1417 } else { 1418 for (;;) { 1419 set_pte(ptep, entry); 1420 if (--nr == 0) 1421 break; 1422 ptep++; 1423 entry = __pte(pte_val(entry) + PAGE_SIZE); 1424 } 1425 } 1426 } 1427 #define set_ptes set_ptes 1428 1429 /* 1430 * Conversion functions: convert a page and protection to a page entry, 1431 * and a page entry and page directory to the page they refer to. 1432 */ 1433 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1434 { 1435 pte_t __pte; 1436 1437 __pte = __pte(physpage | pgprot_val(pgprot)); 1438 if (!MACHINE_HAS_NX) 1439 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC)); 1440 return pte_mkyoung(__pte); 1441 } 1442 1443 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1444 { 1445 unsigned long physpage = page_to_phys(page); 1446 pte_t __pte = mk_pte_phys(physpage, pgprot); 1447 1448 if (pte_write(__pte) && PageDirty(page)) 1449 __pte = pte_mkdirty(__pte); 1450 return __pte; 1451 } 1452 1453 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1454 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1455 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1456 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1457 1458 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1459 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1460 1461 static inline unsigned long pmd_deref(pmd_t pmd) 1462 { 1463 unsigned long origin_mask; 1464 1465 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1466 if (pmd_leaf(pmd)) 1467 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1468 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1469 } 1470 1471 static inline unsigned long pmd_pfn(pmd_t pmd) 1472 { 1473 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1474 } 1475 1476 static inline unsigned long pud_deref(pud_t pud) 1477 { 1478 unsigned long origin_mask; 1479 1480 origin_mask = _REGION_ENTRY_ORIGIN; 1481 if (pud_leaf(pud)) 1482 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1483 return (unsigned long)__va(pud_val(pud) & origin_mask); 1484 } 1485 1486 #define pud_pfn pud_pfn 1487 static inline unsigned long pud_pfn(pud_t pud) 1488 { 1489 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1490 } 1491 1492 /* 1493 * The pgd_offset function *always* adds the index for the top-level 1494 * region/segment table. This is done to get a sequence like the 1495 * following to work: 1496 * pgdp = pgd_offset(current->mm, addr); 1497 * pgd = READ_ONCE(*pgdp); 1498 * p4dp = p4d_offset(&pgd, addr); 1499 * ... 1500 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1501 * only add an index if they dereferenced the pointer. 1502 */ 1503 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1504 { 1505 unsigned long rste; 1506 unsigned int shift; 1507 1508 /* Get the first entry of the top level table */ 1509 rste = pgd_val(*pgd); 1510 /* Pick up the shift from the table type of the first entry */ 1511 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1512 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1513 } 1514 1515 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1516 1517 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1518 { 1519 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1520 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1521 return (p4d_t *) pgdp; 1522 } 1523 #define p4d_offset_lockless p4d_offset_lockless 1524 1525 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1526 { 1527 return p4d_offset_lockless(pgdp, *pgdp, address); 1528 } 1529 1530 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1531 { 1532 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1533 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1534 return (pud_t *) p4dp; 1535 } 1536 #define pud_offset_lockless pud_offset_lockless 1537 1538 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1539 { 1540 return pud_offset_lockless(p4dp, *p4dp, address); 1541 } 1542 #define pud_offset pud_offset 1543 1544 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1545 { 1546 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1547 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1548 return (pmd_t *) pudp; 1549 } 1550 #define pmd_offset_lockless pmd_offset_lockless 1551 1552 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1553 { 1554 return pmd_offset_lockless(pudp, *pudp, address); 1555 } 1556 #define pmd_offset pmd_offset 1557 1558 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1559 { 1560 return (unsigned long) pmd_deref(pmd); 1561 } 1562 1563 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1564 { 1565 return end <= current->mm->context.asce_limit; 1566 } 1567 #define gup_fast_permitted gup_fast_permitted 1568 1569 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1570 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1571 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1572 1573 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1574 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1575 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1576 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1577 1578 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1579 { 1580 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1581 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1582 } 1583 1584 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1585 { 1586 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1587 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1588 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1589 return pmd; 1590 } 1591 1592 static inline pmd_t pmd_mkclean(pmd_t pmd) 1593 { 1594 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1595 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1596 } 1597 1598 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1599 { 1600 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1601 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1602 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1603 return pmd; 1604 } 1605 1606 static inline pud_t pud_wrprotect(pud_t pud) 1607 { 1608 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1609 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1610 } 1611 1612 static inline pud_t pud_mkwrite(pud_t pud) 1613 { 1614 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1615 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1616 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1617 return pud; 1618 } 1619 1620 static inline pud_t pud_mkclean(pud_t pud) 1621 { 1622 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1623 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1624 } 1625 1626 static inline pud_t pud_mkdirty(pud_t pud) 1627 { 1628 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1629 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1630 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1631 return pud; 1632 } 1633 1634 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1635 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1636 { 1637 /* 1638 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1639 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1640 */ 1641 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1642 return pgprot_val(SEGMENT_NONE); 1643 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1644 return pgprot_val(SEGMENT_RO); 1645 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1646 return pgprot_val(SEGMENT_RX); 1647 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1648 return pgprot_val(SEGMENT_RW); 1649 return pgprot_val(SEGMENT_RWX); 1650 } 1651 1652 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1653 { 1654 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1655 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1656 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1657 return pmd; 1658 } 1659 1660 static inline pmd_t pmd_mkold(pmd_t pmd) 1661 { 1662 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1663 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1664 } 1665 1666 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1667 { 1668 unsigned long mask; 1669 1670 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1671 mask |= _SEGMENT_ENTRY_DIRTY; 1672 mask |= _SEGMENT_ENTRY_YOUNG; 1673 mask |= _SEGMENT_ENTRY_LARGE; 1674 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1675 pmd = __pmd(pmd_val(pmd) & mask); 1676 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1677 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1678 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1679 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1680 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1681 return pmd; 1682 } 1683 1684 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1685 { 1686 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1687 } 1688 1689 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1690 1691 static inline void __pmdp_csp(pmd_t *pmdp) 1692 { 1693 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp), 1694 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1695 } 1696 1697 #define IDTE_GLOBAL 0 1698 #define IDTE_LOCAL 1 1699 1700 #define IDTE_PTOA 0x0800 1701 #define IDTE_NODAT 0x1000 1702 #define IDTE_GUEST_ASCE 0x2000 1703 1704 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1705 unsigned long opt, unsigned long asce, 1706 int local) 1707 { 1708 unsigned long sto; 1709 1710 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1711 if (__builtin_constant_p(opt) && opt == 0) { 1712 /* flush without guest asce */ 1713 asm volatile( 1714 " idte %[r1],0,%[r2],%[m4]" 1715 : "+m" (*pmdp) 1716 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1717 [m4] "i" (local) 1718 : "cc" ); 1719 } else { 1720 /* flush with guest asce */ 1721 asm volatile( 1722 " idte %[r1],%[r3],%[r2],%[m4]" 1723 : "+m" (*pmdp) 1724 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1725 [r3] "a" (asce), [m4] "i" (local) 1726 : "cc" ); 1727 } 1728 } 1729 1730 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1731 unsigned long opt, unsigned long asce, 1732 int local) 1733 { 1734 unsigned long r3o; 1735 1736 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1737 r3o |= _ASCE_TYPE_REGION3; 1738 if (__builtin_constant_p(opt) && opt == 0) { 1739 /* flush without guest asce */ 1740 asm volatile( 1741 " idte %[r1],0,%[r2],%[m4]" 1742 : "+m" (*pudp) 1743 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1744 [m4] "i" (local) 1745 : "cc"); 1746 } else { 1747 /* flush with guest asce */ 1748 asm volatile( 1749 " idte %[r1],%[r3],%[r2],%[m4]" 1750 : "+m" (*pudp) 1751 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1752 [r3] "a" (asce), [m4] "i" (local) 1753 : "cc" ); 1754 } 1755 } 1756 1757 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1758 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1759 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1760 1761 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1762 1763 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1764 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1765 pgtable_t pgtable); 1766 1767 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1768 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1769 1770 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1771 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1772 unsigned long addr, pmd_t *pmdp, 1773 pmd_t entry, int dirty) 1774 { 1775 VM_BUG_ON(addr & ~HPAGE_MASK); 1776 1777 entry = pmd_mkyoung(entry); 1778 if (dirty) 1779 entry = pmd_mkdirty(entry); 1780 if (pmd_val(*pmdp) == pmd_val(entry)) 1781 return 0; 1782 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1783 return 1; 1784 } 1785 1786 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1787 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1788 unsigned long addr, pmd_t *pmdp) 1789 { 1790 pmd_t pmd = *pmdp; 1791 1792 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1793 return pmd_young(pmd); 1794 } 1795 1796 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1797 static inline int pmdp_clear_flush_young(struct vm_area_struct *vma, 1798 unsigned long addr, pmd_t *pmdp) 1799 { 1800 VM_BUG_ON(addr & ~HPAGE_MASK); 1801 return pmdp_test_and_clear_young(vma, addr, pmdp); 1802 } 1803 1804 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1805 pmd_t *pmdp, pmd_t entry) 1806 { 1807 if (!MACHINE_HAS_NX) 1808 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC)); 1809 set_pmd(pmdp, entry); 1810 } 1811 1812 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1813 { 1814 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1815 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1816 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1817 } 1818 1819 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1820 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1821 unsigned long addr, pmd_t *pmdp) 1822 { 1823 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1824 } 1825 1826 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1827 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1828 unsigned long addr, 1829 pmd_t *pmdp, int full) 1830 { 1831 if (full) { 1832 pmd_t pmd = *pmdp; 1833 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1834 return pmd; 1835 } 1836 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1837 } 1838 1839 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1840 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1841 unsigned long addr, pmd_t *pmdp) 1842 { 1843 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1844 } 1845 1846 #define __HAVE_ARCH_PMDP_INVALIDATE 1847 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1848 unsigned long addr, pmd_t *pmdp) 1849 { 1850 pmd_t pmd; 1851 1852 VM_WARN_ON_ONCE(!pmd_present(*pmdp)); 1853 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1854 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1855 } 1856 1857 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1858 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1859 unsigned long addr, pmd_t *pmdp) 1860 { 1861 pmd_t pmd = *pmdp; 1862 1863 if (pmd_write(pmd)) 1864 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1865 } 1866 1867 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1868 unsigned long address, 1869 pmd_t *pmdp) 1870 { 1871 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1872 } 1873 #define pmdp_collapse_flush pmdp_collapse_flush 1874 1875 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1876 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1877 1878 static inline int pmd_trans_huge(pmd_t pmd) 1879 { 1880 return pmd_leaf(pmd); 1881 } 1882 1883 #define has_transparent_hugepage has_transparent_hugepage 1884 static inline int has_transparent_hugepage(void) 1885 { 1886 return MACHINE_HAS_EDAT1 ? 1 : 0; 1887 } 1888 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1889 1890 /* 1891 * 64 bit swap entry format: 1892 * A page-table entry has some bits we have to treat in a special way. 1893 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1894 * as invalid. 1895 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1896 * | offset |E11XX|type |S0| 1897 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1898 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1899 * 1900 * Bits 0-51 store the offset. 1901 * Bit 52 (E) is used to remember PG_anon_exclusive. 1902 * Bits 57-61 store the type. 1903 * Bit 62 (S) is used for softdirty tracking. 1904 * Bits 55 and 56 (X) are unused. 1905 */ 1906 1907 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1908 #define __SWP_OFFSET_SHIFT 12 1909 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1910 #define __SWP_TYPE_SHIFT 2 1911 1912 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1913 { 1914 unsigned long pteval; 1915 1916 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1917 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1918 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1919 return __pte(pteval); 1920 } 1921 1922 static inline unsigned long __swp_type(swp_entry_t entry) 1923 { 1924 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1925 } 1926 1927 static inline unsigned long __swp_offset(swp_entry_t entry) 1928 { 1929 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1930 } 1931 1932 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1933 { 1934 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1935 } 1936 1937 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1938 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1939 1940 /* 1941 * 64 bit swap entry format for REGION3 and SEGMENT table entries (RSTE) 1942 * Bits 59 and 63 are used to indicate the swap entry. Bit 58 marks the rste 1943 * as invalid. 1944 * A swap entry is indicated by bit pattern (rste & 0x011) == 0x010 1945 * | offset |Xtype |11TT|S0| 1946 * |0000000000111111111122222222223333333333444444444455|555555|5566|66| 1947 * |0123456789012345678901234567890123456789012345678901|234567|8901|23| 1948 * 1949 * Bits 0-51 store the offset. 1950 * Bits 53-57 store the type. 1951 * Bit 62 (S) is used for softdirty tracking. 1952 * Bits 60-61 (TT) indicate the table type: 0x01 for REGION3 and 0x00 for SEGMENT. 1953 * Bit 52 (X) is unused. 1954 */ 1955 1956 #define __SWP_OFFSET_MASK_RSTE ((1UL << 52) - 1) 1957 #define __SWP_OFFSET_SHIFT_RSTE 12 1958 #define __SWP_TYPE_MASK_RSTE ((1UL << 5) - 1) 1959 #define __SWP_TYPE_SHIFT_RSTE 6 1960 1961 /* 1962 * TT bits set to 0x00 == SEGMENT. For REGION3 entries, caller must add R3 1963 * bits 0x01. See also __set_huge_pte_at(). 1964 */ 1965 static inline unsigned long mk_swap_rste(unsigned long type, unsigned long offset) 1966 { 1967 unsigned long rste; 1968 1969 rste = _RST_ENTRY_INVALID | _RST_ENTRY_COMM; 1970 rste |= (offset & __SWP_OFFSET_MASK_RSTE) << __SWP_OFFSET_SHIFT_RSTE; 1971 rste |= (type & __SWP_TYPE_MASK_RSTE) << __SWP_TYPE_SHIFT_RSTE; 1972 return rste; 1973 } 1974 1975 static inline unsigned long __swp_type_rste(swp_entry_t entry) 1976 { 1977 return (entry.val >> __SWP_TYPE_SHIFT_RSTE) & __SWP_TYPE_MASK_RSTE; 1978 } 1979 1980 static inline unsigned long __swp_offset_rste(swp_entry_t entry) 1981 { 1982 return (entry.val >> __SWP_OFFSET_SHIFT_RSTE) & __SWP_OFFSET_MASK_RSTE; 1983 } 1984 1985 #define __rste_to_swp_entry(rste) ((swp_entry_t) { rste }) 1986 1987 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1988 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1989 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1990 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1991 extern void vmem_unmap_4k_page(unsigned long addr); 1992 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1993 extern int s390_enable_sie(void); 1994 extern int s390_enable_skey(void); 1995 extern void s390_reset_cmma(struct mm_struct *mm); 1996 1997 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1998 #define HAVE_ARCH_UNMAPPED_AREA 1999 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 2000 2001 #define pmd_pgtable(pmd) \ 2002 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 2003 2004 #endif /* _S390_PAGE_H */ 2005