1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * S390 version 4 * Copyright IBM Corp. 1999, 2000 5 * Author(s): Hartmut Penner (hp@de.ibm.com) 6 * Ulrich Weigand (weigand@de.ibm.com) 7 * Martin Schwidefsky (schwidefsky@de.ibm.com) 8 * 9 * Derived from "include/asm-i386/pgtable.h" 10 */ 11 12 #ifndef _ASM_S390_PGTABLE_H 13 #define _ASM_S390_PGTABLE_H 14 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/cpufeature.h> 18 #include <linux/page-flags.h> 19 #include <linux/page_table_check.h> 20 #include <linux/radix-tree.h> 21 #include <linux/atomic.h> 22 #include <linux/mmap_lock.h> 23 #include <asm/ctlreg.h> 24 #include <asm/bug.h> 25 #include <asm/page.h> 26 #include <asm/uv.h> 27 28 extern pgd_t swapper_pg_dir[]; 29 extern pgd_t invalid_pg_dir[]; 30 extern void paging_init(void); 31 extern struct ctlreg s390_invalid_asce; 32 33 enum { 34 PG_DIRECT_MAP_4K = 0, 35 PG_DIRECT_MAP_1M, 36 PG_DIRECT_MAP_2G, 37 PG_DIRECT_MAP_MAX 38 }; 39 40 extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX]; 41 42 static inline void update_page_count(int level, long count) 43 { 44 if (IS_ENABLED(CONFIG_PROC_FS)) 45 atomic_long_add(count, &direct_pages_count[level]); 46 } 47 48 /* 49 * The S390 doesn't have any external MMU info: the kernel page 50 * tables contain all the necessary information. 51 */ 52 #define update_mmu_cache(vma, address, ptep) do { } while (0) 53 #define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0) 54 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 55 56 /* 57 * ZERO_PAGE is a global shared page that is always zero; used 58 * for zero-mapped memory areas etc.. 59 */ 60 61 extern unsigned long empty_zero_page; 62 extern unsigned long zero_page_mask; 63 64 #define ZERO_PAGE(vaddr) \ 65 (virt_to_page((void *)(empty_zero_page + \ 66 (((unsigned long)(vaddr)) &zero_page_mask)))) 67 #define __HAVE_COLOR_ZERO_PAGE 68 69 /* TODO: s390 cannot support io_remap_pfn_range... */ 70 71 /* 72 * The vmalloc and module area will always be on the topmost area of the 73 * kernel mapping. 512GB are reserved for vmalloc by default. 74 * At the top of the vmalloc area a 2GB area is reserved where modules 75 * will reside. That makes sure that inter module branches always 76 * happen without trampolines and in addition the placement within a 77 * 2GB frame is branch prediction unit friendly. 78 */ 79 extern unsigned long VMALLOC_START; 80 extern unsigned long VMALLOC_END; 81 #define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN) 82 extern struct page *vmemmap; 83 extern unsigned long vmemmap_size; 84 85 extern unsigned long MODULES_VADDR; 86 extern unsigned long MODULES_END; 87 #define MODULES_VADDR MODULES_VADDR 88 #define MODULES_END MODULES_END 89 #define MODULES_LEN (1UL << 31) 90 91 static inline int is_module_addr(void *addr) 92 { 93 BUILD_BUG_ON(MODULES_LEN > (1UL << 31)); 94 if (addr < (void *)MODULES_VADDR) 95 return 0; 96 if (addr > (void *)MODULES_END) 97 return 0; 98 return 1; 99 } 100 101 #ifdef CONFIG_KMSAN 102 #define KMSAN_VMALLOC_SIZE (VMALLOC_END - VMALLOC_START) 103 #define KMSAN_VMALLOC_SHADOW_START VMALLOC_END 104 #define KMSAN_VMALLOC_SHADOW_END (KMSAN_VMALLOC_SHADOW_START + KMSAN_VMALLOC_SIZE) 105 #define KMSAN_VMALLOC_ORIGIN_START KMSAN_VMALLOC_SHADOW_END 106 #define KMSAN_VMALLOC_ORIGIN_END (KMSAN_VMALLOC_ORIGIN_START + KMSAN_VMALLOC_SIZE) 107 #define KMSAN_MODULES_SHADOW_START KMSAN_VMALLOC_ORIGIN_END 108 #define KMSAN_MODULES_SHADOW_END (KMSAN_MODULES_SHADOW_START + MODULES_LEN) 109 #define KMSAN_MODULES_ORIGIN_START KMSAN_MODULES_SHADOW_END 110 #define KMSAN_MODULES_ORIGIN_END (KMSAN_MODULES_ORIGIN_START + MODULES_LEN) 111 #endif 112 113 #ifdef CONFIG_RANDOMIZE_BASE 114 #define KASLR_LEN (1UL << 31) 115 #else 116 #define KASLR_LEN 0UL 117 #endif 118 119 void setup_protection_map(void); 120 121 /* 122 * A 64 bit pagetable entry of S390 has following format: 123 * | PFRA |0IPC| OS | 124 * 0000000000111111111122222222223333333333444444444455555555556666 125 * 0123456789012345678901234567890123456789012345678901234567890123 126 * 127 * I Page-Invalid Bit: Page is not available for address-translation 128 * P Page-Protection Bit: Store access not possible for page 129 * C Change-bit override: HW is not required to set change bit 130 * 131 * A 64 bit segmenttable entry of S390 has following format: 132 * | P-table origin | TT 133 * 0000000000111111111122222222223333333333444444444455555555556666 134 * 0123456789012345678901234567890123456789012345678901234567890123 135 * 136 * I Segment-Invalid Bit: Segment is not available for address-translation 137 * C Common-Segment Bit: Segment is not private (PoP 3-30) 138 * P Page-Protection Bit: Store access not possible for page 139 * TT Type 00 140 * 141 * A 64 bit region table entry of S390 has following format: 142 * | S-table origin | TF TTTL 143 * 0000000000111111111122222222223333333333444444444455555555556666 144 * 0123456789012345678901234567890123456789012345678901234567890123 145 * 146 * I Segment-Invalid Bit: Segment is not available for address-translation 147 * TT Type 01 148 * TF 149 * TL Table length 150 * 151 * The 64 bit regiontable origin of S390 has following format: 152 * | region table origon | DTTL 153 * 0000000000111111111122222222223333333333444444444455555555556666 154 * 0123456789012345678901234567890123456789012345678901234567890123 155 * 156 * X Space-Switch event: 157 * G Segment-Invalid Bit: 158 * P Private-Space Bit: 159 * S Storage-Alteration: 160 * R Real space 161 * TL Table-Length: 162 * 163 * A storage key has the following format: 164 * | ACC |F|R|C|0| 165 * 0 3 4 5 6 7 166 * ACC: access key 167 * F : fetch protection bit 168 * R : referenced bit 169 * C : changed bit 170 */ 171 172 /* Hardware bits in the page table entry */ 173 #define _PAGE_NOEXEC 0x100 /* HW no-execute bit */ 174 #define _PAGE_PROTECT 0x200 /* HW read-only bit */ 175 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 176 #define _PAGE_LARGE 0x800 /* Bit to mark a large pte */ 177 178 /* Software bits in the page table entry */ 179 #define _PAGE_PRESENT 0x001 /* SW pte present bit */ 180 #define _PAGE_YOUNG 0x004 /* SW pte young bit */ 181 #define _PAGE_DIRTY 0x008 /* SW pte dirty bit */ 182 #define _PAGE_READ 0x010 /* SW pte read bit */ 183 #define _PAGE_WRITE 0x020 /* SW pte write bit */ 184 #define _PAGE_SPECIAL 0x040 /* SW associated with special page */ 185 #define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */ 186 187 #ifdef CONFIG_MEM_SOFT_DIRTY 188 #define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */ 189 #else 190 #define _PAGE_SOFT_DIRTY 0x000 191 #endif 192 193 #define _PAGE_SW_BITS 0xffUL /* All SW bits */ 194 195 #define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */ 196 197 /* Set of bits not changed in pte_modify */ 198 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \ 199 _PAGE_YOUNG | _PAGE_SOFT_DIRTY) 200 201 /* 202 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT 203 * HW bit and all SW bits. 204 */ 205 #define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS) 206 207 /* 208 * handle_pte_fault uses pte_present and pte_none to find out the pte type 209 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to 210 * distinguish present from not-present ptes. It is changed only with the page 211 * table lock held. 212 * 213 * The following table gives the different possible bit combinations for 214 * the pte hardware and software bits in the last 12 bits of a pte 215 * (. unassigned bit, x don't care, t swap type): 216 * 217 * 842100000000 218 * 000084210000 219 * 000000008421 220 * .IR.uswrdy.p 221 * empty .10.00000000 222 * swap .11..ttttt.0 223 * prot-none, clean, old .11.xx0000.1 224 * prot-none, clean, young .11.xx0001.1 225 * prot-none, dirty, old .11.xx0010.1 226 * prot-none, dirty, young .11.xx0011.1 227 * read-only, clean, old .11.xx0100.1 228 * read-only, clean, young .01.xx0101.1 229 * read-only, dirty, old .11.xx0110.1 230 * read-only, dirty, young .01.xx0111.1 231 * read-write, clean, old .11.xx1100.1 232 * read-write, clean, young .01.xx1101.1 233 * read-write, dirty, old .10.xx1110.1 234 * read-write, dirty, young .00.xx1111.1 235 * HW-bits: R read-only, I invalid 236 * SW-bits: p present, y young, d dirty, r read, w write, s special, 237 * u unused, l large 238 * 239 * pte_none is true for the bit pattern .10.00000000, pte == 0x400 240 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200 241 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001 242 */ 243 244 /* Bits in the segment/region table address-space-control-element */ 245 #define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */ 246 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 247 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 248 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 249 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 250 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 251 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 252 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 253 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 254 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 255 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 256 257 /* Bits in the region table entry */ 258 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 259 #define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */ 260 #define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */ 261 #define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */ 262 #define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */ 263 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */ 264 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 265 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 266 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 267 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 268 269 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 270 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID) 271 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 272 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID) 273 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH | \ 274 _REGION3_ENTRY_PRESENT) 275 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID) 276 277 #define _REGION3_ENTRY_HARDWARE_BITS 0xfffffffffffff6ffUL 278 #define _REGION3_ENTRY_HARDWARE_BITS_LARGE 0xffffffff8001073cUL 279 #define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */ 280 #define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */ 281 #define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */ 282 #define _REGION3_ENTRY_COMM 0x0010 /* Common-Region, marks swap entry */ 283 #define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */ 284 #define _REGION3_ENTRY_WRITE 0x8000 /* SW region write bit */ 285 #define _REGION3_ENTRY_READ 0x4000 /* SW region read bit */ 286 287 #ifdef CONFIG_MEM_SOFT_DIRTY 288 #define _REGION3_ENTRY_SOFT_DIRTY 0x0002 /* SW region soft dirty bit */ 289 #else 290 #define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */ 291 #endif 292 293 #define _REGION_ENTRY_BITS 0xfffffffffffff22fUL 294 295 /* 296 * SW region present bit. For non-leaf region-third-table entries, bits 62-63 297 * indicate the TABLE LENGTH and both must be set to 1. But such entries 298 * would always be considered as present, so it is safe to use bit 63 as 299 * PRESENT bit for PUD. 300 */ 301 #define _REGION3_ENTRY_PRESENT 0x0001 302 303 /* Bits in the segment table entry */ 304 #define _SEGMENT_ENTRY_BITS 0xfffffffffffffe3fUL 305 #define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe3cUL 306 #define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff1073cUL 307 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */ 308 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */ 309 #define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */ 310 #define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */ 311 #define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */ 312 #define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */ 313 314 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PRESENT) 315 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID) 316 317 #define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */ 318 #define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */ 319 320 #define _SEGMENT_ENTRY_COMM 0x0010 /* Common-Segment, marks swap entry */ 321 #define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */ 322 #define _SEGMENT_ENTRY_WRITE 0x8000 /* SW segment write bit */ 323 #define _SEGMENT_ENTRY_READ 0x4000 /* SW segment read bit */ 324 325 #ifdef CONFIG_MEM_SOFT_DIRTY 326 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0002 /* SW segment soft dirty bit */ 327 #else 328 #define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */ 329 #endif 330 331 #define _SEGMENT_ENTRY_PRESENT 0x0001 /* SW segment present bit */ 332 333 /* Common bits in region and segment table entries, for swap entries */ 334 #define _RST_ENTRY_COMM 0x0010 /* Common-Region/Segment, marks swap entry */ 335 #define _RST_ENTRY_INVALID 0x0020 /* invalid region/segment table entry */ 336 337 #define _CRST_ENTRIES 2048 /* number of region/segment table entries */ 338 #define _PAGE_ENTRIES 256 /* number of page table entries */ 339 340 #define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8) 341 #define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8) 342 343 #define _REGION1_SHIFT 53 344 #define _REGION2_SHIFT 42 345 #define _REGION3_SHIFT 31 346 #define _SEGMENT_SHIFT 20 347 348 #define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT) 349 #define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT) 350 #define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT) 351 #define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT) 352 #define _PAGE_INDEX (0xffUL << PAGE_SHIFT) 353 354 #define _REGION1_SIZE (1UL << _REGION1_SHIFT) 355 #define _REGION2_SIZE (1UL << _REGION2_SHIFT) 356 #define _REGION3_SIZE (1UL << _REGION3_SHIFT) 357 #define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT) 358 359 #define _REGION1_MASK (~(_REGION1_SIZE - 1)) 360 #define _REGION2_MASK (~(_REGION2_SIZE - 1)) 361 #define _REGION3_MASK (~(_REGION3_SIZE - 1)) 362 #define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1)) 363 364 #define PMD_SHIFT _SEGMENT_SHIFT 365 #define PUD_SHIFT _REGION3_SHIFT 366 #define P4D_SHIFT _REGION2_SHIFT 367 #define PGDIR_SHIFT _REGION1_SHIFT 368 369 #define PMD_SIZE _SEGMENT_SIZE 370 #define PUD_SIZE _REGION3_SIZE 371 #define P4D_SIZE _REGION2_SIZE 372 #define PGDIR_SIZE _REGION1_SIZE 373 374 #define PMD_MASK _SEGMENT_MASK 375 #define PUD_MASK _REGION3_MASK 376 #define P4D_MASK _REGION2_MASK 377 #define PGDIR_MASK _REGION1_MASK 378 379 #define PTRS_PER_PTE _PAGE_ENTRIES 380 #define PTRS_PER_PMD _CRST_ENTRIES 381 #define PTRS_PER_PUD _CRST_ENTRIES 382 #define PTRS_PER_P4D _CRST_ENTRIES 383 #define PTRS_PER_PGD _CRST_ENTRIES 384 385 /* 386 * Segment table and region3 table entry encoding 387 * (R = read-only, I = invalid, y = young bit): 388 * dy..R...I...wr 389 * prot-none, clean, old 00..1...1...00 390 * prot-none, clean, young 01..1...1...00 391 * prot-none, dirty, old 10..1...1...00 392 * prot-none, dirty, young 11..1...1...00 393 * read-only, clean, old 00..1...1...01 394 * read-only, clean, young 01..1...0...01 395 * read-only, dirty, old 10..1...1...01 396 * read-only, dirty, young 11..1...0...01 397 * read-write, clean, old 00..1...1...11 398 * read-write, clean, young 01..1...0...11 399 * read-write, dirty, old 10..0...1...11 400 * read-write, dirty, young 11..0...0...11 401 * The segment table origin is used to distinguish empty (origin==0) from 402 * read-write, old segment table entries (origin!=0) 403 * HW-bits: R read-only, I invalid 404 * SW-bits: y young, d dirty, r read, w write 405 */ 406 407 /* 408 * A user page table pointer has the space-switch-event bit, the 409 * private-space-control bit and the storage-alteration-event-control 410 * bit set. A kernel page table pointer doesn't need them. 411 */ 412 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 413 _ASCE_ALT_EVENT) 414 415 /* 416 * Page protection definitions. 417 */ 418 #define __PAGE_NONE (_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT) 419 #define __PAGE_RO (_PAGE_PRESENT | _PAGE_READ | \ 420 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 421 #define __PAGE_RX (_PAGE_PRESENT | _PAGE_READ | \ 422 _PAGE_INVALID | _PAGE_PROTECT) 423 #define __PAGE_RW (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 424 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT) 425 #define __PAGE_RWX (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 426 _PAGE_INVALID | _PAGE_PROTECT) 427 #define __PAGE_SHARED (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 428 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 429 #define __PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 430 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC) 431 #define __PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \ 432 _PAGE_PROTECT | _PAGE_NOEXEC) 433 434 extern unsigned long page_noexec_mask; 435 436 #define __pgprot_page_mask(x) __pgprot((x) & page_noexec_mask) 437 438 #define PAGE_NONE __pgprot_page_mask(__PAGE_NONE) 439 #define PAGE_RO __pgprot_page_mask(__PAGE_RO) 440 #define PAGE_RX __pgprot_page_mask(__PAGE_RX) 441 #define PAGE_RW __pgprot_page_mask(__PAGE_RW) 442 #define PAGE_RWX __pgprot_page_mask(__PAGE_RWX) 443 #define PAGE_SHARED __pgprot_page_mask(__PAGE_SHARED) 444 #define PAGE_KERNEL __pgprot_page_mask(__PAGE_KERNEL) 445 #define PAGE_KERNEL_RO __pgprot_page_mask(__PAGE_KERNEL_RO) 446 447 /* 448 * Segment entry (large page) protection definitions. 449 */ 450 #define __SEGMENT_NONE (_SEGMENT_ENTRY_PRESENT | \ 451 _SEGMENT_ENTRY_INVALID | \ 452 _SEGMENT_ENTRY_PROTECT) 453 #define __SEGMENT_RO (_SEGMENT_ENTRY_PRESENT | \ 454 _SEGMENT_ENTRY_PROTECT | \ 455 _SEGMENT_ENTRY_READ | \ 456 _SEGMENT_ENTRY_NOEXEC) 457 #define __SEGMENT_RX (_SEGMENT_ENTRY_PRESENT | \ 458 _SEGMENT_ENTRY_PROTECT | \ 459 _SEGMENT_ENTRY_READ) 460 #define __SEGMENT_RW (_SEGMENT_ENTRY_PRESENT | \ 461 _SEGMENT_ENTRY_READ | \ 462 _SEGMENT_ENTRY_WRITE | \ 463 _SEGMENT_ENTRY_NOEXEC) 464 #define __SEGMENT_RWX (_SEGMENT_ENTRY_PRESENT | \ 465 _SEGMENT_ENTRY_READ | \ 466 _SEGMENT_ENTRY_WRITE) 467 #define __SEGMENT_KERNEL (_SEGMENT_ENTRY | \ 468 _SEGMENT_ENTRY_LARGE | \ 469 _SEGMENT_ENTRY_READ | \ 470 _SEGMENT_ENTRY_WRITE | \ 471 _SEGMENT_ENTRY_YOUNG | \ 472 _SEGMENT_ENTRY_DIRTY | \ 473 _SEGMENT_ENTRY_NOEXEC) 474 #define __SEGMENT_KERNEL_RO (_SEGMENT_ENTRY | \ 475 _SEGMENT_ENTRY_LARGE | \ 476 _SEGMENT_ENTRY_READ | \ 477 _SEGMENT_ENTRY_YOUNG | \ 478 _SEGMENT_ENTRY_PROTECT | \ 479 _SEGMENT_ENTRY_NOEXEC) 480 481 extern unsigned long segment_noexec_mask; 482 483 #define __pgprot_segment_mask(x) __pgprot((x) & segment_noexec_mask) 484 485 #define SEGMENT_NONE __pgprot_segment_mask(__SEGMENT_NONE) 486 #define SEGMENT_RO __pgprot_segment_mask(__SEGMENT_RO) 487 #define SEGMENT_RX __pgprot_segment_mask(__SEGMENT_RX) 488 #define SEGMENT_RW __pgprot_segment_mask(__SEGMENT_RW) 489 #define SEGMENT_RWX __pgprot_segment_mask(__SEGMENT_RWX) 490 #define SEGMENT_KERNEL __pgprot_segment_mask(__SEGMENT_KERNEL) 491 #define SEGMENT_KERNEL_RO __pgprot_segment_mask(__SEGMENT_KERNEL_RO) 492 493 /* 494 * Region3 entry (large page) protection definitions. 495 */ 496 497 #define __REGION3_KERNEL (_REGION_ENTRY_TYPE_R3 | \ 498 _REGION3_ENTRY_PRESENT | \ 499 _REGION3_ENTRY_LARGE | \ 500 _REGION3_ENTRY_READ | \ 501 _REGION3_ENTRY_WRITE | \ 502 _REGION3_ENTRY_YOUNG | \ 503 _REGION3_ENTRY_DIRTY | \ 504 _REGION_ENTRY_NOEXEC) 505 #define __REGION3_KERNEL_RO (_REGION_ENTRY_TYPE_R3 | \ 506 _REGION3_ENTRY_PRESENT | \ 507 _REGION3_ENTRY_LARGE | \ 508 _REGION3_ENTRY_READ | \ 509 _REGION3_ENTRY_YOUNG | \ 510 _REGION_ENTRY_PROTECT | \ 511 _REGION_ENTRY_NOEXEC) 512 513 extern unsigned long region_noexec_mask; 514 515 #define __pgprot_region_mask(x) __pgprot((x) & region_noexec_mask) 516 517 #define REGION3_KERNEL __pgprot_region_mask(__REGION3_KERNEL) 518 #define REGION3_KERNEL_RO __pgprot_region_mask(__REGION3_KERNEL_RO) 519 520 static inline bool mm_p4d_folded(struct mm_struct *mm) 521 { 522 return mm->context.asce_limit <= _REGION1_SIZE; 523 } 524 #define mm_p4d_folded(mm) mm_p4d_folded(mm) 525 526 static inline bool mm_pud_folded(struct mm_struct *mm) 527 { 528 return mm->context.asce_limit <= _REGION2_SIZE; 529 } 530 #define mm_pud_folded(mm) mm_pud_folded(mm) 531 532 static inline bool mm_pmd_folded(struct mm_struct *mm) 533 { 534 return mm->context.asce_limit <= _REGION3_SIZE; 535 } 536 #define mm_pmd_folded(mm) mm_pmd_folded(mm) 537 538 static inline int mm_is_protected(struct mm_struct *mm) 539 { 540 #if IS_ENABLED(CONFIG_KVM) 541 if (unlikely(atomic_read(&mm->context.protected_count))) 542 return 1; 543 #endif 544 return 0; 545 } 546 547 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 548 { 549 return __pte(pte_val(pte) & ~pgprot_val(prot)); 550 } 551 552 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 553 { 554 return __pte(pte_val(pte) | pgprot_val(prot)); 555 } 556 557 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 558 { 559 return __pmd(pmd_val(pmd) & ~pgprot_val(prot)); 560 } 561 562 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 563 { 564 return __pmd(pmd_val(pmd) | pgprot_val(prot)); 565 } 566 567 static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot) 568 { 569 return __pud(pud_val(pud) & ~pgprot_val(prot)); 570 } 571 572 static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) 573 { 574 return __pud(pud_val(pud) | pgprot_val(prot)); 575 } 576 577 /* 578 * As soon as the guest uses storage keys or enables PV, we deduplicate all 579 * mapped shared zeropages and prevent new shared zeropages from getting 580 * mapped. 581 */ 582 #define mm_forbids_zeropage mm_forbids_zeropage 583 static inline int mm_forbids_zeropage(struct mm_struct *mm) 584 { 585 #if IS_ENABLED(CONFIG_KVM) 586 if (!mm->context.allow_cow_sharing) 587 return 1; 588 #endif 589 return 0; 590 } 591 592 /** 593 * cspg() - Compare and Swap and Purge (CSPG) 594 * @ptr: Pointer to the value to be exchanged 595 * @old: The expected old value 596 * @new: The new value 597 * 598 * Return: True if compare and swap was successful, otherwise false. 599 */ 600 static inline bool cspg(unsigned long *ptr, unsigned long old, unsigned long new) 601 { 602 union register_pair r1 = { .even = old, .odd = new, }; 603 unsigned long address = (unsigned long)ptr | 1; 604 605 asm volatile( 606 " cspg %[r1],%[address]" 607 : [r1] "+&d" (r1.pair), "+m" (*ptr) 608 : [address] "d" (address) 609 : "cc"); 610 return old == r1.even; 611 } 612 613 #define CRDTE_DTT_PAGE 0x00UL 614 #define CRDTE_DTT_SEGMENT 0x10UL 615 #define CRDTE_DTT_REGION3 0x14UL 616 #define CRDTE_DTT_REGION2 0x18UL 617 #define CRDTE_DTT_REGION1 0x1cUL 618 619 /** 620 * crdte() - Compare and Replace DAT Table Entry 621 * @old: The expected old value 622 * @new: The new value 623 * @table: Pointer to the value to be exchanged 624 * @dtt: Table type of the table to be exchanged 625 * @address: The address mapped by the entry to be replaced 626 * @asce: The ASCE of this entry 627 * 628 * Return: True if compare and replace was successful, otherwise false. 629 */ 630 static inline bool crdte(unsigned long old, unsigned long new, 631 unsigned long *table, unsigned long dtt, 632 unsigned long address, unsigned long asce) 633 { 634 union register_pair r1 = { .even = old, .odd = new, }; 635 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, }; 636 637 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0" 638 : [r1] "+&d" (r1.pair) 639 : [r2] "d" (r2.pair), [asce] "a" (asce) 640 : "memory", "cc"); 641 return old == r1.even; 642 } 643 644 /* 645 * pgd/p4d/pud/pmd/pte query functions 646 */ 647 static inline int pgd_folded(pgd_t pgd) 648 { 649 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1; 650 } 651 652 static inline int pgd_present(pgd_t pgd) 653 { 654 if (pgd_folded(pgd)) 655 return 1; 656 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 657 } 658 659 static inline int pgd_none(pgd_t pgd) 660 { 661 if (pgd_folded(pgd)) 662 return 0; 663 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL; 664 } 665 666 static inline int pgd_bad(pgd_t pgd) 667 { 668 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1) 669 return 0; 670 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0; 671 } 672 673 static inline unsigned long pgd_pfn(pgd_t pgd) 674 { 675 unsigned long origin_mask; 676 677 origin_mask = _REGION_ENTRY_ORIGIN; 678 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT; 679 } 680 681 static inline int p4d_folded(p4d_t p4d) 682 { 683 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2; 684 } 685 686 static inline int p4d_present(p4d_t p4d) 687 { 688 if (p4d_folded(p4d)) 689 return 1; 690 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL; 691 } 692 693 static inline int p4d_none(p4d_t p4d) 694 { 695 if (p4d_folded(p4d)) 696 return 0; 697 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY; 698 } 699 700 static inline unsigned long p4d_pfn(p4d_t p4d) 701 { 702 unsigned long origin_mask; 703 704 origin_mask = _REGION_ENTRY_ORIGIN; 705 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT; 706 } 707 708 static inline int pud_folded(pud_t pud) 709 { 710 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3; 711 } 712 713 static inline int pud_present(pud_t pud) 714 { 715 if (pud_folded(pud)) 716 return 1; 717 return (pud_val(pud) & _REGION3_ENTRY_PRESENT) != 0; 718 } 719 720 static inline int pud_none(pud_t pud) 721 { 722 if (pud_folded(pud)) 723 return 0; 724 return pud_val(pud) == _REGION3_ENTRY_EMPTY; 725 } 726 727 #define pud_leaf pud_leaf 728 static inline bool pud_leaf(pud_t pud) 729 { 730 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 731 return 0; 732 return (pud_present(pud) && (pud_val(pud) & _REGION3_ENTRY_LARGE) != 0); 733 } 734 735 static inline int pmd_present(pmd_t pmd) 736 { 737 return (pmd_val(pmd) & _SEGMENT_ENTRY_PRESENT) != 0; 738 } 739 740 #define pmd_leaf pmd_leaf 741 static inline bool pmd_leaf(pmd_t pmd) 742 { 743 return (pmd_present(pmd) && (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0); 744 } 745 746 static inline int pmd_bad(pmd_t pmd) 747 { 748 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd)) 749 return 1; 750 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0; 751 } 752 753 static inline int pud_bad(pud_t pud) 754 { 755 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK; 756 757 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud)) 758 return 1; 759 if (type < _REGION_ENTRY_TYPE_R3) 760 return 0; 761 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0; 762 } 763 764 static inline int p4d_bad(p4d_t p4d) 765 { 766 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK; 767 768 if (type > _REGION_ENTRY_TYPE_R2) 769 return 1; 770 if (type < _REGION_ENTRY_TYPE_R2) 771 return 0; 772 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0; 773 } 774 775 static inline int pmd_none(pmd_t pmd) 776 { 777 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY; 778 } 779 780 #define pmd_write pmd_write 781 static inline int pmd_write(pmd_t pmd) 782 { 783 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0; 784 } 785 786 #define pud_write pud_write 787 static inline int pud_write(pud_t pud) 788 { 789 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0; 790 } 791 792 #define pmd_dirty pmd_dirty 793 static inline int pmd_dirty(pmd_t pmd) 794 { 795 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0; 796 } 797 798 #define pmd_young pmd_young 799 static inline int pmd_young(pmd_t pmd) 800 { 801 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0; 802 } 803 804 static inline int pte_present(pte_t pte) 805 { 806 /* Bit pattern: (pte & 0x001) == 0x001 */ 807 return (pte_val(pte) & _PAGE_PRESENT) != 0; 808 } 809 810 static inline int pte_none(pte_t pte) 811 { 812 /* Bit pattern: pte == 0x400 */ 813 return pte_val(pte) == _PAGE_INVALID; 814 } 815 816 static inline int pte_swap(pte_t pte) 817 { 818 /* Bit pattern: (pte & 0x201) == 0x200 */ 819 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT)) 820 == _PAGE_PROTECT; 821 } 822 823 static inline int pte_special(pte_t pte) 824 { 825 return (pte_val(pte) & _PAGE_SPECIAL); 826 } 827 828 #define __HAVE_ARCH_PTE_SAME 829 static inline int pte_same(pte_t a, pte_t b) 830 { 831 return pte_val(a) == pte_val(b); 832 } 833 834 #ifdef CONFIG_ARCH_HAS_PTE_PROTNONE 835 static inline int pte_protnone(pte_t pte) 836 { 837 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ); 838 } 839 840 static inline int pmd_protnone(pmd_t pmd) 841 { 842 /* pmd_leaf(pmd) implies pmd_present(pmd) */ 843 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ); 844 } 845 #endif /* CONFIG_ARCH_HAS_PTE_PROTNONE */ 846 847 static inline bool pte_swp_exclusive(pte_t pte) 848 { 849 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 850 } 851 852 static inline pte_t pte_swp_mkexclusive(pte_t pte) 853 { 854 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 855 } 856 857 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 858 { 859 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE)); 860 } 861 862 static inline int pte_soft_dirty(pte_t pte) 863 { 864 return pte_val(pte) & _PAGE_SOFT_DIRTY; 865 } 866 #define pte_swp_soft_dirty pte_soft_dirty 867 868 static inline pte_t pte_mksoft_dirty(pte_t pte) 869 { 870 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 871 } 872 #define pte_swp_mksoft_dirty pte_mksoft_dirty 873 874 static inline pte_t pte_clear_soft_dirty(pte_t pte) 875 { 876 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY)); 877 } 878 #define pte_swp_clear_soft_dirty pte_clear_soft_dirty 879 880 static inline int pmd_soft_dirty(pmd_t pmd) 881 { 882 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY; 883 } 884 885 static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) 886 { 887 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 888 } 889 890 static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) 891 { 892 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY)); 893 } 894 895 #ifdef CONFIG_ARCH_HAS_PMD_SOFTLEAVES 896 #define pmd_swp_soft_dirty(pmd) pmd_soft_dirty(pmd) 897 #define pmd_swp_mksoft_dirty(pmd) pmd_mksoft_dirty(pmd) 898 #define pmd_swp_clear_soft_dirty(pmd) pmd_clear_soft_dirty(pmd) 899 #endif 900 901 /* 902 * query functions pte_write/pte_dirty/pte_young only work if 903 * pte_present() is true. Undefined behaviour if not.. 904 */ 905 static inline int pte_write(pte_t pte) 906 { 907 return (pte_val(pte) & _PAGE_WRITE) != 0; 908 } 909 910 static inline int pte_dirty(pte_t pte) 911 { 912 return (pte_val(pte) & _PAGE_DIRTY) != 0; 913 } 914 915 static inline int pte_young(pte_t pte) 916 { 917 return (pte_val(pte) & _PAGE_YOUNG) != 0; 918 } 919 920 #define __HAVE_ARCH_PTE_UNUSED 921 static inline int pte_unused(pte_t pte) 922 { 923 return pte_val(pte) & _PAGE_UNUSED; 924 } 925 926 /* 927 * Extract the pgprot value from the given pte while at the same time making it 928 * usable for kernel address space mappings where fault driven dirty and 929 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID 930 * must not be set. 931 */ 932 #define pte_pgprot pte_pgprot 933 static inline pgprot_t pte_pgprot(pte_t pte) 934 { 935 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK; 936 937 if (pte_write(pte)) 938 pte_flags |= pgprot_val(PAGE_KERNEL); 939 else 940 pte_flags |= pgprot_val(PAGE_KERNEL_RO); 941 pte_flags |= pte_val(pte) & mio_wb_bit_mask; 942 943 return __pgprot(pte_flags); 944 } 945 946 /* 947 * pgd/pmd/pte modification functions 948 */ 949 950 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 951 { 952 WRITE_ONCE(*pgdp, pgd); 953 } 954 955 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 956 { 957 WRITE_ONCE(*p4dp, p4d); 958 } 959 960 static inline void set_pud(pud_t *pudp, pud_t pud) 961 { 962 WRITE_ONCE(*pudp, pud); 963 } 964 965 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 966 { 967 WRITE_ONCE(*pmdp, pmd); 968 } 969 970 static inline void set_pte(pte_t *ptep, pte_t pte) 971 { 972 if (pte_present(pte)) 973 pte = clear_pte_bit(pte, __pgprot(_PAGE_UNUSED)); 974 WRITE_ONCE(*ptep, pte); 975 } 976 977 #define ptep_get ptep_get 978 static inline pte_t ptep_get(pte_t *ptep) 979 { 980 return READ_ONCE(*ptep); 981 } 982 983 #define pmdp_get pmdp_get 984 static inline pmd_t pmdp_get(pmd_t *pmdp) 985 { 986 return READ_ONCE(*pmdp); 987 } 988 989 #define pudp_get pudp_get 990 static inline pud_t pudp_get(pud_t *pudp) 991 { 992 return READ_ONCE(*pudp); 993 } 994 995 #define p4dp_get p4dp_get 996 static inline p4d_t p4dp_get(p4d_t *p4dp) 997 { 998 return READ_ONCE(*p4dp); 999 } 1000 1001 #define pgdp_get pgdp_get 1002 static inline pgd_t pgdp_get(pgd_t *pgdp) 1003 { 1004 return READ_ONCE(*pgdp); 1005 } 1006 1007 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 1008 { 1009 set_pte(ptep, __pte(_PAGE_INVALID)); 1010 } 1011 1012 static inline void pmd_clear(pmd_t *pmdp) 1013 { 1014 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1015 } 1016 1017 static inline void pud_clear(pud_t *pud) 1018 { 1019 if ((pud_val(pudp_get(pud)) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1020 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY)); 1021 } 1022 1023 static inline void p4d_clear(p4d_t *p4d) 1024 { 1025 if ((p4d_val(p4dp_get(p4d)) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1026 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY)); 1027 } 1028 1029 static inline void pgd_clear(pgd_t *pgd) 1030 { 1031 if ((pgd_val(pgdp_get(pgd)) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1) 1032 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY)); 1033 } 1034 1035 /* 1036 * The following pte modification functions only work if 1037 * pte_present() is true. Undefined behaviour if not.. 1038 */ 1039 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1040 { 1041 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK)); 1042 pte = set_pte_bit(pte, newprot); 1043 /* 1044 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX 1045 * has the invalid bit set, clear it again for readable, young pages 1046 */ 1047 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ)) 1048 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1049 /* 1050 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page 1051 * protection bit set, clear it again for writable, dirty pages 1052 */ 1053 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE)) 1054 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1055 return pte; 1056 } 1057 1058 static inline pte_t pte_wrprotect(pte_t pte) 1059 { 1060 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1061 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1062 } 1063 1064 static inline pte_t pte_mkwrite_novma(pte_t pte) 1065 { 1066 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE)); 1067 if (pte_val(pte) & _PAGE_DIRTY) 1068 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1069 return pte; 1070 } 1071 1072 static inline pte_t pte_mkclean(pte_t pte) 1073 { 1074 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY)); 1075 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1076 } 1077 1078 static inline pte_t pte_mkdirty(pte_t pte) 1079 { 1080 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 1081 if (pte_val(pte) & _PAGE_WRITE) 1082 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT)); 1083 return pte; 1084 } 1085 1086 static inline pte_t pte_mkold(pte_t pte) 1087 { 1088 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1089 return set_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1090 } 1091 1092 static inline pte_t pte_mkyoung(pte_t pte) 1093 { 1094 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG)); 1095 if (pte_val(pte) & _PAGE_READ) 1096 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID)); 1097 return pte; 1098 } 1099 1100 static inline pte_t pte_mkspecial(pte_t pte) 1101 { 1102 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL)); 1103 } 1104 1105 #ifdef CONFIG_HUGETLB_PAGE 1106 static inline pte_t pte_mkhuge(pte_t pte) 1107 { 1108 return set_pte_bit(pte, __pgprot(_PAGE_LARGE)); 1109 } 1110 #endif 1111 1112 static inline unsigned long sske_frame(unsigned long addr, unsigned char skey) 1113 { 1114 asm volatile("sske %[skey],%[addr],1" 1115 : [addr] "+a" (addr) : [skey] "d" (skey)); 1116 return addr; 1117 } 1118 1119 #define IPTE_GLOBAL 0 1120 #define IPTE_LOCAL 1 1121 1122 #define IPTE_NODAT 0x400 1123 #define IPTE_GUEST_ASCE 0x800 1124 1125 static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, int local) 1126 { 1127 unsigned long pto; 1128 1129 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1); 1130 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%%r0,%[m4]" 1131 : "+m" (*ptep) 1132 : [r1] "a" (pto), [r2] "a" (addr & PAGE_MASK), 1133 [m4] "i" (local)); 1134 } 1135 1136 static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep, 1137 unsigned long opt, unsigned long asce, 1138 int local) 1139 { 1140 unsigned long pto = __pa(ptep); 1141 1142 if (__builtin_constant_p(opt) && opt == 0) { 1143 /* Invalidation + TLB flush for the pte */ 1144 asm volatile( 1145 " ipte %[r1],%[r2],0,%[m4]" 1146 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address), 1147 [m4] "i" (local)); 1148 return; 1149 } 1150 1151 /* Invalidate ptes with options + TLB flush of the ptes */ 1152 opt = opt | (asce & _ASCE_ORIGIN); 1153 asm volatile( 1154 " ipte %[r1],%[r2],%[r3],%[m4]" 1155 : [r2] "+a" (address), [r3] "+a" (opt) 1156 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1157 } 1158 1159 static __always_inline void __ptep_ipte_range(unsigned long address, int nr, 1160 pte_t *ptep, int local) 1161 { 1162 unsigned long pto = __pa(ptep); 1163 1164 /* Invalidate a range of ptes + TLB flush of the ptes */ 1165 do { 1166 asm volatile( 1167 " ipte %[r1],%[r2],%[r3],%[m4]" 1168 : [r2] "+a" (address), [r3] "+a" (nr) 1169 : [r1] "a" (pto), [m4] "i" (local) : "memory"); 1170 } while (nr != 255); 1171 } 1172 1173 /* 1174 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 1175 * both clear the TLB for the unmapped pte. The reason is that 1176 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 1177 * to modify an active pte. The sequence is 1178 * 1) ptep_get_and_clear 1179 * 2) set_pte_at 1180 * 3) flush_tlb_range 1181 * On s390 the tlb needs to get flushed with the modification of the pte 1182 * if the pte is active. The only way how this can be implemented is to 1183 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 1184 * is a nop. 1185 */ 1186 pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t); 1187 pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t); 1188 1189 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1190 static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma, 1191 unsigned long addr, pte_t *ptep) 1192 { 1193 pte_t pte = ptep_get(ptep); 1194 1195 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte)); 1196 return pte_young(pte); 1197 } 1198 1199 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1200 static inline bool ptep_clear_flush_young(struct vm_area_struct *vma, 1201 unsigned long address, pte_t *ptep) 1202 { 1203 return ptep_test_and_clear_young(vma, address, ptep); 1204 } 1205 1206 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1207 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1208 unsigned long addr, pte_t *ptep) 1209 { 1210 pte_t res; 1211 1212 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1213 page_table_check_pte_clear(mm, addr, res); 1214 /* At this point the reference through the mapping is still present */ 1215 if (mm_is_protected(mm) && pte_present(res)) 1216 WARN_ON_ONCE(uv_convert_from_secure_pte(res)); 1217 return res; 1218 } 1219 1220 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1221 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1222 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1223 pte_t *, pte_t, pte_t); 1224 1225 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1226 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1227 unsigned long addr, pte_t *ptep) 1228 { 1229 pte_t res; 1230 1231 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID)); 1232 page_table_check_pte_clear(vma->vm_mm, addr, res); 1233 /* At this point the reference through the mapping is still present */ 1234 if (mm_is_protected(vma->vm_mm) && pte_present(res)) 1235 WARN_ON_ONCE(uv_convert_from_secure_pte(res)); 1236 return res; 1237 } 1238 1239 /* 1240 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1241 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1242 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1243 * cannot be accessed while the batched unmap is running. In this case 1244 * full==1 and a simple pte_clear is enough. See tlb.h. 1245 */ 1246 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1247 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1248 unsigned long addr, 1249 pte_t *ptep, int full) 1250 { 1251 pte_t res; 1252 1253 if (full) { 1254 res = ptep_get(ptep); 1255 set_pte(ptep, __pte(_PAGE_INVALID)); 1256 } else { 1257 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID)); 1258 } 1259 page_table_check_pte_clear(mm, addr, res); 1260 /* At this point the reference through the mapping is still present */ 1261 if (mm_is_protected(mm) && pte_present(res)) { 1262 /* 1263 * The notifier should have destroyed all protected vCPUs at 1264 * this point, so the destroy should be successful. 1265 */ 1266 if (full && !uv_destroy_pte(res)) 1267 return res; 1268 /* 1269 * If something went wrong and the page could not be destroyed, 1270 * or if this is not a mm teardown, the slower export is used 1271 * as fallback instead. If even that fails, print a warning and 1272 * leak the page, to avoid crashing the whole system. 1273 */ 1274 WARN_ON_ONCE(uv_convert_from_secure_pte(res)); 1275 } 1276 return res; 1277 } 1278 1279 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1280 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1281 unsigned long addr, pte_t *ptep) 1282 { 1283 pte_t pte = ptep_get(ptep); 1284 1285 if (pte_write(pte)) 1286 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte)); 1287 } 1288 1289 /* 1290 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE 1291 * bits in the comparison. Those might change e.g. because of dirty and young 1292 * tracking. 1293 */ 1294 static inline int pte_allow_rdp(pte_t old, pte_t new) 1295 { 1296 /* 1297 * Only allow changes from RO to RW 1298 */ 1299 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT) 1300 return 0; 1301 1302 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK); 1303 } 1304 1305 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma, 1306 unsigned long address, 1307 pte_t *ptep) 1308 { 1309 /* 1310 * RDP might not have propagated the PTE protection reset to all CPUs, 1311 * so there could be spurious TLB protection faults. 1312 * NOTE: This will also be called when a racing pagetable update on 1313 * another thread already installed the correct PTE. Both cases cannot 1314 * really be distinguished. 1315 * Therefore, only do the local TLB flush when RDP can be used, and the 1316 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead. 1317 * A local RDP can be used to do the flush. 1318 */ 1319 if (cpu_has_rdp() && !(pte_val(ptep_get(ptep)) & _PAGE_PROTECT)) 1320 __ptep_rdp(address, ptep, 1); 1321 } 1322 #define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault 1323 1324 void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 1325 pte_t new); 1326 1327 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1328 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1329 unsigned long addr, pte_t *ptep, 1330 pte_t entry, int dirty) 1331 { 1332 if (pte_same(*ptep, entry)) 1333 return 0; 1334 if (cpu_has_rdp() && pte_allow_rdp(*ptep, entry)) 1335 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry); 1336 else 1337 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry); 1338 return 1; 1339 } 1340 1341 #define pgprot_writecombine pgprot_writecombine 1342 pgprot_t pgprot_writecombine(pgprot_t prot); 1343 1344 #define PFN_PTE_SHIFT PAGE_SHIFT 1345 1346 /* 1347 * Set multiple PTEs to consecutive pages with a single call. All PTEs 1348 * are within the same folio, PMD and VMA. 1349 */ 1350 static inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1351 pte_t *ptep, pte_t entry, unsigned int nr) 1352 { 1353 page_table_check_ptes_set(mm, addr, ptep, entry, nr); 1354 for (;;) { 1355 set_pte(ptep, entry); 1356 if (--nr == 0) 1357 break; 1358 ptep++; 1359 entry = __pte(pte_val(entry) + PAGE_SIZE); 1360 } 1361 } 1362 #define set_ptes set_ptes 1363 1364 /* 1365 * Conversion functions: convert a page and protection to a page entry, 1366 * and a page entry and page directory to the page they refer to. 1367 */ 1368 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1369 { 1370 pte_t __pte; 1371 1372 __pte = __pte(physpage | pgprot_val(pgprot)); 1373 return pte_mkyoung(__pte); 1374 } 1375 1376 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1377 #define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1)) 1378 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1379 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1380 1381 #define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN)) 1382 #define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN)) 1383 1384 static inline unsigned long pmd_deref(pmd_t pmd) 1385 { 1386 unsigned long origin_mask; 1387 1388 origin_mask = _SEGMENT_ENTRY_ORIGIN; 1389 if (pmd_leaf(pmd)) 1390 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1391 return (unsigned long)__va(pmd_val(pmd) & origin_mask); 1392 } 1393 1394 static inline unsigned long pmd_pfn(pmd_t pmd) 1395 { 1396 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT; 1397 } 1398 1399 static inline unsigned long pud_deref(pud_t pud) 1400 { 1401 unsigned long origin_mask; 1402 1403 origin_mask = _REGION_ENTRY_ORIGIN; 1404 if (pud_leaf(pud)) 1405 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE; 1406 return (unsigned long)__va(pud_val(pud) & origin_mask); 1407 } 1408 1409 #define pud_pfn pud_pfn 1410 static inline unsigned long pud_pfn(pud_t pud) 1411 { 1412 return __pa(pud_deref(pud)) >> PAGE_SHIFT; 1413 } 1414 1415 /* 1416 * The pgd_offset function *always* adds the index for the top-level 1417 * region/segment table. This is done to get a sequence like the 1418 * following to work: 1419 * pgdp = pgd_offset(current->mm, addr); 1420 * pgd = READ_ONCE(*pgdp); 1421 * p4dp = p4d_offset(&pgd, addr); 1422 * ... 1423 * The subsequent p4d_offset, pud_offset and pmd_offset functions 1424 * only add an index if they dereferenced the pointer. 1425 */ 1426 static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address) 1427 { 1428 unsigned long rste; 1429 unsigned int shift; 1430 1431 /* Get the first entry of the top level table */ 1432 rste = pgd_val(*pgd); 1433 /* Pick up the shift from the table type of the first entry */ 1434 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20; 1435 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1)); 1436 } 1437 1438 #define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address) 1439 1440 static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address) 1441 { 1442 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1) 1443 return (p4d_t *) pgd_deref(pgd) + p4d_index(address); 1444 return (p4d_t *) pgdp; 1445 } 1446 #define p4d_offset_lockless p4d_offset_lockless 1447 1448 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address) 1449 { 1450 return p4d_offset_lockless(pgdp, *pgdp, address); 1451 } 1452 1453 static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address) 1454 { 1455 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2) 1456 return (pud_t *) p4d_deref(p4d) + pud_index(address); 1457 return (pud_t *) p4dp; 1458 } 1459 #define pud_offset_lockless pud_offset_lockless 1460 1461 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address) 1462 { 1463 return pud_offset_lockless(p4dp, *p4dp, address); 1464 } 1465 #define pud_offset pud_offset 1466 1467 static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address) 1468 { 1469 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3) 1470 return (pmd_t *) pud_deref(pud) + pmd_index(address); 1471 return (pmd_t *) pudp; 1472 } 1473 #define pmd_offset_lockless pmd_offset_lockless 1474 1475 static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address) 1476 { 1477 return pmd_offset_lockless(pudp, *pudp, address); 1478 } 1479 #define pmd_offset pmd_offset 1480 1481 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 1482 { 1483 return (unsigned long) pmd_deref(pmd); 1484 } 1485 1486 static inline bool gup_fast_permitted(unsigned long start, unsigned long end) 1487 { 1488 return end <= current->mm->context.asce_limit; 1489 } 1490 #define gup_fast_permitted gup_fast_permitted 1491 1492 #define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1493 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1494 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1495 1496 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 1497 #define pud_page(pud) pfn_to_page(pud_pfn(pud)) 1498 #define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d)) 1499 #define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd)) 1500 1501 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1502 { 1503 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1504 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1505 } 1506 1507 static inline pmd_t pmd_mkwrite_novma(pmd_t pmd) 1508 { 1509 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE)); 1510 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) 1511 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1512 return pmd; 1513 } 1514 1515 static inline pmd_t pmd_mkclean(pmd_t pmd) 1516 { 1517 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY)); 1518 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1519 } 1520 1521 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1522 { 1523 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY)); 1524 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) 1525 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1526 return pmd; 1527 } 1528 1529 static inline pud_t pud_wrprotect(pud_t pud) 1530 { 1531 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1532 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1533 } 1534 1535 static inline pud_t pud_mkwrite(pud_t pud) 1536 { 1537 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE)); 1538 if (pud_val(pud) & _REGION3_ENTRY_DIRTY) 1539 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1540 return pud; 1541 } 1542 1543 static inline pud_t pud_mkclean(pud_t pud) 1544 { 1545 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY)); 1546 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1547 } 1548 1549 static inline pud_t pud_mkdirty(pud_t pud) 1550 { 1551 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY)); 1552 if (pud_val(pud) & _REGION3_ENTRY_WRITE) 1553 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT)); 1554 return pud; 1555 } 1556 1557 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) 1558 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1559 { 1560 /* 1561 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX 1562 * (see __Pxxx / __Sxxx). Convert to segment table entry format. 1563 */ 1564 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1565 return pgprot_val(SEGMENT_NONE); 1566 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1567 return pgprot_val(SEGMENT_RO); 1568 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX)) 1569 return pgprot_val(SEGMENT_RX); 1570 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW)) 1571 return pgprot_val(SEGMENT_RW); 1572 return pgprot_val(SEGMENT_RWX); 1573 } 1574 1575 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1576 { 1577 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1578 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ) 1579 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1580 return pmd; 1581 } 1582 1583 static inline pmd_t pmd_mkold(pmd_t pmd) 1584 { 1585 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1586 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1587 } 1588 1589 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1590 { 1591 unsigned long mask; 1592 1593 mask = _SEGMENT_ENTRY_ORIGIN_LARGE; 1594 mask |= _SEGMENT_ENTRY_DIRTY; 1595 mask |= _SEGMENT_ENTRY_YOUNG; 1596 mask |= _SEGMENT_ENTRY_LARGE; 1597 mask |= _SEGMENT_ENTRY_SOFT_DIRTY; 1598 pmd = __pmd(pmd_val(pmd) & mask); 1599 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot))); 1600 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)) 1601 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1602 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG)) 1603 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1604 return pmd; 1605 } 1606 1607 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1608 { 1609 return __pmd(physpage + massage_pgprot_pmd(pgprot)); 1610 } 1611 1612 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */ 1613 1614 static inline void __pmdp_cspg(pmd_t *pmdp) 1615 { 1616 cspg((unsigned long *)pmdp, pmd_val(*pmdp), 1617 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID); 1618 } 1619 1620 #define IDTE_GLOBAL 0 1621 #define IDTE_LOCAL 1 1622 1623 #define IDTE_PTOA 0x0800 1624 #define IDTE_NODAT 0x1000 1625 #define IDTE_GUEST_ASCE 0x2000 1626 1627 static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp, 1628 unsigned long opt, unsigned long asce, 1629 int local) 1630 { 1631 unsigned long sto; 1632 1633 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t); 1634 if (__builtin_constant_p(opt) && opt == 0) { 1635 /* flush without guest asce */ 1636 asm volatile( 1637 " idte %[r1],0,%[r2],%[m4]" 1638 : "+m" (*pmdp) 1639 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)), 1640 [m4] "i" (local) 1641 : "cc" ); 1642 } else { 1643 /* flush with guest asce */ 1644 asm volatile( 1645 " idte %[r1],%[r3],%[r2],%[m4]" 1646 : "+m" (*pmdp) 1647 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt), 1648 [r3] "a" (asce), [m4] "i" (local) 1649 : "cc" ); 1650 } 1651 } 1652 1653 static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp, 1654 unsigned long opt, unsigned long asce, 1655 int local) 1656 { 1657 unsigned long r3o; 1658 1659 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t); 1660 r3o |= _ASCE_TYPE_REGION3; 1661 if (__builtin_constant_p(opt) && opt == 0) { 1662 /* flush without guest asce */ 1663 asm volatile( 1664 " idte %[r1],0,%[r2],%[m4]" 1665 : "+m" (*pudp) 1666 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)), 1667 [m4] "i" (local) 1668 : "cc"); 1669 } else { 1670 /* flush with guest asce */ 1671 asm volatile( 1672 " idte %[r1],%[r3],%[r2],%[m4]" 1673 : "+m" (*pudp) 1674 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt), 1675 [r3] "a" (asce), [m4] "i" (local) 1676 : "cc" ); 1677 } 1678 } 1679 1680 pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1681 pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t); 1682 pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t); 1683 1684 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1685 1686 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1687 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 1688 pgtable_t pgtable); 1689 1690 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1691 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 1692 1693 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1694 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1695 unsigned long addr, pmd_t *pmdp, 1696 pmd_t entry, int dirty) 1697 { 1698 VM_BUG_ON(addr & ~HPAGE_MASK); 1699 1700 entry = pmd_mkyoung(entry); 1701 if (dirty) 1702 entry = pmd_mkdirty(entry); 1703 if (pmd_val(*pmdp) == pmd_val(entry)) 1704 return 0; 1705 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry); 1706 return 1; 1707 } 1708 1709 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1710 static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma, 1711 unsigned long addr, pmd_t *pmdp) 1712 { 1713 pmd_t pmd = *pmdp; 1714 1715 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd)); 1716 return pmd_young(pmd); 1717 } 1718 1719 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 1720 static inline bool pmdp_clear_flush_young(struct vm_area_struct *vma, 1721 unsigned long addr, pmd_t *pmdp) 1722 { 1723 VM_BUG_ON(addr & ~HPAGE_MASK); 1724 return pmdp_test_and_clear_young(vma, addr, pmdp); 1725 } 1726 1727 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1728 pmd_t *pmdp, pmd_t entry) 1729 { 1730 page_table_check_pmd_set(mm, addr, pmdp, entry); 1731 set_pmd(pmdp, entry); 1732 } 1733 1734 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1735 { 1736 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE)); 1737 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG)); 1738 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT)); 1739 } 1740 1741 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1742 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1743 unsigned long addr, pmd_t *pmdp) 1744 { 1745 pmd_t pmd; 1746 1747 pmd = pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1748 page_table_check_pmd_clear(mm, addr, pmd); 1749 return pmd; 1750 } 1751 1752 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1753 static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1754 unsigned long addr, 1755 pmd_t *pmdp, int full) 1756 { 1757 pmd_t pmd; 1758 1759 if (full) { 1760 pmd = *pmdp; 1761 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1762 page_table_check_pmd_clear(vma->vm_mm, addr, pmd); 1763 return pmd; 1764 } 1765 pmd = pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY)); 1766 page_table_check_pmd_clear(vma->vm_mm, addr, pmd); 1767 return pmd; 1768 } 1769 1770 #define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH 1771 static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma, 1772 unsigned long addr, pmd_t *pmdp) 1773 { 1774 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp); 1775 } 1776 1777 #define __HAVE_ARCH_PMDP_INVALIDATE 1778 static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma, 1779 unsigned long addr, pmd_t *pmdp) 1780 { 1781 pmd_t pmd = *pmdp; 1782 1783 VM_WARN_ON_ONCE(!pmd_present(pmd)); 1784 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID)); 1785 #ifdef CONFIG_PAGE_TABLE_CHECK 1786 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_READ)); 1787 #endif 1788 page_table_check_pmd_set(vma->vm_mm, addr, pmdp, pmd); 1789 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd); 1790 return pmd; 1791 } 1792 1793 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1794 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1795 unsigned long addr, pmd_t *pmdp) 1796 { 1797 pmd_t pmd = *pmdp; 1798 1799 if (pmd_write(pmd)) 1800 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd)); 1801 } 1802 1803 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1804 unsigned long address, 1805 pmd_t *pmdp) 1806 { 1807 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp); 1808 } 1809 #define pmdp_collapse_flush pmdp_collapse_flush 1810 1811 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot)) 1812 1813 static inline int pmd_trans_huge(pmd_t pmd) 1814 { 1815 return pmd_leaf(pmd); 1816 } 1817 1818 #define has_transparent_hugepage has_transparent_hugepage 1819 static inline int has_transparent_hugepage(void) 1820 { 1821 return cpu_has_edat1() ? 1 : 0; 1822 } 1823 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1824 1825 #ifdef CONFIG_PAGE_TABLE_CHECK 1826 static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte) 1827 { 1828 VM_BUG_ON(mm == &init_mm); 1829 1830 return pte_present(pte); 1831 } 1832 1833 static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd) 1834 { 1835 VM_BUG_ON(mm == &init_mm); 1836 1837 return pmd_leaf(pmd) && (pmd_val(pmd) & _SEGMENT_ENTRY_READ); 1838 } 1839 1840 static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud) 1841 { 1842 VM_BUG_ON(mm == &init_mm); 1843 1844 return pud_leaf(pud); 1845 } 1846 #endif 1847 1848 /* 1849 * 64 bit swap entry format: 1850 * A page-table entry has some bits we have to treat in a special way. 1851 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte 1852 * as invalid. 1853 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 1854 * | offset |E11XX|type |S0| 1855 * |0000000000111111111122222222223333333333444444444455|55555|55566|66| 1856 * |0123456789012345678901234567890123456789012345678901|23456|78901|23| 1857 * 1858 * Bits 0-51 store the offset. 1859 * Bit 52 (E) is used to remember PG_anon_exclusive. 1860 * Bits 57-61 store the type. 1861 * Bit 62 (S) is used for softdirty tracking. 1862 * Bits 55 and 56 (X) are unused. 1863 */ 1864 1865 #define __SWP_OFFSET_MASK ((1UL << 52) - 1) 1866 #define __SWP_OFFSET_SHIFT 12 1867 #define __SWP_TYPE_MASK ((1UL << 5) - 1) 1868 #define __SWP_TYPE_SHIFT 2 1869 1870 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1871 { 1872 unsigned long pteval; 1873 1874 pteval = _PAGE_INVALID | _PAGE_PROTECT; 1875 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT; 1876 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT; 1877 return __pte(pteval); 1878 } 1879 1880 static inline unsigned long __swp_type(swp_entry_t entry) 1881 { 1882 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK; 1883 } 1884 1885 static inline unsigned long __swp_offset(swp_entry_t entry) 1886 { 1887 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK; 1888 } 1889 1890 static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset) 1891 { 1892 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) }; 1893 } 1894 1895 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1896 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1897 1898 /* 1899 * 64 bit swap entry format for REGION3 and SEGMENT table entries (RSTE) 1900 * Bits 59 and 63 are used to indicate the swap entry. Bit 58 marks the rste 1901 * as invalid. 1902 * A swap entry is indicated by bit pattern (rste & 0x011) == 0x010 1903 * | offset |Xtype |11TT|S0| 1904 * |0000000000111111111122222222223333333333444444444455|555555|5566|66| 1905 * |0123456789012345678901234567890123456789012345678901|234567|8901|23| 1906 * 1907 * Bits 0-51 store the offset. 1908 * Bits 53-57 store the type. 1909 * Bit 62 (S) is used for softdirty tracking. 1910 * Bits 60-61 (TT) indicate the table type: 0x01 for REGION3 and 0x00 for SEGMENT. 1911 * Bit 52 (X) is unused. 1912 */ 1913 1914 #define __SWP_OFFSET_MASK_RSTE ((1UL << 52) - 1) 1915 #define __SWP_OFFSET_SHIFT_RSTE 12 1916 #define __SWP_TYPE_MASK_RSTE ((1UL << 5) - 1) 1917 #define __SWP_TYPE_SHIFT_RSTE 6 1918 1919 /* 1920 * TT bits set to 0x00 == SEGMENT. For REGION3 entries, caller must add R3 1921 * bits 0x01. See also __set_huge_pte_at(). 1922 */ 1923 static inline unsigned long mk_swap_rste(unsigned long type, unsigned long offset) 1924 { 1925 unsigned long rste; 1926 1927 rste = _RST_ENTRY_INVALID | _RST_ENTRY_COMM; 1928 rste |= (offset & __SWP_OFFSET_MASK_RSTE) << __SWP_OFFSET_SHIFT_RSTE; 1929 rste |= (type & __SWP_TYPE_MASK_RSTE) << __SWP_TYPE_SHIFT_RSTE; 1930 return rste; 1931 } 1932 1933 static inline unsigned long __swp_type_rste(swp_entry_t entry) 1934 { 1935 return (entry.val >> __SWP_TYPE_SHIFT_RSTE) & __SWP_TYPE_MASK_RSTE; 1936 } 1937 1938 static inline unsigned long __swp_offset_rste(swp_entry_t entry) 1939 { 1940 return (entry.val >> __SWP_OFFSET_SHIFT_RSTE) & __SWP_OFFSET_MASK_RSTE; 1941 } 1942 1943 #define __rste_to_swp_entry(rste) ((swp_entry_t) { rste }) 1944 1945 /* 1946 * s390 has different layout for PTE and region / segment table entries (RSTE). 1947 * This is also true for swap entries, and their swap type and offset encoding. 1948 * For hugetlbfs PTE_MARKER support, s390 has internal __swp_type_rste() and 1949 * __swp_offset_rste() helpers to correctly handle RSTE swap entries. 1950 * 1951 * But common swap code does not know about this difference, and only uses 1952 * __swp_type(), __swp_offset() and __swp_entry() helpers for conversion between 1953 * arch-dependent and arch-independent representation of swp_entry_t for all 1954 * pagetable levels. On s390, those helpers only work for PTE swap entries. 1955 * 1956 * Therefore, implement __pmd_to_swp_entry() to build a fake PTE swap entry 1957 * and return the arch-dependent representation of that. Correspondingly, 1958 * implement __swp_entry_to_pmd() to convert that into a proper PMD swap 1959 * entry again. With this, the arch-dependent swp_entry_t representation will 1960 * always look like a PTE swap entry in common code. 1961 * 1962 * This is somewhat similar to fake PTEs in hugetlbfs code for s390, but only 1963 * requires conversion of the swap type and offset, and not all the possible 1964 * PTE bits. 1965 */ 1966 static inline swp_entry_t __pmd_to_swp_entry(pmd_t pmd) 1967 { 1968 swp_entry_t arch_entry; 1969 pte_t pte; 1970 1971 arch_entry = __rste_to_swp_entry(pmd_val(pmd)); 1972 pte = mk_swap_pte(__swp_type_rste(arch_entry), __swp_offset_rste(arch_entry)); 1973 return __pte_to_swp_entry(pte); 1974 } 1975 1976 static inline pmd_t __swp_entry_to_pmd(swp_entry_t arch_entry) 1977 { 1978 pmd_t pmd; 1979 1980 pmd = __pmd(mk_swap_rste(__swp_type(arch_entry), __swp_offset(arch_entry))); 1981 return pmd; 1982 } 1983 1984 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1985 extern void vmem_remove_mapping(unsigned long start, unsigned long size); 1986 extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc); 1987 extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot); 1988 extern void vmem_unmap_4k_page(unsigned long addr); 1989 extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc); 1990 1991 /* s390 has a private copy of get unmapped area to deal with cache synonyms */ 1992 #define HAVE_ARCH_UNMAPPED_AREA 1993 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 1994 1995 #define pmd_pgtable(pmd) \ 1996 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)) 1997 1998 #endif /* _S390_PAGE_H */ 1999