1 /* 2 * S390 version 3 * Copyright IBM Corp. 1999, 2000 4 * Author(s): Hartmut Penner (hp@de.ibm.com) 5 * Ulrich Weigand (weigand@de.ibm.com) 6 * Martin Schwidefsky (schwidefsky@de.ibm.com) 7 * 8 * Derived from "include/asm-i386/pgtable.h" 9 */ 10 11 #ifndef _ASM_S390_PGTABLE_H 12 #define _ASM_S390_PGTABLE_H 13 14 /* 15 * The Linux memory management assumes a three-level page table setup. For 16 * s390 31 bit we "fold" the mid level into the top-level page table, so 17 * that we physically have the same two-level page table as the s390 mmu 18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels 19 * the hardware provides (region first and region second tables are not 20 * used). 21 * 22 * The "pgd_xxx()" functions are trivial for a folded two-level 23 * setup: the pgd is never bad, and a pmd always exists (as it's folded 24 * into the pgd entry) 25 * 26 * This file contains the functions and defines necessary to modify and use 27 * the S390 page table tree. 28 */ 29 #ifndef __ASSEMBLY__ 30 #include <linux/sched.h> 31 #include <linux/mm_types.h> 32 #include <asm/bug.h> 33 #include <asm/page.h> 34 35 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); 36 extern void paging_init(void); 37 extern void vmem_map_init(void); 38 39 /* 40 * The S390 doesn't have any external MMU info: the kernel page 41 * tables contain all the necessary information. 42 */ 43 #define update_mmu_cache(vma, address, ptep) do { } while (0) 44 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0) 45 46 /* 47 * ZERO_PAGE is a global shared page that is always zero; used 48 * for zero-mapped memory areas etc.. 49 */ 50 51 extern unsigned long empty_zero_page; 52 extern unsigned long zero_page_mask; 53 54 #define ZERO_PAGE(vaddr) \ 55 (virt_to_page((void *)(empty_zero_page + \ 56 (((unsigned long)(vaddr)) &zero_page_mask)))) 57 #define __HAVE_COLOR_ZERO_PAGE 58 59 #endif /* !__ASSEMBLY__ */ 60 61 /* 62 * PMD_SHIFT determines the size of the area a second-level page 63 * table can map 64 * PGDIR_SHIFT determines what a third-level page table entry can map 65 */ 66 #ifndef CONFIG_64BIT 67 # define PMD_SHIFT 20 68 # define PUD_SHIFT 20 69 # define PGDIR_SHIFT 20 70 #else /* CONFIG_64BIT */ 71 # define PMD_SHIFT 20 72 # define PUD_SHIFT 31 73 # define PGDIR_SHIFT 42 74 #endif /* CONFIG_64BIT */ 75 76 #define PMD_SIZE (1UL << PMD_SHIFT) 77 #define PMD_MASK (~(PMD_SIZE-1)) 78 #define PUD_SIZE (1UL << PUD_SHIFT) 79 #define PUD_MASK (~(PUD_SIZE-1)) 80 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 81 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 82 83 /* 84 * entries per page directory level: the S390 is two-level, so 85 * we don't really have any PMD directory physically. 86 * for S390 segment-table entries are combined to one PGD 87 * that leads to 1024 pte per pgd 88 */ 89 #define PTRS_PER_PTE 256 90 #ifndef CONFIG_64BIT 91 #define PTRS_PER_PMD 1 92 #define PTRS_PER_PUD 1 93 #else /* CONFIG_64BIT */ 94 #define PTRS_PER_PMD 2048 95 #define PTRS_PER_PUD 2048 96 #endif /* CONFIG_64BIT */ 97 #define PTRS_PER_PGD 2048 98 99 #define FIRST_USER_ADDRESS 0 100 101 #define pte_ERROR(e) \ 102 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) 103 #define pmd_ERROR(e) \ 104 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) 105 #define pud_ERROR(e) \ 106 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) 107 #define pgd_ERROR(e) \ 108 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) 109 110 #ifndef __ASSEMBLY__ 111 /* 112 * The vmalloc and module area will always be on the topmost area of the kernel 113 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules. 114 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where 115 * modules will reside. That makes sure that inter module branches always 116 * happen without trampolines and in addition the placement within a 2GB frame 117 * is branch prediction unit friendly. 118 */ 119 extern unsigned long VMALLOC_START; 120 extern unsigned long VMALLOC_END; 121 extern struct page *vmemmap; 122 123 #define VMEM_MAX_PHYS ((unsigned long) vmemmap) 124 125 #ifdef CONFIG_64BIT 126 extern unsigned long MODULES_VADDR; 127 extern unsigned long MODULES_END; 128 #define MODULES_VADDR MODULES_VADDR 129 #define MODULES_END MODULES_END 130 #define MODULES_LEN (1UL << 31) 131 #endif 132 133 /* 134 * A 31 bit pagetable entry of S390 has following format: 135 * | PFRA | | OS | 136 * 0 0IP0 137 * 00000000001111111111222222222233 138 * 01234567890123456789012345678901 139 * 140 * I Page-Invalid Bit: Page is not available for address-translation 141 * P Page-Protection Bit: Store access not possible for page 142 * 143 * A 31 bit segmenttable entry of S390 has following format: 144 * | P-table origin | |PTL 145 * 0 IC 146 * 00000000001111111111222222222233 147 * 01234567890123456789012345678901 148 * 149 * I Segment-Invalid Bit: Segment is not available for address-translation 150 * C Common-Segment Bit: Segment is not private (PoP 3-30) 151 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) 152 * 153 * The 31 bit segmenttable origin of S390 has following format: 154 * 155 * |S-table origin | | STL | 156 * X **GPS 157 * 00000000001111111111222222222233 158 * 01234567890123456789012345678901 159 * 160 * X Space-Switch event: 161 * G Segment-Invalid Bit: * 162 * P Private-Space Bit: Segment is not private (PoP 3-30) 163 * S Storage-Alteration: 164 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) 165 * 166 * A 64 bit pagetable entry of S390 has following format: 167 * | PFRA |0IPC| OS | 168 * 0000000000111111111122222222223333333333444444444455555555556666 169 * 0123456789012345678901234567890123456789012345678901234567890123 170 * 171 * I Page-Invalid Bit: Page is not available for address-translation 172 * P Page-Protection Bit: Store access not possible for page 173 * C Change-bit override: HW is not required to set change bit 174 * 175 * A 64 bit segmenttable entry of S390 has following format: 176 * | P-table origin | TT 177 * 0000000000111111111122222222223333333333444444444455555555556666 178 * 0123456789012345678901234567890123456789012345678901234567890123 179 * 180 * I Segment-Invalid Bit: Segment is not available for address-translation 181 * C Common-Segment Bit: Segment is not private (PoP 3-30) 182 * P Page-Protection Bit: Store access not possible for page 183 * TT Type 00 184 * 185 * A 64 bit region table entry of S390 has following format: 186 * | S-table origin | TF TTTL 187 * 0000000000111111111122222222223333333333444444444455555555556666 188 * 0123456789012345678901234567890123456789012345678901234567890123 189 * 190 * I Segment-Invalid Bit: Segment is not available for address-translation 191 * TT Type 01 192 * TF 193 * TL Table length 194 * 195 * The 64 bit regiontable origin of S390 has following format: 196 * | region table origon | DTTL 197 * 0000000000111111111122222222223333333333444444444455555555556666 198 * 0123456789012345678901234567890123456789012345678901234567890123 199 * 200 * X Space-Switch event: 201 * G Segment-Invalid Bit: 202 * P Private-Space Bit: 203 * S Storage-Alteration: 204 * R Real space 205 * TL Table-Length: 206 * 207 * A storage key has the following format: 208 * | ACC |F|R|C|0| 209 * 0 3 4 5 6 7 210 * ACC: access key 211 * F : fetch protection bit 212 * R : referenced bit 213 * C : changed bit 214 */ 215 216 /* Hardware bits in the page table entry */ 217 #define _PAGE_CO 0x100 /* HW Change-bit override */ 218 #define _PAGE_RO 0x200 /* HW read-only bit */ 219 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 220 221 /* Software bits in the page table entry */ 222 #define _PAGE_SWT 0x001 /* SW pte type bit t */ 223 #define _PAGE_SWX 0x002 /* SW pte type bit x */ 224 #define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */ 225 #define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */ 226 #define _PAGE_SPECIAL 0x010 /* SW associated with special page */ 227 #define __HAVE_ARCH_PTE_SPECIAL 228 229 /* Set of bits not changed in pte_modify */ 230 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR) 231 232 /* Six different types of pages. */ 233 #define _PAGE_TYPE_EMPTY 0x400 234 #define _PAGE_TYPE_NONE 0x401 235 #define _PAGE_TYPE_SWAP 0x403 236 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ 237 #define _PAGE_TYPE_RO 0x200 238 #define _PAGE_TYPE_RW 0x000 239 240 /* 241 * Only four types for huge pages, using the invalid bit and protection bit 242 * of a segment table entry. 243 */ 244 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ 245 #define _HPAGE_TYPE_NONE 0x220 246 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ 247 #define _HPAGE_TYPE_RW 0x000 248 249 /* 250 * PTE type bits are rather complicated. handle_pte_fault uses pte_present, 251 * pte_none and pte_file to find out the pte type WITHOUT holding the page 252 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to 253 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs 254 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. 255 * This change is done while holding the lock, but the intermediate step 256 * of a previously valid pte with the hw invalid bit set can be observed by 257 * handle_pte_fault. That makes it necessary that all valid pte types with 258 * the hw invalid bit set must be distinguishable from the four pte types 259 * empty, none, swap and file. 260 * 261 * irxt ipte irxt 262 * _PAGE_TYPE_EMPTY 1000 -> 1000 263 * _PAGE_TYPE_NONE 1001 -> 1001 264 * _PAGE_TYPE_SWAP 1011 -> 1011 265 * _PAGE_TYPE_FILE 11?1 -> 11?1 266 * _PAGE_TYPE_RO 0100 -> 1100 267 * _PAGE_TYPE_RW 0000 -> 1000 268 * 269 * pte_none is true for bits combinations 1000, 1010, 1100, 1110 270 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 271 * pte_file is true for bits combinations 1101, 1111 272 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. 273 */ 274 275 #ifndef CONFIG_64BIT 276 277 /* Bits in the segment table address-space-control-element */ 278 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ 279 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ 280 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 281 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 282 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ 283 284 /* Bits in the segment table entry */ 285 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ 286 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 287 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 288 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ 289 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ 290 291 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) 292 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 293 294 /* Page status table bits for virtualization */ 295 #define RCP_ACC_BITS 0xf0000000UL 296 #define RCP_FP_BIT 0x08000000UL 297 #define RCP_PCL_BIT 0x00800000UL 298 #define RCP_HR_BIT 0x00400000UL 299 #define RCP_HC_BIT 0x00200000UL 300 #define RCP_GR_BIT 0x00040000UL 301 #define RCP_GC_BIT 0x00020000UL 302 303 /* User dirty / referenced bit for KVM's migration feature */ 304 #define KVM_UR_BIT 0x00008000UL 305 #define KVM_UC_BIT 0x00004000UL 306 307 #else /* CONFIG_64BIT */ 308 309 /* Bits in the segment/region table address-space-control-element */ 310 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ 311 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 312 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 313 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 314 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 315 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 316 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 317 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 318 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 319 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 320 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 321 322 /* Bits in the region table entry */ 323 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ 324 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 325 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 326 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 327 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 328 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 329 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 330 331 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) 332 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) 333 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) 334 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) 335 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) 336 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) 337 338 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */ 339 340 /* Bits in the segment table entry */ 341 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ 342 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 343 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 344 345 #define _SEGMENT_ENTRY (0) 346 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) 347 348 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ 349 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ 350 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */ 351 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT) 352 353 /* Set of bits not changed in pmd_modify */ 354 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \ 355 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO) 356 357 /* Page status table bits for virtualization */ 358 #define RCP_ACC_BITS 0xf000000000000000UL 359 #define RCP_FP_BIT 0x0800000000000000UL 360 #define RCP_PCL_BIT 0x0080000000000000UL 361 #define RCP_HR_BIT 0x0040000000000000UL 362 #define RCP_HC_BIT 0x0020000000000000UL 363 #define RCP_GR_BIT 0x0004000000000000UL 364 #define RCP_GC_BIT 0x0002000000000000UL 365 366 /* User dirty / referenced bit for KVM's migration feature */ 367 #define KVM_UR_BIT 0x0000800000000000UL 368 #define KVM_UC_BIT 0x0000400000000000UL 369 370 #endif /* CONFIG_64BIT */ 371 372 /* 373 * A user page table pointer has the space-switch-event bit, the 374 * private-space-control bit and the storage-alteration-event-control 375 * bit set. A kernel page table pointer doesn't need them. 376 */ 377 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ 378 _ASCE_ALT_EVENT) 379 380 /* 381 * Page protection definitions. 382 */ 383 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) 384 #define PAGE_RO __pgprot(_PAGE_TYPE_RO) 385 #define PAGE_RW __pgprot(_PAGE_TYPE_RW) 386 387 #define PAGE_KERNEL PAGE_RW 388 #define PAGE_COPY PAGE_RO 389 390 /* 391 * On s390 the page table entry has an invalid bit and a read-only bit. 392 * Read permission implies execute permission and write permission 393 * implies read permission. 394 */ 395 /*xwr*/ 396 #define __P000 PAGE_NONE 397 #define __P001 PAGE_RO 398 #define __P010 PAGE_RO 399 #define __P011 PAGE_RO 400 #define __P100 PAGE_RO 401 #define __P101 PAGE_RO 402 #define __P110 PAGE_RO 403 #define __P111 PAGE_RO 404 405 #define __S000 PAGE_NONE 406 #define __S001 PAGE_RO 407 #define __S010 PAGE_RW 408 #define __S011 PAGE_RW 409 #define __S100 PAGE_RO 410 #define __S101 PAGE_RO 411 #define __S110 PAGE_RW 412 #define __S111 PAGE_RW 413 414 static inline int mm_exclusive(struct mm_struct *mm) 415 { 416 return likely(mm == current->active_mm && 417 atomic_read(&mm->context.attach_count) <= 1); 418 } 419 420 static inline int mm_has_pgste(struct mm_struct *mm) 421 { 422 #ifdef CONFIG_PGSTE 423 if (unlikely(mm->context.has_pgste)) 424 return 1; 425 #endif 426 return 0; 427 } 428 /* 429 * pgd/pmd/pte query functions 430 */ 431 #ifndef CONFIG_64BIT 432 433 static inline int pgd_present(pgd_t pgd) { return 1; } 434 static inline int pgd_none(pgd_t pgd) { return 0; } 435 static inline int pgd_bad(pgd_t pgd) { return 0; } 436 437 static inline int pud_present(pud_t pud) { return 1; } 438 static inline int pud_none(pud_t pud) { return 0; } 439 static inline int pud_large(pud_t pud) { return 0; } 440 static inline int pud_bad(pud_t pud) { return 0; } 441 442 #else /* CONFIG_64BIT */ 443 444 static inline int pgd_present(pgd_t pgd) 445 { 446 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 447 return 1; 448 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; 449 } 450 451 static inline int pgd_none(pgd_t pgd) 452 { 453 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) 454 return 0; 455 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; 456 } 457 458 static inline int pgd_bad(pgd_t pgd) 459 { 460 /* 461 * With dynamic page table levels the pgd can be a region table 462 * entry or a segment table entry. Check for the bit that are 463 * invalid for either table entry. 464 */ 465 unsigned long mask = 466 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 467 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 468 return (pgd_val(pgd) & mask) != 0; 469 } 470 471 static inline int pud_present(pud_t pud) 472 { 473 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 474 return 1; 475 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; 476 } 477 478 static inline int pud_none(pud_t pud) 479 { 480 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) 481 return 0; 482 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; 483 } 484 485 static inline int pud_large(pud_t pud) 486 { 487 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3) 488 return 0; 489 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE); 490 } 491 492 static inline int pud_bad(pud_t pud) 493 { 494 /* 495 * With dynamic page table levels the pud can be a region table 496 * entry or a segment table entry. Check for the bit that are 497 * invalid for either table entry. 498 */ 499 unsigned long mask = 500 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & 501 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; 502 return (pud_val(pud) & mask) != 0; 503 } 504 505 #endif /* CONFIG_64BIT */ 506 507 static inline int pmd_present(pmd_t pmd) 508 { 509 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO; 510 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE || 511 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV); 512 } 513 514 static inline int pmd_none(pmd_t pmd) 515 { 516 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) && 517 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO); 518 } 519 520 static inline int pmd_large(pmd_t pmd) 521 { 522 #ifdef CONFIG_64BIT 523 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE); 524 #else 525 return 0; 526 #endif 527 } 528 529 static inline int pmd_bad(pmd_t pmd) 530 { 531 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; 532 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; 533 } 534 535 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 536 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 537 unsigned long addr, pmd_t *pmdp); 538 539 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 540 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 541 unsigned long address, pmd_t *pmdp, 542 pmd_t entry, int dirty); 543 544 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 545 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 546 unsigned long address, pmd_t *pmdp); 547 548 #define __HAVE_ARCH_PMD_WRITE 549 static inline int pmd_write(pmd_t pmd) 550 { 551 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0; 552 } 553 554 static inline int pmd_young(pmd_t pmd) 555 { 556 return 0; 557 } 558 559 static inline int pte_none(pte_t pte) 560 { 561 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); 562 } 563 564 static inline int pte_present(pte_t pte) 565 { 566 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; 567 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || 568 (!(pte_val(pte) & _PAGE_INVALID) && 569 !(pte_val(pte) & _PAGE_SWT)); 570 } 571 572 static inline int pte_file(pte_t pte) 573 { 574 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; 575 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; 576 } 577 578 static inline int pte_special(pte_t pte) 579 { 580 return (pte_val(pte) & _PAGE_SPECIAL); 581 } 582 583 #define __HAVE_ARCH_PTE_SAME 584 static inline int pte_same(pte_t a, pte_t b) 585 { 586 return pte_val(a) == pte_val(b); 587 } 588 589 static inline pgste_t pgste_get_lock(pte_t *ptep) 590 { 591 unsigned long new = 0; 592 #ifdef CONFIG_PGSTE 593 unsigned long old; 594 595 preempt_disable(); 596 asm( 597 " lg %0,%2\n" 598 "0: lgr %1,%0\n" 599 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */ 600 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */ 601 " csg %0,%1,%2\n" 602 " jl 0b\n" 603 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 604 : "Q" (ptep[PTRS_PER_PTE]) : "cc"); 605 #endif 606 return __pgste(new); 607 } 608 609 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste) 610 { 611 #ifdef CONFIG_PGSTE 612 asm( 613 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ 614 " stg %1,%0\n" 615 : "=Q" (ptep[PTRS_PER_PTE]) 616 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); 617 preempt_enable(); 618 #endif 619 } 620 621 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 622 { 623 #ifdef CONFIG_PGSTE 624 unsigned long address, bits; 625 unsigned char skey; 626 627 if (!pte_present(*ptep)) 628 return pgste; 629 address = pte_val(*ptep) & PAGE_MASK; 630 skey = page_get_storage_key(address); 631 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); 632 /* Clear page changed & referenced bit in the storage key */ 633 if (bits & _PAGE_CHANGED) 634 page_set_storage_key(address, skey ^ bits, 1); 635 else if (bits) 636 page_reset_referenced(address); 637 /* Transfer page changed & referenced bit to guest bits in pgste */ 638 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */ 639 /* Get host changed & referenced bits from pgste */ 640 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52; 641 /* Clear host bits in pgste. */ 642 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT); 643 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT); 644 /* Copy page access key and fetch protection bit to pgste */ 645 pgste_val(pgste) |= 646 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56; 647 /* Transfer changed and referenced to kvm user bits */ 648 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */ 649 /* Transfer changed & referenced to pte sofware bits */ 650 pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */ 651 #endif 652 return pgste; 653 654 } 655 656 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) 657 { 658 #ifdef CONFIG_PGSTE 659 int young; 660 661 if (!pte_present(*ptep)) 662 return pgste; 663 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK); 664 /* Transfer page referenced bit to pte software bit (host view) */ 665 if (young || (pgste_val(pgste) & RCP_HR_BIT)) 666 pte_val(*ptep) |= _PAGE_SWR; 667 /* Clear host referenced bit in pgste. */ 668 pgste_val(pgste) &= ~RCP_HR_BIT; 669 /* Transfer page referenced bit to guest bit in pgste */ 670 pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */ 671 #endif 672 return pgste; 673 674 } 675 676 static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) 677 { 678 #ifdef CONFIG_PGSTE 679 unsigned long address; 680 unsigned long okey, nkey; 681 682 if (!pte_present(entry)) 683 return; 684 address = pte_val(entry) & PAGE_MASK; 685 okey = nkey = page_get_storage_key(address); 686 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT); 687 /* Set page access key and fetch protection bit from pgste */ 688 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; 689 if (okey != nkey) 690 page_set_storage_key(address, nkey, 1); 691 #endif 692 } 693 694 /** 695 * struct gmap_struct - guest address space 696 * @mm: pointer to the parent mm_struct 697 * @table: pointer to the page directory 698 * @asce: address space control element for gmap page table 699 * @crst_list: list of all crst tables used in the guest address space 700 */ 701 struct gmap { 702 struct list_head list; 703 struct mm_struct *mm; 704 unsigned long *table; 705 unsigned long asce; 706 struct list_head crst_list; 707 }; 708 709 /** 710 * struct gmap_rmap - reverse mapping for segment table entries 711 * @next: pointer to the next gmap_rmap structure in the list 712 * @entry: pointer to a segment table entry 713 */ 714 struct gmap_rmap { 715 struct list_head list; 716 unsigned long *entry; 717 }; 718 719 /** 720 * struct gmap_pgtable - gmap information attached to a page table 721 * @vmaddr: address of the 1MB segment in the process virtual memory 722 * @mapper: list of segment table entries maping a page table 723 */ 724 struct gmap_pgtable { 725 unsigned long vmaddr; 726 struct list_head mapper; 727 }; 728 729 struct gmap *gmap_alloc(struct mm_struct *mm); 730 void gmap_free(struct gmap *gmap); 731 void gmap_enable(struct gmap *gmap); 732 void gmap_disable(struct gmap *gmap); 733 int gmap_map_segment(struct gmap *gmap, unsigned long from, 734 unsigned long to, unsigned long length); 735 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len); 736 unsigned long __gmap_fault(unsigned long address, struct gmap *); 737 unsigned long gmap_fault(unsigned long address, struct gmap *); 738 void gmap_discard(unsigned long from, unsigned long to, struct gmap *); 739 740 /* 741 * Certain architectures need to do special things when PTEs 742 * within a page table are directly modified. Thus, the following 743 * hook is made available. 744 */ 745 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 746 pte_t *ptep, pte_t entry) 747 { 748 pgste_t pgste; 749 750 if (mm_has_pgste(mm)) { 751 pgste = pgste_get_lock(ptep); 752 pgste_set_pte(ptep, pgste, entry); 753 *ptep = entry; 754 pgste_set_unlock(ptep, pgste); 755 } else 756 *ptep = entry; 757 } 758 759 /* 760 * query functions pte_write/pte_dirty/pte_young only work if 761 * pte_present() is true. Undefined behaviour if not.. 762 */ 763 static inline int pte_write(pte_t pte) 764 { 765 return (pte_val(pte) & _PAGE_RO) == 0; 766 } 767 768 static inline int pte_dirty(pte_t pte) 769 { 770 #ifdef CONFIG_PGSTE 771 if (pte_val(pte) & _PAGE_SWC) 772 return 1; 773 #endif 774 return 0; 775 } 776 777 static inline int pte_young(pte_t pte) 778 { 779 #ifdef CONFIG_PGSTE 780 if (pte_val(pte) & _PAGE_SWR) 781 return 1; 782 #endif 783 return 0; 784 } 785 786 /* 787 * pgd/pmd/pte modification functions 788 */ 789 790 static inline void pgd_clear(pgd_t *pgd) 791 { 792 #ifdef CONFIG_64BIT 793 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 794 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; 795 #endif 796 } 797 798 static inline void pud_clear(pud_t *pud) 799 { 800 #ifdef CONFIG_64BIT 801 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 802 pud_val(*pud) = _REGION3_ENTRY_EMPTY; 803 #endif 804 } 805 806 static inline void pmd_clear(pmd_t *pmdp) 807 { 808 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; 809 } 810 811 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 812 { 813 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 814 } 815 816 /* 817 * The following pte modification functions only work if 818 * pte_present() is true. Undefined behaviour if not.. 819 */ 820 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 821 { 822 pte_val(pte) &= _PAGE_CHG_MASK; 823 pte_val(pte) |= pgprot_val(newprot); 824 return pte; 825 } 826 827 static inline pte_t pte_wrprotect(pte_t pte) 828 { 829 /* Do not clobber _PAGE_TYPE_NONE pages! */ 830 if (!(pte_val(pte) & _PAGE_INVALID)) 831 pte_val(pte) |= _PAGE_RO; 832 return pte; 833 } 834 835 static inline pte_t pte_mkwrite(pte_t pte) 836 { 837 pte_val(pte) &= ~_PAGE_RO; 838 return pte; 839 } 840 841 static inline pte_t pte_mkclean(pte_t pte) 842 { 843 #ifdef CONFIG_PGSTE 844 pte_val(pte) &= ~_PAGE_SWC; 845 #endif 846 return pte; 847 } 848 849 static inline pte_t pte_mkdirty(pte_t pte) 850 { 851 return pte; 852 } 853 854 static inline pte_t pte_mkold(pte_t pte) 855 { 856 #ifdef CONFIG_PGSTE 857 pte_val(pte) &= ~_PAGE_SWR; 858 #endif 859 return pte; 860 } 861 862 static inline pte_t pte_mkyoung(pte_t pte) 863 { 864 return pte; 865 } 866 867 static inline pte_t pte_mkspecial(pte_t pte) 868 { 869 pte_val(pte) |= _PAGE_SPECIAL; 870 return pte; 871 } 872 873 #ifdef CONFIG_HUGETLB_PAGE 874 static inline pte_t pte_mkhuge(pte_t pte) 875 { 876 /* 877 * PROT_NONE needs to be remapped from the pte type to the ste type. 878 * The HW invalid bit is also different for pte and ste. The pte 879 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE 880 * bit, so we don't have to clear it. 881 */ 882 if (pte_val(pte) & _PAGE_INVALID) { 883 if (pte_val(pte) & _PAGE_SWT) 884 pte_val(pte) |= _HPAGE_TYPE_NONE; 885 pte_val(pte) |= _SEGMENT_ENTRY_INV; 886 } 887 /* 888 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment 889 * table entry. 890 */ 891 pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX); 892 /* 893 * Also set the change-override bit because we don't need dirty bit 894 * tracking for hugetlbfs pages. 895 */ 896 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO); 897 return pte; 898 } 899 #endif 900 901 /* 902 * Get (and clear) the user dirty bit for a pte. 903 */ 904 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, 905 pte_t *ptep) 906 { 907 pgste_t pgste; 908 int dirty = 0; 909 910 if (mm_has_pgste(mm)) { 911 pgste = pgste_get_lock(ptep); 912 pgste = pgste_update_all(ptep, pgste); 913 dirty = !!(pgste_val(pgste) & KVM_UC_BIT); 914 pgste_val(pgste) &= ~KVM_UC_BIT; 915 pgste_set_unlock(ptep, pgste); 916 return dirty; 917 } 918 return dirty; 919 } 920 921 /* 922 * Get (and clear) the user referenced bit for a pte. 923 */ 924 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, 925 pte_t *ptep) 926 { 927 pgste_t pgste; 928 int young = 0; 929 930 if (mm_has_pgste(mm)) { 931 pgste = pgste_get_lock(ptep); 932 pgste = pgste_update_young(ptep, pgste); 933 young = !!(pgste_val(pgste) & KVM_UR_BIT); 934 pgste_val(pgste) &= ~KVM_UR_BIT; 935 pgste_set_unlock(ptep, pgste); 936 } 937 return young; 938 } 939 940 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 941 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 942 unsigned long addr, pte_t *ptep) 943 { 944 pgste_t pgste; 945 pte_t pte; 946 947 if (mm_has_pgste(vma->vm_mm)) { 948 pgste = pgste_get_lock(ptep); 949 pgste = pgste_update_young(ptep, pgste); 950 pte = *ptep; 951 *ptep = pte_mkold(pte); 952 pgste_set_unlock(ptep, pgste); 953 return pte_young(pte); 954 } 955 return 0; 956 } 957 958 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 959 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 960 unsigned long address, pte_t *ptep) 961 { 962 /* No need to flush TLB 963 * On s390 reference bits are in storage key and never in TLB 964 * With virtualization we handle the reference bit, without we 965 * we can simply return */ 966 return ptep_test_and_clear_young(vma, address, ptep); 967 } 968 969 static inline void __ptep_ipte(unsigned long address, pte_t *ptep) 970 { 971 if (!(pte_val(*ptep) & _PAGE_INVALID)) { 972 #ifndef CONFIG_64BIT 973 /* pto must point to the start of the segment table */ 974 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); 975 #else 976 /* ipte in zarch mode can do the math */ 977 pte_t *pto = ptep; 978 #endif 979 asm volatile( 980 " ipte %2,%3" 981 : "=m" (*ptep) : "m" (*ptep), 982 "a" (pto), "a" (address)); 983 } 984 } 985 986 /* 987 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush 988 * both clear the TLB for the unmapped pte. The reason is that 989 * ptep_get_and_clear is used in common code (e.g. change_pte_range) 990 * to modify an active pte. The sequence is 991 * 1) ptep_get_and_clear 992 * 2) set_pte_at 993 * 3) flush_tlb_range 994 * On s390 the tlb needs to get flushed with the modification of the pte 995 * if the pte is active. The only way how this can be implemented is to 996 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range 997 * is a nop. 998 */ 999 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1000 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1001 unsigned long address, pte_t *ptep) 1002 { 1003 pgste_t pgste; 1004 pte_t pte; 1005 1006 mm->context.flush_mm = 1; 1007 if (mm_has_pgste(mm)) 1008 pgste = pgste_get_lock(ptep); 1009 1010 pte = *ptep; 1011 if (!mm_exclusive(mm)) 1012 __ptep_ipte(address, ptep); 1013 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1014 1015 if (mm_has_pgste(mm)) { 1016 pgste = pgste_update_all(&pte, pgste); 1017 pgste_set_unlock(ptep, pgste); 1018 } 1019 return pte; 1020 } 1021 1022 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1023 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, 1024 unsigned long address, 1025 pte_t *ptep) 1026 { 1027 pte_t pte; 1028 1029 mm->context.flush_mm = 1; 1030 if (mm_has_pgste(mm)) 1031 pgste_get_lock(ptep); 1032 1033 pte = *ptep; 1034 if (!mm_exclusive(mm)) 1035 __ptep_ipte(address, ptep); 1036 return pte; 1037 } 1038 1039 static inline void ptep_modify_prot_commit(struct mm_struct *mm, 1040 unsigned long address, 1041 pte_t *ptep, pte_t pte) 1042 { 1043 *ptep = pte; 1044 if (mm_has_pgste(mm)) 1045 pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE)); 1046 } 1047 1048 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH 1049 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, 1050 unsigned long address, pte_t *ptep) 1051 { 1052 pgste_t pgste; 1053 pte_t pte; 1054 1055 if (mm_has_pgste(vma->vm_mm)) 1056 pgste = pgste_get_lock(ptep); 1057 1058 pte = *ptep; 1059 __ptep_ipte(address, ptep); 1060 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1061 1062 if (mm_has_pgste(vma->vm_mm)) { 1063 pgste = pgste_update_all(&pte, pgste); 1064 pgste_set_unlock(ptep, pgste); 1065 } 1066 return pte; 1067 } 1068 1069 /* 1070 * The batched pte unmap code uses ptep_get_and_clear_full to clear the 1071 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all 1072 * tlbs of an mm if it can guarantee that the ptes of the mm_struct 1073 * cannot be accessed while the batched unmap is running. In this case 1074 * full==1 and a simple pte_clear is enough. See tlb.h. 1075 */ 1076 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 1077 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 1078 unsigned long address, 1079 pte_t *ptep, int full) 1080 { 1081 pgste_t pgste; 1082 pte_t pte; 1083 1084 if (mm_has_pgste(mm)) 1085 pgste = pgste_get_lock(ptep); 1086 1087 pte = *ptep; 1088 if (!full) 1089 __ptep_ipte(address, ptep); 1090 pte_val(*ptep) = _PAGE_TYPE_EMPTY; 1091 1092 if (mm_has_pgste(mm)) { 1093 pgste = pgste_update_all(&pte, pgste); 1094 pgste_set_unlock(ptep, pgste); 1095 } 1096 return pte; 1097 } 1098 1099 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1100 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, 1101 unsigned long address, pte_t *ptep) 1102 { 1103 pgste_t pgste; 1104 pte_t pte = *ptep; 1105 1106 if (pte_write(pte)) { 1107 mm->context.flush_mm = 1; 1108 if (mm_has_pgste(mm)) 1109 pgste = pgste_get_lock(ptep); 1110 1111 if (!mm_exclusive(mm)) 1112 __ptep_ipte(address, ptep); 1113 *ptep = pte_wrprotect(pte); 1114 1115 if (mm_has_pgste(mm)) 1116 pgste_set_unlock(ptep, pgste); 1117 } 1118 return pte; 1119 } 1120 1121 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1122 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1123 unsigned long address, pte_t *ptep, 1124 pte_t entry, int dirty) 1125 { 1126 pgste_t pgste; 1127 1128 if (pte_same(*ptep, entry)) 1129 return 0; 1130 if (mm_has_pgste(vma->vm_mm)) 1131 pgste = pgste_get_lock(ptep); 1132 1133 __ptep_ipte(address, ptep); 1134 *ptep = entry; 1135 1136 if (mm_has_pgste(vma->vm_mm)) 1137 pgste_set_unlock(ptep, pgste); 1138 return 1; 1139 } 1140 1141 /* 1142 * Conversion functions: convert a page and protection to a page entry, 1143 * and a page entry and page directory to the page they refer to. 1144 */ 1145 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) 1146 { 1147 pte_t __pte; 1148 pte_val(__pte) = physpage + pgprot_val(pgprot); 1149 return __pte; 1150 } 1151 1152 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) 1153 { 1154 unsigned long physpage = page_to_phys(page); 1155 1156 return mk_pte_phys(physpage, pgprot); 1157 } 1158 1159 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 1160 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 1161 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 1162 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 1163 1164 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1165 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1166 1167 #ifndef CONFIG_64BIT 1168 1169 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1170 #define pud_deref(pmd) ({ BUG(); 0UL; }) 1171 #define pgd_deref(pmd) ({ BUG(); 0UL; }) 1172 1173 #define pud_offset(pgd, address) ((pud_t *) pgd) 1174 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) 1175 1176 #else /* CONFIG_64BIT */ 1177 1178 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) 1179 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) 1180 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) 1181 1182 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) 1183 { 1184 pud_t *pud = (pud_t *) pgd; 1185 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) 1186 pud = (pud_t *) pgd_deref(*pgd); 1187 return pud + pud_index(address); 1188 } 1189 1190 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) 1191 { 1192 pmd_t *pmd = (pmd_t *) pud; 1193 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) 1194 pmd = (pmd_t *) pud_deref(*pud); 1195 return pmd + pmd_index(address); 1196 } 1197 1198 #endif /* CONFIG_64BIT */ 1199 1200 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) 1201 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) 1202 #define pte_page(x) pfn_to_page(pte_pfn(x)) 1203 1204 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 1205 1206 /* Find an entry in the lowest level page table.. */ 1207 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) 1208 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) 1209 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 1210 #define pte_unmap(pte) do { } while (0) 1211 1212 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp) 1213 { 1214 unsigned long sto = (unsigned long) pmdp - 1215 pmd_index(address) * sizeof(pmd_t); 1216 1217 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) { 1218 asm volatile( 1219 " .insn rrf,0xb98e0000,%2,%3,0,0" 1220 : "=m" (*pmdp) 1221 : "m" (*pmdp), "a" (sto), 1222 "a" ((address & HPAGE_MASK)) 1223 : "cc" 1224 ); 1225 } 1226 } 1227 1228 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1229 1230 #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE) 1231 #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO) 1232 #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW) 1233 1234 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1235 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable); 1236 1237 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1238 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm); 1239 1240 static inline int pmd_trans_splitting(pmd_t pmd) 1241 { 1242 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT; 1243 } 1244 1245 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1246 pmd_t *pmdp, pmd_t entry) 1247 { 1248 *pmdp = entry; 1249 } 1250 1251 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot) 1252 { 1253 /* 1254 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx) 1255 * Convert to segment table entry format. 1256 */ 1257 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE)) 1258 return pgprot_val(SEGMENT_NONE); 1259 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO)) 1260 return pgprot_val(SEGMENT_RO); 1261 return pgprot_val(SEGMENT_RW); 1262 } 1263 1264 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1265 { 1266 pmd_val(pmd) &= _SEGMENT_CHG_MASK; 1267 pmd_val(pmd) |= massage_pgprot_pmd(newprot); 1268 return pmd; 1269 } 1270 1271 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1272 { 1273 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE; 1274 return pmd; 1275 } 1276 1277 static inline pmd_t pmd_mkwrite(pmd_t pmd) 1278 { 1279 /* Do not clobber _HPAGE_TYPE_NONE pages! */ 1280 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV)) 1281 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO; 1282 return pmd; 1283 } 1284 1285 static inline pmd_t pmd_wrprotect(pmd_t pmd) 1286 { 1287 pmd_val(pmd) |= _SEGMENT_ENTRY_RO; 1288 return pmd; 1289 } 1290 1291 static inline pmd_t pmd_mkdirty(pmd_t pmd) 1292 { 1293 /* No dirty bit in the segment table entry. */ 1294 return pmd; 1295 } 1296 1297 static inline pmd_t pmd_mkold(pmd_t pmd) 1298 { 1299 /* No referenced bit in the segment table entry. */ 1300 return pmd; 1301 } 1302 1303 static inline pmd_t pmd_mkyoung(pmd_t pmd) 1304 { 1305 /* No referenced bit in the segment table entry. */ 1306 return pmd; 1307 } 1308 1309 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1310 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1311 unsigned long address, pmd_t *pmdp) 1312 { 1313 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK; 1314 long tmp, rc; 1315 int counter; 1316 1317 rc = 0; 1318 if (MACHINE_HAS_RRBM) { 1319 counter = PTRS_PER_PTE >> 6; 1320 asm volatile( 1321 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */ 1322 " ogr %1,%0\n" 1323 " la %3,0(%4,%3)\n" 1324 " brct %2,0b\n" 1325 : "=&d" (tmp), "+&d" (rc), "+d" (counter), 1326 "+a" (pmd_addr) 1327 : "a" (64 * 4096UL) : "cc"); 1328 rc = !!rc; 1329 } else { 1330 counter = PTRS_PER_PTE; 1331 asm volatile( 1332 "0: rrbe 0,%2\n" 1333 " la %2,0(%3,%2)\n" 1334 " brc 12,1f\n" 1335 " lhi %0,1\n" 1336 "1: brct %1,0b\n" 1337 : "+d" (rc), "+d" (counter), "+a" (pmd_addr) 1338 : "a" (4096UL) : "cc"); 1339 } 1340 return rc; 1341 } 1342 1343 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 1344 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 1345 unsigned long address, pmd_t *pmdp) 1346 { 1347 pmd_t pmd = *pmdp; 1348 1349 __pmd_idte(address, pmdp); 1350 pmd_clear(pmdp); 1351 return pmd; 1352 } 1353 1354 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH 1355 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma, 1356 unsigned long address, pmd_t *pmdp) 1357 { 1358 return pmdp_get_and_clear(vma->vm_mm, address, pmdp); 1359 } 1360 1361 #define __HAVE_ARCH_PMDP_INVALIDATE 1362 static inline void pmdp_invalidate(struct vm_area_struct *vma, 1363 unsigned long address, pmd_t *pmdp) 1364 { 1365 __pmd_idte(address, pmdp); 1366 } 1367 1368 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot) 1369 { 1370 pmd_t __pmd; 1371 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot); 1372 return __pmd; 1373 } 1374 1375 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot)) 1376 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) 1377 1378 static inline int pmd_trans_huge(pmd_t pmd) 1379 { 1380 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE; 1381 } 1382 1383 static inline int has_transparent_hugepage(void) 1384 { 1385 return MACHINE_HAS_HPAGE ? 1 : 0; 1386 } 1387 1388 static inline unsigned long pmd_pfn(pmd_t pmd) 1389 { 1390 if (pmd_trans_huge(pmd)) 1391 return pmd_val(pmd) >> HPAGE_SHIFT; 1392 else 1393 return pmd_val(pmd) >> PAGE_SHIFT; 1394 } 1395 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1396 1397 /* 1398 * 31 bit swap entry format: 1399 * A page-table entry has some bits we have to treat in a special way. 1400 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification 1401 * exception will occur instead of a page translation exception. The 1402 * specifiation exception has the bad habit not to store necessary 1403 * information in the lowcore. 1404 * Bit 21 and bit 22 are the page invalid bit and the page protection 1405 * bit. We set both to indicate a swapped page. 1406 * Bit 30 and 31 are used to distinguish the different page types. For 1407 * a swapped page these bits need to be zero. 1408 * This leaves the bits 1-19 and bits 24-29 to store type and offset. 1409 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 1410 * plus 24 for the offset. 1411 * 0| offset |0110|o|type |00| 1412 * 0 0000000001111111111 2222 2 22222 33 1413 * 0 1234567890123456789 0123 4 56789 01 1414 * 1415 * 64 bit swap entry format: 1416 * A page-table entry has some bits we have to treat in a special way. 1417 * Bits 52 and bit 55 have to be zero, otherwise an specification 1418 * exception will occur instead of a page translation exception. The 1419 * specifiation exception has the bad habit not to store necessary 1420 * information in the lowcore. 1421 * Bit 53 and bit 54 are the page invalid bit and the page protection 1422 * bit. We set both to indicate a swapped page. 1423 * Bit 62 and 63 are used to distinguish the different page types. For 1424 * a swapped page these bits need to be zero. 1425 * This leaves the bits 0-51 and bits 56-61 to store type and offset. 1426 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 1427 * plus 56 for the offset. 1428 * | offset |0110|o|type |00| 1429 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 1430 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 1431 */ 1432 #ifndef CONFIG_64BIT 1433 #define __SWP_OFFSET_MASK (~0UL >> 12) 1434 #else 1435 #define __SWP_OFFSET_MASK (~0UL >> 11) 1436 #endif 1437 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) 1438 { 1439 pte_t pte; 1440 offset &= __SWP_OFFSET_MASK; 1441 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | 1442 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); 1443 return pte; 1444 } 1445 1446 #define __swp_type(entry) (((entry).val >> 2) & 0x1f) 1447 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) 1448 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) 1449 1450 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1451 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 1452 1453 #ifndef CONFIG_64BIT 1454 # define PTE_FILE_MAX_BITS 26 1455 #else /* CONFIG_64BIT */ 1456 # define PTE_FILE_MAX_BITS 59 1457 #endif /* CONFIG_64BIT */ 1458 1459 #define pte_to_pgoff(__pte) \ 1460 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) 1461 1462 #define pgoff_to_pte(__off) \ 1463 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ 1464 | _PAGE_TYPE_FILE }) 1465 1466 #endif /* !__ASSEMBLY__ */ 1467 1468 #define kern_addr_valid(addr) (1) 1469 1470 extern int vmem_add_mapping(unsigned long start, unsigned long size); 1471 extern int vmem_remove_mapping(unsigned long start, unsigned long size); 1472 extern int s390_enable_sie(void); 1473 1474 /* 1475 * No page table caches to initialise 1476 */ 1477 #define pgtable_cache_init() do { } while (0) 1478 1479 #include <asm-generic/pgtable.h> 1480 1481 #endif /* _S390_PAGE_H */ 1482