1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_S390_PCI_CLP_H 3 #define _ASM_S390_PCI_CLP_H 4 5 #include <asm/clp.h> 6 7 /* 8 * Call Logical Processor - Command Codes 9 */ 10 #define CLP_LIST_PCI 0x0002 11 #define CLP_QUERY_PCI_FN 0x0003 12 #define CLP_QUERY_PCI_FNGRP 0x0004 13 #define CLP_SET_PCI_FN 0x0005 14 15 /* PCI function handle list entry */ 16 struct clp_fh_list_entry { 17 u16 device_id; 18 u16 vendor_id; 19 u32 config_state : 1; 20 u32 : 31; 21 u32 fid; /* PCI function id */ 22 u32 fh; /* PCI function handle */ 23 } __packed; 24 25 #define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */ 26 #define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */ 27 #define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */ 28 #define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */ 29 #define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */ 30 #define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */ 31 #define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */ 32 #define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */ 33 #define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */ 34 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */ 35 36 /* request or response block header length */ 37 #define LIST_PCI_HDR_LEN 32 38 39 /* Number of function handles fitting in response block */ 40 #define CLP_FH_LIST_NR_ENTRIES \ 41 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \ 42 / sizeof(struct clp_fh_list_entry)) 43 44 #define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */ 45 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */ 46 #define CLP_SET_ENABLE_MIO 2 47 #define CLP_SET_DISABLE_MIO 3 48 49 #define CLP_UTIL_STR_LEN 64 50 #define CLP_PFIP_NR_SEGMENTS 4 51 52 extern bool zpci_unique_uid; 53 54 /* List PCI functions request */ 55 struct clp_req_list_pci { 56 struct clp_req_hdr hdr; 57 u64 resume_token; 58 u64 reserved2; 59 } __packed; 60 61 /* List PCI functions response */ 62 struct clp_rsp_list_pci { 63 struct clp_rsp_hdr hdr; 64 u64 resume_token; 65 u32 reserved2; 66 u16 max_fn; 67 u8 : 7; 68 u8 uid_checking : 1; 69 u8 entry_size; 70 struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES]; 71 } __packed; 72 73 struct mio_info { 74 u32 valid : 6; 75 u32 : 26; 76 u32 : 32; 77 struct { 78 u64 wb; 79 u64 wt; 80 } addr[PCI_STD_NUM_BARS]; 81 u32 reserved[6]; 82 } __packed; 83 84 /* Query PCI function request */ 85 struct clp_req_query_pci { 86 struct clp_req_hdr hdr; 87 u32 fh; /* function handle */ 88 u32 reserved2; 89 u64 reserved3; 90 } __packed; 91 92 /* Query PCI function response */ 93 struct clp_rsp_query_pci { 94 struct clp_rsp_hdr hdr; 95 u16 vfn; /* virtual fn number */ 96 u16 : 3; 97 u16 rid_avail : 1; 98 u16 is_physfn : 1; 99 u16 reserved1 : 1; 100 u16 mio_addr_avail : 1; 101 u16 util_str_avail : 1; /* utility string available? */ 102 u16 pfgid : 8; /* pci function group id */ 103 u32 fid; /* pci function id */ 104 u8 bar_size[PCI_STD_NUM_BARS]; 105 u16 pchid; 106 __le32 bar[PCI_STD_NUM_BARS]; 107 u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */ 108 u16 : 12; 109 u16 port : 4; 110 u8 fmb_len; 111 u8 pft; /* pci function type */ 112 u64 sdma; /* start dma as */ 113 u64 edma; /* end dma as */ 114 #define ZPCI_RID_MASK_DEVFN 0x00ff 115 u16 rid; /* BUS/DEVFN PCI address */ 116 u16 reserved0; 117 u32 reserved[10]; 118 u32 uid; /* user defined id */ 119 u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */ 120 u32 reserved2[16]; 121 struct mio_info mio; 122 } __packed; 123 124 /* Query PCI function group request */ 125 struct clp_req_query_pci_grp { 126 struct clp_req_hdr hdr; 127 u32 reserved2 : 24; 128 u32 pfgid : 8; /* function group id */ 129 u32 reserved3; 130 u64 reserved4; 131 } __packed; 132 133 /* Query PCI function group response */ 134 struct clp_rsp_query_pci_grp { 135 struct clp_rsp_hdr hdr; 136 u16 : 4; 137 u16 noi : 12; /* number of interrupts */ 138 u8 version; 139 u8 : 6; 140 u8 frame : 1; 141 u8 refresh : 1; /* TLB refresh mode */ 142 u16 reserved2; 143 u16 mui; 144 u16 : 16; 145 u16 maxfaal; 146 u16 : 4; 147 u16 dnoi : 12; 148 u16 maxcpu; 149 u64 dasm; /* dma address space mask */ 150 u64 msia; /* MSI address */ 151 u64 reserved4; 152 u64 reserved5; 153 } __packed; 154 155 /* Set PCI function request */ 156 struct clp_req_set_pci { 157 struct clp_req_hdr hdr; 158 u32 fh; /* function handle */ 159 u16 reserved2; 160 u8 oc; /* operation controls */ 161 u8 ndas; /* number of dma spaces */ 162 u64 reserved3; 163 } __packed; 164 165 /* Set PCI function response */ 166 struct clp_rsp_set_pci { 167 struct clp_rsp_hdr hdr; 168 u32 fh; /* function handle */ 169 u32 reserved1; 170 u64 reserved2; 171 struct mio_info mio; 172 } __packed; 173 174 /* Combined request/response block structures used by clp insn */ 175 struct clp_req_rsp_list_pci { 176 struct clp_req_list_pci request; 177 struct clp_rsp_list_pci response; 178 } __packed; 179 180 struct clp_req_rsp_set_pci { 181 struct clp_req_set_pci request; 182 struct clp_rsp_set_pci response; 183 } __packed; 184 185 struct clp_req_rsp_query_pci { 186 struct clp_req_query_pci request; 187 struct clp_rsp_query_pci response; 188 } __packed; 189 190 struct clp_req_rsp_query_pci_grp { 191 struct clp_req_query_pci_grp request; 192 struct clp_rsp_query_pci_grp response; 193 } __packed; 194 195 #endif 196