1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright IBM Corp. 1999, 2012 4 * Author(s): Hartmut Penner <hp@de.ibm.com>, 5 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 6 * Denis Joseph Barrow, 7 */ 8 9 #ifndef _ASM_S390_LOWCORE_H 10 #define _ASM_S390_LOWCORE_H 11 12 #include <linux/types.h> 13 #include <asm/ptrace.h> 14 #include <asm/ctlreg.h> 15 #include <asm/cpu.h> 16 #include <asm/types.h> 17 #include <asm/alternative.h> 18 19 #define LC_ORDER 1 20 #define LC_PAGES 2 21 22 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL) 23 24 #ifndef __ASSEMBLY__ 25 26 struct pgm_tdb { 27 u64 data[32]; 28 }; 29 30 struct lowcore { 31 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */ 32 __u32 ipl_parmblock_ptr; /* 0x0014 */ 33 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */ 34 __u32 ext_params; /* 0x0080 */ 35 union { 36 struct { 37 __u16 ext_cpu_addr; /* 0x0084 */ 38 __u16 ext_int_code; /* 0x0086 */ 39 }; 40 __u32 ext_int_code_addr; 41 }; 42 __u32 svc_int_code; /* 0x0088 */ 43 union { 44 struct { 45 __u16 pgm_ilc; /* 0x008c */ 46 __u16 pgm_code; /* 0x008e */ 47 }; 48 __u32 pgm_int_code; 49 }; 50 __u32 data_exc_code; /* 0x0090 */ 51 __u16 mon_class_num; /* 0x0094 */ 52 union { 53 struct { 54 __u8 per_code; /* 0x0096 */ 55 __u8 per_atmid; /* 0x0097 */ 56 }; 57 __u16 per_code_combined; 58 }; 59 __u64 per_address; /* 0x0098 */ 60 __u8 exc_access_id; /* 0x00a0 */ 61 __u8 per_access_id; /* 0x00a1 */ 62 __u8 op_access_id; /* 0x00a2 */ 63 __u8 ar_mode_id; /* 0x00a3 */ 64 __u8 pad_0x00a4[0x00a8-0x00a4]; /* 0x00a4 */ 65 __u64 trans_exc_code; /* 0x00a8 */ 66 __u64 monitor_code; /* 0x00b0 */ 67 union { 68 struct { 69 __u16 subchannel_id; /* 0x00b8 */ 70 __u16 subchannel_nr; /* 0x00ba */ 71 __u32 io_int_parm; /* 0x00bc */ 72 __u32 io_int_word; /* 0x00c0 */ 73 }; 74 struct tpi_info tpi_info; /* 0x00b8 */ 75 }; 76 __u8 pad_0x00c4[0x00c8-0x00c4]; /* 0x00c4 */ 77 __u32 stfl_fac_list; /* 0x00c8 */ 78 __u8 pad_0x00cc[0x00e8-0x00cc]; /* 0x00cc */ 79 __u64 mcck_interruption_code; /* 0x00e8 */ 80 __u8 pad_0x00f0[0x00f4-0x00f0]; /* 0x00f0 */ 81 __u32 external_damage_code; /* 0x00f4 */ 82 __u64 failing_storage_address; /* 0x00f8 */ 83 __u8 pad_0x0100[0x0110-0x0100]; /* 0x0100 */ 84 __u64 pgm_last_break; /* 0x0110 */ 85 __u8 pad_0x0118[0x0120-0x0118]; /* 0x0118 */ 86 psw_t restart_old_psw; /* 0x0120 */ 87 psw_t external_old_psw; /* 0x0130 */ 88 psw_t svc_old_psw; /* 0x0140 */ 89 psw_t program_old_psw; /* 0x0150 */ 90 psw_t mcck_old_psw; /* 0x0160 */ 91 psw_t io_old_psw; /* 0x0170 */ 92 __u8 pad_0x0180[0x01a0-0x0180]; /* 0x0180 */ 93 psw_t restart_psw; /* 0x01a0 */ 94 psw_t external_new_psw; /* 0x01b0 */ 95 psw_t svc_new_psw; /* 0x01c0 */ 96 psw_t program_new_psw; /* 0x01d0 */ 97 psw_t mcck_new_psw; /* 0x01e0 */ 98 psw_t io_new_psw; /* 0x01f0 */ 99 100 /* Save areas. */ 101 __u64 save_area_sync[8]; /* 0x0200 */ 102 __u64 save_area_async[8]; /* 0x0240 */ 103 __u64 save_area_restart[1]; /* 0x0280 */ 104 105 __u64 pcpu; /* 0x0288 */ 106 107 /* Return psws. */ 108 psw_t return_psw; /* 0x0290 */ 109 psw_t return_mcck_psw; /* 0x02a0 */ 110 111 __u64 last_break; /* 0x02b0 */ 112 113 /* CPU accounting and timing values. */ 114 __u64 sys_enter_timer; /* 0x02b8 */ 115 __u64 mcck_enter_timer; /* 0x02c0 */ 116 __u64 exit_timer; /* 0x02c8 */ 117 __u64 user_timer; /* 0x02d0 */ 118 __u64 guest_timer; /* 0x02d8 */ 119 __u64 system_timer; /* 0x02e0 */ 120 __u64 hardirq_timer; /* 0x02e8 */ 121 __u64 softirq_timer; /* 0x02f0 */ 122 __u64 steal_timer; /* 0x02f8 */ 123 __u64 avg_steal_timer; /* 0x0300 */ 124 __u64 last_update_timer; /* 0x0308 */ 125 __u64 last_update_clock; /* 0x0310 */ 126 __u64 int_clock; /* 0x0318 */ 127 __u8 pad_0x0320[0x0328-0x0320]; /* 0x0320 */ 128 __u64 clock_comparator; /* 0x0328 */ 129 __u64 boot_clock[2]; /* 0x0330 */ 130 131 /* Current process. */ 132 __u64 current_task; /* 0x0340 */ 133 __u64 kernel_stack; /* 0x0348 */ 134 135 /* Interrupt, DAT-off and restartstack. */ 136 __u64 async_stack; /* 0x0350 */ 137 __u64 nodat_stack; /* 0x0358 */ 138 __u64 restart_stack; /* 0x0360 */ 139 __u64 mcck_stack; /* 0x0368 */ 140 /* Restart function and parameter. */ 141 __u64 restart_fn; /* 0x0370 */ 142 __u64 restart_data; /* 0x0378 */ 143 __u32 restart_source; /* 0x0380 */ 144 __u32 restart_flags; /* 0x0384 */ 145 146 /* Address space pointer. */ 147 struct ctlreg kernel_asce; /* 0x0388 */ 148 struct ctlreg user_asce; /* 0x0390 */ 149 150 /* 151 * The lpp and current_pid fields form a 152 * 64-bit value that is set as program 153 * parameter with the LPP instruction. 154 */ 155 __u32 lpp; /* 0x0398 */ 156 __u32 current_pid; /* 0x039c */ 157 158 /* SMP info area */ 159 __u32 cpu_nr; /* 0x03a0 */ 160 __u32 softirq_pending; /* 0x03a4 */ 161 __s32 preempt_count; /* 0x03a8 */ 162 __u32 spinlock_lockval; /* 0x03ac */ 163 __u32 spinlock_index; /* 0x03b0 */ 164 __u8 pad_0x03b4[0x03b8-0x03b4]; /* 0x03b4 */ 165 __u64 percpu_offset; /* 0x03b8 */ 166 __u8 pad_0x03c0[0x03c8-0x03c0]; /* 0x03c0 */ 167 __u64 machine_flags; /* 0x03c8 */ 168 __u64 gmap; /* 0x03d0 */ 169 __u8 pad_0x03d8[0x0400-0x03d8]; /* 0x03d8 */ 170 171 __u32 return_lpswe; /* 0x0400 */ 172 __u32 return_mcck_lpswe; /* 0x0404 */ 173 __u8 pad_0x040a[0x0e00-0x0408]; /* 0x0408 */ 174 175 /* 176 * 0xe00 contains the address of the IPL Parameter Information 177 * block. Dump tools need IPIB for IPL after dump. 178 * Note: do not change the position of any fields in 0x0e00-0x0f00 179 */ 180 __u64 ipib; /* 0x0e00 */ 181 __u32 ipib_checksum; /* 0x0e08 */ 182 __u64 vmcore_info; /* 0x0e0c */ 183 __u8 pad_0x0e14[0x0e18-0x0e14]; /* 0x0e14 */ 184 __u64 os_info; /* 0x0e18 */ 185 __u8 pad_0x0e20[0x11b0-0x0e20]; /* 0x0e20 */ 186 187 /* Pointer to the machine check extended save area */ 188 __u64 mcesad; /* 0x11b0 */ 189 190 /* 64 bit extparam used for pfault/diag 250: defined by architecture */ 191 __u64 ext_params2; /* 0x11B8 */ 192 __u8 pad_0x11c0[0x1200-0x11C0]; /* 0x11C0 */ 193 194 /* CPU register save area: defined by architecture */ 195 __u64 floating_pt_save_area[16]; /* 0x1200 */ 196 __u64 gpregs_save_area[16]; /* 0x1280 */ 197 psw_t psw_save_area; /* 0x1300 */ 198 __u8 pad_0x1310[0x1318-0x1310]; /* 0x1310 */ 199 __u32 prefixreg_save_area; /* 0x1318 */ 200 __u32 fpt_creg_save_area; /* 0x131c */ 201 __u8 pad_0x1320[0x1324-0x1320]; /* 0x1320 */ 202 __u32 tod_progreg_save_area; /* 0x1324 */ 203 __u32 cpu_timer_save_area[2]; /* 0x1328 */ 204 __u32 clock_comp_save_area[2]; /* 0x1330 */ 205 __u64 last_break_save_area; /* 0x1338 */ 206 __u32 access_regs_save_area[16]; /* 0x1340 */ 207 struct ctlreg cregs_save_area[16]; /* 0x1380 */ 208 __u8 pad_0x1400[0x1500-0x1400]; /* 0x1400 */ 209 /* Cryptography-counter designation */ 210 __u64 ccd; /* 0x1500 */ 211 /* AI-extension counter designation */ 212 __u64 aicd; /* 0x1508 */ 213 __u8 pad_0x1510[0x1800-0x1510]; /* 0x1510 */ 214 215 /* Transaction abort diagnostic block */ 216 struct pgm_tdb pgm_tdb; /* 0x1800 */ 217 __u8 pad_0x1900[0x2000-0x1900]; /* 0x1900 */ 218 } __packed __aligned(8192); 219 220 static __always_inline struct lowcore *get_lowcore(void) 221 { 222 struct lowcore *lc; 223 224 if (__is_defined(__DECOMPRESSOR)) 225 return NULL; 226 asm(ALTERNATIVE("llilh %[lc],0", "llilh %[lc],%[alt]", ALT_LOWCORE) 227 : [lc] "=d" (lc) 228 : [alt] "i" (LOWCORE_ALT_ADDRESS >> 16)); 229 return lc; 230 } 231 232 extern struct lowcore *lowcore_ptr[]; 233 234 static inline void set_prefix(__u32 address) 235 { 236 asm volatile("spx %0" : : "Q" (address) : "memory"); 237 } 238 239 #else /* __ASSEMBLY__ */ 240 241 .macro GET_LC reg 242 ALTERNATIVE "llilh \reg,0", \ 243 __stringify(llilh \reg, LOWCORE_ALT_ADDRESS >> 16), \ 244 ALT_LOWCORE 245 .endm 246 247 .macro STMG_LC start, end, savearea 248 ALTERNATIVE "stmg \start, \end, \savearea", \ 249 __stringify(stmg \start, \end, LOWCORE_ALT_ADDRESS + \savearea), \ 250 ALT_LOWCORE 251 .endm 252 253 #endif /* __ASSEMBLY__ */ 254 #endif /* _ASM_S390_LOWCORE_H */ 255