1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Vector Instructions 4 * 5 * Assembler macros to generate .byte/.word code for particular 6 * vector instructions that are supported by recent binutils (>= 2.26) only. 7 * 8 * Copyright IBM Corp. 2015 9 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> 10 */ 11 12 #ifndef __ASM_S390_FPU_INSN_ASM_H 13 #define __ASM_S390_FPU_INSN_ASM_H 14 15 #ifndef __ASM_S390_FPU_INSN_H 16 #error only <asm/fpu-insn.h> can be included directly 17 #endif 18 19 #include <asm/insn-common-asm.h> 20 21 #ifdef __ASSEMBLER__ 22 23 /* RXB - Compute most significant bit used vector registers 24 * 25 * @rxb: Operand to store computed RXB value 26 * @v1: Vector register designated operand whose MSB is stored in 27 * RXB bit 0 (instruction bit 36) and whose remaining bits 28 * are stored in instruction bits 8-11. 29 * @v2: Vector register designated operand whose MSB is stored in 30 * RXB bit 1 (instruction bit 37) and whose remaining bits 31 * are stored in instruction bits 12-15. 32 * @v3: Vector register designated operand whose MSB is stored in 33 * RXB bit 2 (instruction bit 38) and whose remaining bits 34 * are stored in instruction bits 16-19. 35 * @v4: Vector register designated operand whose MSB is stored in 36 * RXB bit 3 (instruction bit 39) and whose remaining bits 37 * are stored in instruction bits 32-35. 38 * 39 * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly 40 * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but 41 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d, 42 * and VSI. 43 * 44 * [1] IBM z/Architecture Principles of Operation, chapter "Program 45 * Execution, section "Instructions", subsection "Instruction Formats". 46 */ 47 .macro RXB rxb v1 v2=0 v3=0 v4=0 48 \rxb = 0 49 .if \v1 & 0x10 50 \rxb = \rxb | 0x08 51 .endif 52 .if \v2 & 0x10 53 \rxb = \rxb | 0x04 54 .endif 55 .if \v3 & 0x10 56 \rxb = \rxb | 0x02 57 .endif 58 .if \v4 & 0x10 59 \rxb = \rxb | 0x01 60 .endif 61 .endm 62 63 /* MRXB - Generate Element Size Control and RXB value 64 * 65 * @m: Element size control 66 * @v1: First vector register designated operand (for RXB) 67 * @v2: Second vector register designated operand (for RXB) 68 * @v3: Third vector register designated operand (for RXB) 69 * @v4: Fourth vector register designated operand (for RXB) 70 * 71 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro 72 * description for further details. 73 */ 74 .macro MRXB m v1 v2=0 v3=0 v4=0 75 rxb = 0 76 RXB rxb, \v1, \v2, \v3, \v4 77 .byte (\m << 4) | rxb 78 .endm 79 80 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields 81 * 82 * @m: Element size control 83 * @opc: Opcode 84 * @v1: First vector register designated operand (for RXB) 85 * @v2: Second vector register designated operand (for RXB) 86 * @v3: Third vector register designated operand (for RXB) 87 * @v4: Fourth vector register designated operand (for RXB) 88 * 89 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro 90 * description for further details. 91 */ 92 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0 93 MRXB \m, \v1, \v2, \v3, \v4 94 .byte \opc 95 .endm 96 97 /* Vector support instructions */ 98 99 /* VECTOR GENERATE BYTE MASK */ 100 .macro VGBM vr imm2 101 VX_NUM v1, \vr 102 .word (0xE700 | ((v1&15) << 4)) 103 .word \imm2 104 MRXBOPC 0, 0x44, v1 105 .endm 106 .macro VZERO vxr 107 VGBM \vxr, 0 108 .endm 109 .macro VONE vxr 110 VGBM \vxr, 0xFFFF 111 .endm 112 113 /* VECTOR LOAD VR ELEMENT FROM GR */ 114 .macro VLVG v, gr, disp, m 115 VX_NUM v1, \v 116 GR_NUM b2, "%r0" 117 GR_NUM r3, \gr 118 .word 0xE700 | ((v1&15) << 4) | r3 119 .word (b2 << 12) | (\disp) 120 MRXBOPC \m, 0x22, v1 121 .endm 122 .macro VLVGB v, gr, index, base 123 VLVG \v, \gr, \index, \base, 0 124 .endm 125 .macro VLVGH v, gr, index 126 VLVG \v, \gr, \index, 1 127 .endm 128 .macro VLVGF v, gr, index 129 VLVG \v, \gr, \index, 2 130 .endm 131 .macro VLVGG v, gr, index 132 VLVG \v, \gr, \index, 3 133 .endm 134 135 /* VECTOR LOAD REGISTER */ 136 .macro VLR v1, v2 137 VX_NUM v1, \v1 138 VX_NUM v2, \v2 139 .word 0xE700 | ((v1&15) << 4) | (v2&15) 140 .word 0 141 MRXBOPC 0, 0x56, v1, v2 142 .endm 143 144 /* VECTOR LOAD */ 145 .macro VL v, disp, index="%r0", base 146 VX_NUM v1, \v 147 GR_NUM x2, \index 148 GR_NUM b2, \base 149 .word 0xE700 | ((v1&15) << 4) | x2 150 .word (b2 << 12) | (\disp) 151 MRXBOPC 0, 0x06, v1 152 .endm 153 154 /* VECTOR LOAD ELEMENT */ 155 .macro VLEx vr1, disp, index="%r0", base, m3, opc 156 VX_NUM v1, \vr1 157 GR_NUM x2, \index 158 GR_NUM b2, \base 159 .word 0xE700 | ((v1&15) << 4) | x2 160 .word (b2 << 12) | (\disp) 161 MRXBOPC \m3, \opc, v1 162 .endm 163 .macro VLEB vr1, disp, index="%r0", base, m3 164 VLEx \vr1, \disp, \index, \base, \m3, 0x00 165 .endm 166 .macro VLEH vr1, disp, index="%r0", base, m3 167 VLEx \vr1, \disp, \index, \base, \m3, 0x01 168 .endm 169 .macro VLEF vr1, disp, index="%r0", base, m3 170 VLEx \vr1, \disp, \index, \base, \m3, 0x03 171 .endm 172 .macro VLEG vr1, disp, index="%r0", base, m3 173 VLEx \vr1, \disp, \index, \base, \m3, 0x02 174 .endm 175 176 /* VECTOR LOAD ELEMENT IMMEDIATE */ 177 .macro VLEIx vr1, imm2, m3, opc 178 VX_NUM v1, \vr1 179 .word 0xE700 | ((v1&15) << 4) 180 .word \imm2 181 MRXBOPC \m3, \opc, v1 182 .endm 183 .macro VLEIB vr1, imm2, index 184 VLEIx \vr1, \imm2, \index, 0x40 185 .endm 186 .macro VLEIH vr1, imm2, index 187 VLEIx \vr1, \imm2, \index, 0x41 188 .endm 189 .macro VLEIF vr1, imm2, index 190 VLEIx \vr1, \imm2, \index, 0x43 191 .endm 192 .macro VLEIG vr1, imm2, index 193 VLEIx \vr1, \imm2, \index, 0x42 194 .endm 195 196 /* VECTOR LOAD GR FROM VR ELEMENT */ 197 .macro VLGV gr, vr, disp, base="%r0", m 198 GR_NUM r1, \gr 199 GR_NUM b2, \base 200 VX_NUM v3, \vr 201 .word 0xE700 | (r1 << 4) | (v3&15) 202 .word (b2 << 12) | (\disp) 203 MRXBOPC \m, 0x21, 0, v3 204 .endm 205 .macro VLGVB gr, vr, disp, base="%r0" 206 VLGV \gr, \vr, \disp, \base, 0 207 .endm 208 .macro VLGVH gr, vr, disp, base="%r0" 209 VLGV \gr, \vr, \disp, \base, 1 210 .endm 211 .macro VLGVF gr, vr, disp, base="%r0" 212 VLGV \gr, \vr, \disp, \base, 2 213 .endm 214 .macro VLGVG gr, vr, disp, base="%r0" 215 VLGV \gr, \vr, \disp, \base, 3 216 .endm 217 218 /* VECTOR LOAD MULTIPLE */ 219 .macro VLM vfrom, vto, disp, base, hint=3 220 VX_NUM v1, \vfrom 221 VX_NUM v3, \vto 222 GR_NUM b2, \base 223 .word 0xE700 | ((v1&15) << 4) | (v3&15) 224 .word (b2 << 12) | (\disp) 225 MRXBOPC \hint, 0x36, v1, v3 226 .endm 227 228 /* VECTOR STORE */ 229 .macro VST vr1, disp, index="%r0", base 230 VX_NUM v1, \vr1 231 GR_NUM x2, \index 232 GR_NUM b2, \base 233 .word 0xE700 | ((v1&15) << 4) | (x2&15) 234 .word (b2 << 12) | (\disp) 235 MRXBOPC 0, 0x0E, v1 236 .endm 237 238 /* VECTOR STORE BYTE REVERSED ELEMENTS */ 239 .macro VSTBR vr1, disp, index="%r0", base, m 240 VX_NUM v1, \vr1 241 GR_NUM x2, \index 242 GR_NUM b2, \base 243 .word 0xE600 | ((v1&15) << 4) | (x2&15) 244 .word (b2 << 12) | (\disp) 245 MRXBOPC \m, 0x0E, v1 246 .endm 247 .macro VSTBRH vr1, disp, index="%r0", base 248 VSTBR \vr1, \disp, \index, \base, 1 249 .endm 250 .macro VSTBRF vr1, disp, index="%r0", base 251 VSTBR \vr1, \disp, \index, \base, 2 252 .endm 253 .macro VSTBRG vr1, disp, index="%r0", base 254 VSTBR \vr1, \disp, \index, \base, 3 255 .endm 256 .macro VSTBRQ vr1, disp, index="%r0", base 257 VSTBR \vr1, \disp, \index, \base, 4 258 .endm 259 260 /* VECTOR STORE MULTIPLE */ 261 .macro VSTM vfrom, vto, disp, base, hint=3 262 VX_NUM v1, \vfrom 263 VX_NUM v3, \vto 264 GR_NUM b2, \base 265 .word 0xE700 | ((v1&15) << 4) | (v3&15) 266 .word (b2 << 12) | (\disp) 267 MRXBOPC \hint, 0x3E, v1, v3 268 .endm 269 270 /* VECTOR PERMUTE */ 271 .macro VPERM vr1, vr2, vr3, vr4 272 VX_NUM v1, \vr1 273 VX_NUM v2, \vr2 274 VX_NUM v3, \vr3 275 VX_NUM v4, \vr4 276 .word 0xE700 | ((v1&15) << 4) | (v2&15) 277 .word ((v3&15) << 12) 278 MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4 279 .endm 280 281 /* VECTOR UNPACK LOGICAL LOW */ 282 .macro VUPLL vr1, vr2, m3 283 VX_NUM v1, \vr1 284 VX_NUM v2, \vr2 285 .word 0xE700 | ((v1&15) << 4) | (v2&15) 286 .word 0x0000 287 MRXBOPC \m3, 0xD4, v1, v2 288 .endm 289 .macro VUPLLB vr1, vr2 290 VUPLL \vr1, \vr2, 0 291 .endm 292 .macro VUPLLH vr1, vr2 293 VUPLL \vr1, \vr2, 1 294 .endm 295 .macro VUPLLF vr1, vr2 296 VUPLL \vr1, \vr2, 2 297 .endm 298 299 /* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */ 300 .macro VPDI vr1, vr2, vr3, m4 301 VX_NUM v1, \vr1 302 VX_NUM v2, \vr2 303 VX_NUM v3, \vr3 304 .word 0xE700 | ((v1&15) << 4) | (v2&15) 305 .word ((v3&15) << 12) 306 MRXBOPC \m4, 0x84, v1, v2, v3 307 .endm 308 309 /* VECTOR REPLICATE */ 310 .macro VREP vr1, vr3, imm2, m4 311 VX_NUM v1, \vr1 312 VX_NUM v3, \vr3 313 .word 0xE700 | ((v1&15) << 4) | (v3&15) 314 .word \imm2 315 MRXBOPC \m4, 0x4D, v1, v3 316 .endm 317 .macro VREPB vr1, vr3, imm2 318 VREP \vr1, \vr3, \imm2, 0 319 .endm 320 .macro VREPH vr1, vr3, imm2 321 VREP \vr1, \vr3, \imm2, 1 322 .endm 323 .macro VREPF vr1, vr3, imm2 324 VREP \vr1, \vr3, \imm2, 2 325 .endm 326 .macro VREPG vr1, vr3, imm2 327 VREP \vr1, \vr3, \imm2, 3 328 .endm 329 330 /* VECTOR MERGE HIGH */ 331 .macro VMRH vr1, vr2, vr3, m4 332 VX_NUM v1, \vr1 333 VX_NUM v2, \vr2 334 VX_NUM v3, \vr3 335 .word 0xE700 | ((v1&15) << 4) | (v2&15) 336 .word ((v3&15) << 12) 337 MRXBOPC \m4, 0x61, v1, v2, v3 338 .endm 339 .macro VMRHB vr1, vr2, vr3 340 VMRH \vr1, \vr2, \vr3, 0 341 .endm 342 .macro VMRHH vr1, vr2, vr3 343 VMRH \vr1, \vr2, \vr3, 1 344 .endm 345 .macro VMRHF vr1, vr2, vr3 346 VMRH \vr1, \vr2, \vr3, 2 347 .endm 348 .macro VMRHG vr1, vr2, vr3 349 VMRH \vr1, \vr2, \vr3, 3 350 .endm 351 352 /* VECTOR MERGE LOW */ 353 .macro VMRL vr1, vr2, vr3, m4 354 VX_NUM v1, \vr1 355 VX_NUM v2, \vr2 356 VX_NUM v3, \vr3 357 .word 0xE700 | ((v1&15) << 4) | (v2&15) 358 .word ((v3&15) << 12) 359 MRXBOPC \m4, 0x60, v1, v2, v3 360 .endm 361 .macro VMRLB vr1, vr2, vr3 362 VMRL \vr1, \vr2, \vr3, 0 363 .endm 364 .macro VMRLH vr1, vr2, vr3 365 VMRL \vr1, \vr2, \vr3, 1 366 .endm 367 .macro VMRLF vr1, vr2, vr3 368 VMRL \vr1, \vr2, \vr3, 2 369 .endm 370 .macro VMRLG vr1, vr2, vr3 371 VMRL \vr1, \vr2, \vr3, 3 372 .endm 373 374 /* VECTOR LOAD WITH LENGTH */ 375 .macro VLL v, gr, disp, base 376 VX_NUM v1, \v 377 GR_NUM b2, \base 378 GR_NUM r3, \gr 379 .word 0xE700 | ((v1&15) << 4) | r3 380 .word (b2 << 12) | (\disp) 381 MRXBOPC 0, 0x37, v1 382 .endm 383 384 /* VECTOR STORE WITH LENGTH */ 385 .macro VSTL v, gr, disp, base 386 VX_NUM v1, \v 387 GR_NUM b2, \base 388 GR_NUM r3, \gr 389 .word 0xE700 | ((v1&15) << 4) | r3 390 .word (b2 << 12) | (\disp) 391 MRXBOPC 0, 0x3f, v1 392 .endm 393 394 /* Vector integer instructions */ 395 396 /* VECTOR AND */ 397 .macro VN vr1, vr2, vr3 398 VX_NUM v1, \vr1 399 VX_NUM v2, \vr2 400 VX_NUM v3, \vr3 401 .word 0xE700 | ((v1&15) << 4) | (v2&15) 402 .word ((v3&15) << 12) 403 MRXBOPC 0, 0x68, v1, v2, v3 404 .endm 405 406 /* VECTOR CHECKSUM */ 407 .macro VCKSM vr1, vr2, vr3 408 VX_NUM v1, \vr1 409 VX_NUM v2, \vr2 410 VX_NUM v3, \vr3 411 .word 0xE700 | ((v1&15) << 4) | (v2&15) 412 .word ((v3&15) << 12) 413 MRXBOPC 0, 0x66, v1, v2, v3 414 .endm 415 416 /* VECTOR EXCLUSIVE OR */ 417 .macro VX vr1, vr2, vr3 418 VX_NUM v1, \vr1 419 VX_NUM v2, \vr2 420 VX_NUM v3, \vr3 421 .word 0xE700 | ((v1&15) << 4) | (v2&15) 422 .word ((v3&15) << 12) 423 MRXBOPC 0, 0x6D, v1, v2, v3 424 .endm 425 426 /* VECTOR GALOIS FIELD MULTIPLY SUM */ 427 .macro VGFM vr1, vr2, vr3, m4 428 VX_NUM v1, \vr1 429 VX_NUM v2, \vr2 430 VX_NUM v3, \vr3 431 .word 0xE700 | ((v1&15) << 4) | (v2&15) 432 .word ((v3&15) << 12) 433 MRXBOPC \m4, 0xB4, v1, v2, v3 434 .endm 435 .macro VGFMB vr1, vr2, vr3 436 VGFM \vr1, \vr2, \vr3, 0 437 .endm 438 .macro VGFMH vr1, vr2, vr3 439 VGFM \vr1, \vr2, \vr3, 1 440 .endm 441 .macro VGFMF vr1, vr2, vr3 442 VGFM \vr1, \vr2, \vr3, 2 443 .endm 444 .macro VGFMG vr1, vr2, vr3 445 VGFM \vr1, \vr2, \vr3, 3 446 .endm 447 448 /* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */ 449 .macro VGFMA vr1, vr2, vr3, vr4, m5 450 VX_NUM v1, \vr1 451 VX_NUM v2, \vr2 452 VX_NUM v3, \vr3 453 VX_NUM v4, \vr4 454 .word 0xE700 | ((v1&15) << 4) | (v2&15) 455 .word ((v3&15) << 12) | (\m5 << 8) 456 MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4 457 .endm 458 .macro VGFMAB vr1, vr2, vr3, vr4 459 VGFMA \vr1, \vr2, \vr3, \vr4, 0 460 .endm 461 .macro VGFMAH vr1, vr2, vr3, vr4 462 VGFMA \vr1, \vr2, \vr3, \vr4, 1 463 .endm 464 .macro VGFMAF vr1, vr2, vr3, vr4 465 VGFMA \vr1, \vr2, \vr3, \vr4, 2 466 .endm 467 .macro VGFMAG vr1, vr2, vr3, vr4 468 VGFMA \vr1, \vr2, \vr3, \vr4, 3 469 .endm 470 471 /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */ 472 .macro VSRLB vr1, vr2, vr3 473 VX_NUM v1, \vr1 474 VX_NUM v2, \vr2 475 VX_NUM v3, \vr3 476 .word 0xE700 | ((v1&15) << 4) | (v2&15) 477 .word ((v3&15) << 12) 478 MRXBOPC 0, 0x7D, v1, v2, v3 479 .endm 480 481 /* VECTOR REPLICATE IMMEDIATE */ 482 .macro VREPI vr1, imm2, m3 483 VX_NUM v1, \vr1 484 .word 0xE700 | ((v1&15) << 4) 485 .word \imm2 486 MRXBOPC \m3, 0x45, v1 487 .endm 488 .macro VREPIB vr1, imm2 489 VREPI \vr1, \imm2, 0 490 .endm 491 .macro VREPIH vr1, imm2 492 VREPI \vr1, \imm2, 1 493 .endm 494 .macro VREPIF vr1, imm2 495 VREPI \vr1, \imm2, 2 496 .endm 497 .macro VREPIG vr1, imm2 498 VREP \vr1, \imm2, 3 499 .endm 500 501 /* VECTOR ADD */ 502 .macro VA vr1, vr2, vr3, m4 503 VX_NUM v1, \vr1 504 VX_NUM v2, \vr2 505 VX_NUM v3, \vr3 506 .word 0xE700 | ((v1&15) << 4) | (v2&15) 507 .word ((v3&15) << 12) 508 MRXBOPC \m4, 0xF3, v1, v2, v3 509 .endm 510 .macro VAB vr1, vr2, vr3 511 VA \vr1, \vr2, \vr3, 0 512 .endm 513 .macro VAH vr1, vr2, vr3 514 VA \vr1, \vr2, \vr3, 1 515 .endm 516 .macro VAF vr1, vr2, vr3 517 VA \vr1, \vr2, \vr3, 2 518 .endm 519 .macro VAG vr1, vr2, vr3 520 VA \vr1, \vr2, \vr3, 3 521 .endm 522 .macro VAQ vr1, vr2, vr3 523 VA \vr1, \vr2, \vr3, 4 524 .endm 525 526 /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ 527 .macro VESRAV vr1, vr2, vr3, m4 528 VX_NUM v1, \vr1 529 VX_NUM v2, \vr2 530 VX_NUM v3, \vr3 531 .word 0xE700 | ((v1&15) << 4) | (v2&15) 532 .word ((v3&15) << 12) 533 MRXBOPC \m4, 0x7A, v1, v2, v3 534 .endm 535 536 .macro VESRAVB vr1, vr2, vr3 537 VESRAV \vr1, \vr2, \vr3, 0 538 .endm 539 .macro VESRAVH vr1, vr2, vr3 540 VESRAV \vr1, \vr2, \vr3, 1 541 .endm 542 .macro VESRAVF vr1, vr2, vr3 543 VESRAV \vr1, \vr2, \vr3, 2 544 .endm 545 .macro VESRAVG vr1, vr2, vr3 546 VESRAV \vr1, \vr2, \vr3, 3 547 .endm 548 549 /* VECTOR ELEMENT ROTATE LEFT LOGICAL */ 550 .macro VERLL vr1, vr3, disp, base="%r0", m4 551 VX_NUM v1, \vr1 552 VX_NUM v3, \vr3 553 GR_NUM b2, \base 554 .word 0xE700 | ((v1&15) << 4) | (v3&15) 555 .word (b2 << 12) | (\disp) 556 MRXBOPC \m4, 0x33, v1, v3 557 .endm 558 .macro VERLLB vr1, vr3, disp, base="%r0" 559 VERLL \vr1, \vr3, \disp, \base, 0 560 .endm 561 .macro VERLLH vr1, vr3, disp, base="%r0" 562 VERLL \vr1, \vr3, \disp, \base, 1 563 .endm 564 .macro VERLLF vr1, vr3, disp, base="%r0" 565 VERLL \vr1, \vr3, \disp, \base, 2 566 .endm 567 .macro VERLLG vr1, vr3, disp, base="%r0" 568 VERLL \vr1, \vr3, \disp, \base, 3 569 .endm 570 571 /* VECTOR SHIFT LEFT DOUBLE BY BYTE */ 572 .macro VSLDB vr1, vr2, vr3, imm4 573 VX_NUM v1, \vr1 574 VX_NUM v2, \vr2 575 VX_NUM v3, \vr3 576 .word 0xE700 | ((v1&15) << 4) | (v2&15) 577 .word ((v3&15) << 12) | (\imm4) 578 MRXBOPC 0, 0x77, v1, v2, v3 579 .endm 580 581 #endif /* __ASSEMBLER__ */ 582 #endif /* __ASM_S390_FPU_INSN_ASM_H */ 583