1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright IBM Corp. 1999, 2010 4 * 5 * Author(s): Hartmut Penner <hp@de.ibm.com> 6 * Martin Schwidefsky <schwidefsky@de.ibm.com> 7 * Rob van der Heij <rvdhei@iae.nl> 8 * 9 * There are 5 different IPL methods 10 * 1) load the image directly into ram at address 0 and do an PSW restart 11 * 2) linload will load the image from address 0x10000 to memory 0x10000 12 * and start the code thru LPSW 0x0008000080010000 (VM only, deprecated) 13 * 3) generate the tape ipl header, store the generated image on a tape 14 * and ipl from it 15 * In case of SL tape you need to IPL 5 times to get past VOL1 etc 16 * 4) generate the vm reader ipl header, move the generated image to the 17 * VM reader (use option NOH!) and do a ipl from reader (VM only) 18 * 5) direct call of start by the SALIPL loader 19 * We use the cpuid to distinguish between VM and native ipl 20 * params for kernel are pushed to 0x10400 (see setup.h) 21 * 22 */ 23 24#include <linux/init.h> 25#include <linux/linkage.h> 26#include <asm/asm-offsets.h> 27#include <asm/page.h> 28#include <asm/ptrace.h> 29#include <asm/sclp.h> 30 31#define ARCH_OFFSET 4 32 33#define EP_OFFSET 0x10008 34#define EP_STRING "S390EP" 35 36__HEAD 37 38#define IPL_BS 0x730 39 .org 0 40 .long 0x00080000,0x80000000+iplstart # The first 24 bytes are loaded 41 .long 0x02000018,0x60000050 # by ipl to addresses 0-23. 42 .long 0x02000068,0x60000050 # (a PSW and two CCWs). 43 .fill 80-24,1,0x40 # bytes 24-79 are discarded !! 44 .long 0x020000f0,0x60000050 # The next 160 byte are loaded 45 .long 0x02000140,0x60000050 # to addresses 0x18-0xb7 46 .long 0x02000190,0x60000050 # They form the continuation 47 .long 0x020001e0,0x60000050 # of the CCW program started 48 .long 0x02000230,0x60000050 # by ipl and load the range 49 .long 0x02000280,0x60000050 # 0x0f0-0x730 from the image 50 .long 0x020002d0,0x60000050 # to the range 0x0f0-0x730 51 .long 0x02000320,0x60000050 # in memory. At the end of 52 .long 0x02000370,0x60000050 # the channel program the PSW 53 .long 0x020003c0,0x60000050 # at location 0 is loaded. 54 .long 0x02000410,0x60000050 # Initial processing starts 55 .long 0x02000460,0x60000050 # at 0x200 = iplstart. 56 .long 0x020004b0,0x60000050 57 .long 0x02000500,0x60000050 58 .long 0x02000550,0x60000050 59 .long 0x020005a0,0x60000050 60 .long 0x020005f0,0x60000050 61 .long 0x02000640,0x60000050 62 .long 0x02000690,0x60000050 63 .long 0x020006e0,0x20000050 64 65 .org __LC_RST_NEW_PSW # 0x1a0 66 .quad 0,iplstart 67 .org __LC_EXT_NEW_PSW # 0x1b0 68 .quad 0x0002000180000000,0x1b0 # disabled wait 69 .org __LC_PGM_NEW_PSW # 0x1d0 70 .quad 0x0000000180000000,startup_pgm_check_handler 71 .org __LC_IO_NEW_PSW # 0x1f0 72 .quad 0x0002000180000000,0x1f0 # disabled wait 73 74 .org 0x200 75 76# 77# subroutine to wait for end I/O 78# 79.Lirqwait: 80 mvc __LC_IO_NEW_PSW(16),.Lnewpsw # set up IO interrupt psw 81 lpsw .Lwaitpsw 82.Lioint: 83 br %r14 84 .align 8 85.Lnewpsw: 86 .quad 0x0000000080000000,.Lioint 87.Lwaitpsw: 88 .long 0x020a0000,0x80000000+.Lioint 89 90# 91# subroutine for loading cards from the reader 92# 93.Lloader: 94 la %r4,0(%r14) 95 la %r3,.Lorb # r2 = address of orb into r2 96 la %r5,.Lirb # r4 = address of irb 97 la %r6,.Lccws 98 la %r7,20 99.Linit: 100 st %r2,4(%r6) # initialize CCW data addresses 101 la %r2,0x50(%r2) 102 la %r6,8(%r6) 103 bct 7,.Linit 104 105 lctl %c6,%c6,.Lcr6 # set IO subclass mask 106 slr %r2,%r2 107.Lldlp: 108 ssch 0(%r3) # load chunk of 1600 bytes 109 bnz .Llderr 110.Lwait4irq: 111 bas %r14,.Lirqwait 112 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 113 bne .Lwait4irq 114 tsch 0(%r5) 115 116 slr %r0,%r0 117 ic %r0,8(%r5) # get device status 118 chi %r0,8 # channel end ? 119 be .Lcont 120 chi %r0,12 # channel end + device end ? 121 be .Lcont 122 123 l %r0,4(%r5) 124 s %r0,8(%r3) # r0/8 = number of ccws executed 125 mhi %r0,10 # *10 = number of bytes in ccws 126 lh %r3,10(%r5) # get residual count 127 sr %r0,%r3 # #ccws*80-residual=#bytes read 128 ar %r2,%r0 129 130 br %r4 # r2 contains the total size 131 132.Lcont: 133 ahi %r2,0x640 # add 0x640 to total size 134 la %r6,.Lccws 135 la %r7,20 136.Lincr: 137 l %r0,4(%r6) # update CCW data addresses 138 ahi %r0,0x640 139 st %r0,4(%r6) 140 ahi %r6,8 141 bct 7,.Lincr 142 143 b .Lldlp 144.Llderr: 145 lpsw .Lcrash 146 147 .align 8 148.Lorb: .long 0x00000000,0x0080ff00,.Lccws 149.Lirb: .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 150.Lcr6: .long 0xff000000 151.Lloadp:.long 0,0 152 .align 8 153.Lcrash:.long 0x000a0000,0x00000000 154 155 .align 8 156.Lccws: .rept 19 157 .long 0x02600050,0x00000000 158 .endr 159 .long 0x02200050,0x00000000 160 161iplstart: 162 mvi __LC_AR_MODE_ID,1 # set esame flag 163 slr %r0,%r0 # set cpuid to zero 164 lhi %r1,2 # mode 2 = esame (dump) 165 sigp %r1,%r0,0x12 # switch to esame mode 166 bras %r13,0f 167 .fill 16,4,0x0 1680: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 169 sam31 # switch to 31 bit addressing mode 170 lh %r1,__LC_SUBCHANNEL_ID # test if subchannel number 171 bct %r1,.Lnoload # is valid 172 l %r1,__LC_SUBCHANNEL_ID # load ipl subchannel number 173 la %r2,IPL_BS # load start address 174 bas %r14,.Lloader # load rest of ipl image 175 l %r12,.Lparm # pointer to parameter area 176 st %r1,IPL_DEVICE+ARCH_OFFSET-PARMAREA(%r12) # save ipl device number 177 178# 179# load parameter file from ipl device 180# 181.Lagain1: 182 l %r2,.Linitrd # ramdisk loc. is temp 183 bas %r14,.Lloader # load parameter file 184 ltr %r2,%r2 # got anything ? 185 bz .Lnopf 186 l %r3,MAX_COMMAND_LINE_SIZE+ARCH_OFFSET-PARMAREA(%r12) 187 ahi %r3,-1 188 clr %r2,%r3 189 bl .Lnotrunc 190 lr %r2,%r3 191.Lnotrunc: 192 l %r4,.Linitrd 193 clc 0(3,%r4),.L_hdr # if it is HDRx 194 bz .Lagain1 # skip dataset header 195 clc 0(3,%r4),.L_eof # if it is EOFx 196 bz .Lagain1 # skip dateset trailer 197 198 lr %r5,%r2 199 la %r6,COMMAND_LINE-PARMAREA(%r12) 200 lr %r7,%r2 201 ahi %r7,1 202 mvcl %r6,%r4 203.Lnopf: 204 205# 206# load ramdisk from ipl device 207# 208.Lagain2: 209 l %r2,.Linitrd # addr of ramdisk 210 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) 211 bas %r14,.Lloader # load ramdisk 212 st %r2,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r12) # store size of rd 213 ltr %r2,%r2 214 bnz .Lrdcont 215 st %r2,INITRD_START+ARCH_OFFSET-PARMAREA(%r12) # no ramdisk found 216.Lrdcont: 217 l %r2,.Linitrd 218 219 clc 0(3,%r2),.L_hdr # skip HDRx and EOFx 220 bz .Lagain2 221 clc 0(3,%r2),.L_eof 222 bz .Lagain2 223 224# 225# reset files in VM reader 226# 227 stidp .Lcpuid # store cpuid 228 tm .Lcpuid,0xff # running VM ? 229 bno .Lnoreset 230 la %r2,.Lreset 231 lhi %r3,26 232 diag %r2,%r3,8 233 la %r5,.Lirb 234 stsch 0(%r5) # check if irq is pending 235 tm 30(%r5),0x0f # by verifying if any of the 236 bnz .Lwaitforirq # activity or status control 237 tm 31(%r5),0xff # bits is set in the schib 238 bz .Lnoreset 239.Lwaitforirq: 240 bas %r14,.Lirqwait # wait for IO interrupt 241 c %r1,__LC_SUBCHANNEL_ID # compare subchannel number 242 bne .Lwaitforirq 243 la %r5,.Lirb 244 tsch 0(%r5) 245.Lnoreset: 246 b .Lnoload 247 248# 249# everything loaded, go for it 250# 251.Lnoload: 252 l %r1,.Lstartup 253 br %r1 254 255.Linitrd:.long _end # default address of initrd 256.Lparm: .long PARMAREA 257.Lstartup: .long startup 258.Lreset:.byte 0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40 259 .byte 0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6 260 .byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold" 261.L_eof: .long 0xc5d6c600 /* C'EOF' */ 262.L_hdr: .long 0xc8c4d900 /* C'HDR' */ 263 .align 8 264.Lcpuid:.fill 8,1,0 265 266# 267# normal startup-code, running in absolute addressing mode 268# this is called either by the ipl loader or directly by PSW restart 269# or linload or SALIPL 270# 271 .org STARTUP_NORMAL_OFFSET 272SYM_CODE_START(startup) 273 j startup_normal 274 .org EP_OFFSET 275# 276# This is a list of s390 kernel entry points. At address 0x1000f the number of 277# valid entry points is stored. 278# 279# IMPORTANT: Do not change this table, it is s390 kernel ABI! 280# 281 .ascii EP_STRING 282 .byte 0x00,0x01 283# 284# kdump startup-code, running in 64 bit absolute addressing mode 285# 286 .org STARTUP_KDUMP_OFFSET 287 j startup_kdump 288SYM_CODE_END(startup) 289SYM_CODE_START_LOCAL(startup_normal) 290 mvi __LC_AR_MODE_ID,1 # set esame flag 291 slr %r0,%r0 # set cpuid to zero 292 lhi %r1,2 # mode 2 = esame (dump) 293 sigp %r1,%r0,0x12 # switch to esame mode 294 bras %r13,0f 295 .fill 16,4,0x0 2960: lmh %r0,%r15,0(%r13) # clear high-order half of gprs 297 sam64 # switch to 64 bit addressing mode 298 basr %r13,0 # get base 299.LPG0: 300 mvc __LC_EXT_NEW_PSW(16),.Lext_new_psw-.LPG0(%r13) 301 mvc __LC_PGM_NEW_PSW(16),.Lpgm_new_psw-.LPG0(%r13) 302 mvc __LC_IO_NEW_PSW(16),.Lio_new_psw-.LPG0(%r13) 303 xc 0x200(256),0x200 # partially clear lowcore 304 xc 0x300(256),0x300 305 xc 0xe00(256),0xe00 306 xc 0xf00(256),0xf00 307 lctlg %c0,%c15,.Lctl-.LPG0(%r13) # load control registers 308 stcke __LC_BOOT_CLOCK 309 mvc __LC_LAST_UPDATE_CLOCK(8),__LC_BOOT_CLOCK+1 310 spt 6f-.LPG0(%r13) 311 mvc __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13) 312 larl %r15,_stack_end-STACK_FRAME_OVERHEAD 313 brasl %r14,sclp_early_setup_buffer 314 brasl %r14,verify_facilities 315 brasl %r14,startup_kernel 316SYM_CODE_END(startup_normal) 317 318 .align 8 3196: .long 0x7fffffff,0xffffffff 320.Lext_new_psw: 321 .quad 0x0002000180000000,0x1b0 # disabled wait 322.Lpgm_new_psw: 323 .quad 0x0000000180000000,startup_pgm_check_handler 324.Lio_new_psw: 325 .quad 0x0002000180000000,0x1f0 # disabled wait 326.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space 327 .quad 0 # cr1: primary space segment table 328 .quad 0 # cr2: dispatchable unit control table 329 .quad 0 # cr3: instruction authorization 330 .quad 0xffff # cr4: instruction authorization 331 .quad 0 # cr5: primary-aste origin 332 .quad 0 # cr6: I/O interrupts 333 .quad 0 # cr7: secondary space segment table 334 .quad 0x0000000000008000 # cr8: access registers translation 335 .quad 0 # cr9: tracing off 336 .quad 0 # cr10: tracing off 337 .quad 0 # cr11: tracing off 338 .quad 0 # cr12: tracing off 339 .quad 0 # cr13: home space segment table 340 .quad 0xc0000000 # cr14: machine check handling off 341 .quad 0 # cr15: linkage stack operations 342 343#include "head_kdump.S" 344 345# 346# This program check is active immediately after kernel start 347# and until early_pgm_check_handler is set in kernel/early.c 348# It simply saves general/control registers and psw in 349# the save area and does disabled wait with a faulty address. 350# 351SYM_CODE_START_LOCAL(startup_pgm_check_handler) 352 stmg %r8,%r15,__LC_SAVE_AREA_SYNC 353 la %r8,4095 354 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8) 355 stmg %r0,%r7,__LC_GPREGS_SAVE_AREA-4095(%r8) 356 mvc __LC_GPREGS_SAVE_AREA-4095+64(64,%r8),__LC_SAVE_AREA_SYNC 357 mvc __LC_PSW_SAVE_AREA-4095(16,%r8),__LC_PGM_OLD_PSW 358 mvc __LC_RETURN_PSW(16),__LC_PGM_OLD_PSW 359 ni __LC_RETURN_PSW,0xfc # remove IO and EX bits 360 ni __LC_RETURN_PSW+1,0xfb # remove MCHK bit 361 oi __LC_RETURN_PSW+1,0x2 # set wait state bit 362 larl %r9,.Lold_psw_disabled_wait 363 stg %r9,__LC_PGM_NEW_PSW+8 364 larl %r15,_dump_info_stack_end-STACK_FRAME_OVERHEAD 365 brasl %r14,print_pgm_check_info 366.Lold_psw_disabled_wait: 367 la %r8,4095 368 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r8) 369 lpswe __LC_RETURN_PSW # disabled wait 370SYM_CODE_END(startup_pgm_check_handler) 371 372# 373# params at 10400 (setup.h) 374# Must be keept in sync with struct parmarea in setup.h 375# 376 .org PARMAREA 377SYM_DATA_START(parmarea) 378 .quad 0 # IPL_DEVICE 379 .quad 0 # INITRD_START 380 .quad 0 # INITRD_SIZE 381 .quad 0 # OLDMEM_BASE 382 .quad 0 # OLDMEM_SIZE 383 .quad kernel_version # points to kernel version string 384 .quad COMMAND_LINE_SIZE 385 386 .org COMMAND_LINE 387 .byte "root=/dev/ram0 ro" 388 .byte 0 389 .org PARMAREA+__PARMAREA_SIZE 390SYM_DATA_END(parmarea) 391