1 // SPDX-License-Identifier: GPL-2.0 2 /* BPF JIT compiler for RV64G 3 * 4 * Copyright(c) 2019 Björn Töpel <bjorn.topel@gmail.com> 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bpf.h> 10 #include <linux/filter.h> 11 #include <linux/memory.h> 12 #include <linux/stop_machine.h> 13 #include <asm/text-patching.h> 14 #include <asm/cfi.h> 15 #include <asm/percpu.h> 16 #include "bpf_jit.h" 17 18 #define RV_MAX_REG_ARGS 8 19 #define RV_FENTRY_NINSNS 2 20 #define RV_FENTRY_NBYTES (RV_FENTRY_NINSNS * 4) 21 #define RV_KCFI_NINSNS (IS_ENABLED(CONFIG_CFI_CLANG) ? 1 : 0) 22 /* imm that allows emit_imm to emit max count insns */ 23 #define RV_MAX_COUNT_IMM 0x7FFF7FF7FF7FF7FF 24 25 #define RV_REG_TCC RV_REG_A6 26 #define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ 27 #define RV_REG_ARENA RV_REG_S7 /* For storing arena_vm_start */ 28 29 static const int regmap[] = { 30 [BPF_REG_0] = RV_REG_A5, 31 [BPF_REG_1] = RV_REG_A0, 32 [BPF_REG_2] = RV_REG_A1, 33 [BPF_REG_3] = RV_REG_A2, 34 [BPF_REG_4] = RV_REG_A3, 35 [BPF_REG_5] = RV_REG_A4, 36 [BPF_REG_6] = RV_REG_S1, 37 [BPF_REG_7] = RV_REG_S2, 38 [BPF_REG_8] = RV_REG_S3, 39 [BPF_REG_9] = RV_REG_S4, 40 [BPF_REG_FP] = RV_REG_S5, 41 [BPF_REG_AX] = RV_REG_T0, 42 }; 43 44 static const int pt_regmap[] = { 45 [RV_REG_A0] = offsetof(struct pt_regs, a0), 46 [RV_REG_A1] = offsetof(struct pt_regs, a1), 47 [RV_REG_A2] = offsetof(struct pt_regs, a2), 48 [RV_REG_A3] = offsetof(struct pt_regs, a3), 49 [RV_REG_A4] = offsetof(struct pt_regs, a4), 50 [RV_REG_A5] = offsetof(struct pt_regs, a5), 51 [RV_REG_S1] = offsetof(struct pt_regs, s1), 52 [RV_REG_S2] = offsetof(struct pt_regs, s2), 53 [RV_REG_S3] = offsetof(struct pt_regs, s3), 54 [RV_REG_S4] = offsetof(struct pt_regs, s4), 55 [RV_REG_S5] = offsetof(struct pt_regs, s5), 56 [RV_REG_T0] = offsetof(struct pt_regs, t0), 57 }; 58 59 enum { 60 RV_CTX_F_SEEN_TAIL_CALL = 0, 61 RV_CTX_F_SEEN_CALL = RV_REG_RA, 62 RV_CTX_F_SEEN_S1 = RV_REG_S1, 63 RV_CTX_F_SEEN_S2 = RV_REG_S2, 64 RV_CTX_F_SEEN_S3 = RV_REG_S3, 65 RV_CTX_F_SEEN_S4 = RV_REG_S4, 66 RV_CTX_F_SEEN_S5 = RV_REG_S5, 67 RV_CTX_F_SEEN_S6 = RV_REG_S6, 68 }; 69 70 static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) 71 { 72 u8 reg = regmap[bpf_reg]; 73 74 switch (reg) { 75 case RV_CTX_F_SEEN_S1: 76 case RV_CTX_F_SEEN_S2: 77 case RV_CTX_F_SEEN_S3: 78 case RV_CTX_F_SEEN_S4: 79 case RV_CTX_F_SEEN_S5: 80 case RV_CTX_F_SEEN_S6: 81 __set_bit(reg, &ctx->flags); 82 } 83 return reg; 84 }; 85 86 static bool seen_reg(int reg, struct rv_jit_context *ctx) 87 { 88 switch (reg) { 89 case RV_CTX_F_SEEN_CALL: 90 case RV_CTX_F_SEEN_S1: 91 case RV_CTX_F_SEEN_S2: 92 case RV_CTX_F_SEEN_S3: 93 case RV_CTX_F_SEEN_S4: 94 case RV_CTX_F_SEEN_S5: 95 case RV_CTX_F_SEEN_S6: 96 return test_bit(reg, &ctx->flags); 97 } 98 return false; 99 } 100 101 static void mark_fp(struct rv_jit_context *ctx) 102 { 103 __set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); 104 } 105 106 static void mark_call(struct rv_jit_context *ctx) 107 { 108 __set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 109 } 110 111 static bool seen_call(struct rv_jit_context *ctx) 112 { 113 return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); 114 } 115 116 static void mark_tail_call(struct rv_jit_context *ctx) 117 { 118 __set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 119 } 120 121 static bool seen_tail_call(struct rv_jit_context *ctx) 122 { 123 return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); 124 } 125 126 static u8 rv_tail_call_reg(struct rv_jit_context *ctx) 127 { 128 mark_tail_call(ctx); 129 130 if (seen_call(ctx)) { 131 __set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); 132 return RV_REG_S6; 133 } 134 return RV_REG_A6; 135 } 136 137 static bool is_32b_int(s64 val) 138 { 139 return -(1L << 31) <= val && val < (1L << 31); 140 } 141 142 static bool in_auipc_jalr_range(s64 val) 143 { 144 /* 145 * auipc+jalr can reach any signed PC-relative offset in the range 146 * [-2^31 - 2^11, 2^31 - 2^11). 147 */ 148 return (-(1L << 31) - (1L << 11)) <= val && 149 val < ((1L << 31) - (1L << 11)); 150 } 151 152 /* Modify rd pointer to alternate reg to avoid corrupting original reg */ 153 static void emit_sextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) 154 { 155 emit_sextw(ra, *rd, ctx); 156 *rd = ra; 157 } 158 159 static void emit_zextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) 160 { 161 emit_zextw(ra, *rd, ctx); 162 *rd = ra; 163 } 164 165 /* Emit fixed-length instructions for address */ 166 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) 167 { 168 /* 169 * Use the ro_insns(RX) to calculate the offset as the BPF program will 170 * finally run from this memory region. 171 */ 172 u64 ip = (u64)(ctx->ro_insns + ctx->ninsns); 173 s64 off = addr - ip; 174 s64 upper = (off + (1 << 11)) >> 12; 175 s64 lower = off & 0xfff; 176 177 if (extra_pass && !in_auipc_jalr_range(off)) { 178 pr_err("bpf-jit: target offset 0x%llx is out of range\n", off); 179 return -ERANGE; 180 } 181 182 emit(rv_auipc(rd, upper), ctx); 183 emit(rv_addi(rd, rd, lower), ctx); 184 return 0; 185 } 186 187 /* Emit variable-length instructions for 32-bit and 64-bit imm */ 188 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) 189 { 190 /* Note that the immediate from the add is sign-extended, 191 * which means that we need to compensate this by adding 2^12, 192 * when the 12th bit is set. A simpler way of doing this, and 193 * getting rid of the check, is to just add 2**11 before the 194 * shift. The "Loading a 32-Bit constant" example from the 195 * "Computer Organization and Design, RISC-V edition" book by 196 * Patterson/Hennessy highlights this fact. 197 * 198 * This also means that we need to process LSB to MSB. 199 */ 200 s64 upper = (val + (1 << 11)) >> 12; 201 /* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, 202 * and addi are signed and RVC checks will perform signed comparisons. 203 */ 204 s64 lower = ((val & 0xfff) << 52) >> 52; 205 int shift; 206 207 if (is_32b_int(val)) { 208 if (upper) 209 emit_lui(rd, upper, ctx); 210 211 if (!upper) { 212 emit_li(rd, lower, ctx); 213 return; 214 } 215 216 emit_addiw(rd, rd, lower, ctx); 217 return; 218 } 219 220 shift = __ffs(upper); 221 upper >>= shift; 222 shift += 12; 223 224 emit_imm(rd, upper, ctx); 225 226 emit_slli(rd, rd, shift, ctx); 227 if (lower) 228 emit_addi(rd, rd, lower, ctx); 229 } 230 231 static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) 232 { 233 int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; 234 235 if (seen_reg(RV_REG_RA, ctx)) { 236 emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); 237 store_offset -= 8; 238 } 239 emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); 240 store_offset -= 8; 241 if (seen_reg(RV_REG_S1, ctx)) { 242 emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); 243 store_offset -= 8; 244 } 245 if (seen_reg(RV_REG_S2, ctx)) { 246 emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); 247 store_offset -= 8; 248 } 249 if (seen_reg(RV_REG_S3, ctx)) { 250 emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); 251 store_offset -= 8; 252 } 253 if (seen_reg(RV_REG_S4, ctx)) { 254 emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); 255 store_offset -= 8; 256 } 257 if (seen_reg(RV_REG_S5, ctx)) { 258 emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); 259 store_offset -= 8; 260 } 261 if (seen_reg(RV_REG_S6, ctx)) { 262 emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); 263 store_offset -= 8; 264 } 265 if (ctx->arena_vm_start) { 266 emit_ld(RV_REG_ARENA, store_offset, RV_REG_SP, ctx); 267 store_offset -= 8; 268 } 269 270 emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); 271 /* Set return value. */ 272 if (!is_tail_call) 273 emit_addiw(RV_REG_A0, RV_REG_A5, 0, ctx); 274 emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, 275 /* kcfi, fentry and TCC init insns will be skipped on tailcall */ 276 is_tail_call ? (RV_KCFI_NINSNS + RV_FENTRY_NINSNS + 1) * 4 : 0, 277 ctx); 278 } 279 280 static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, 281 struct rv_jit_context *ctx) 282 { 283 switch (cond) { 284 case BPF_JEQ: 285 emit(rv_beq(rd, rs, rvoff >> 1), ctx); 286 return; 287 case BPF_JGT: 288 emit(rv_bltu(rs, rd, rvoff >> 1), ctx); 289 return; 290 case BPF_JLT: 291 emit(rv_bltu(rd, rs, rvoff >> 1), ctx); 292 return; 293 case BPF_JGE: 294 emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); 295 return; 296 case BPF_JLE: 297 emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); 298 return; 299 case BPF_JNE: 300 emit(rv_bne(rd, rs, rvoff >> 1), ctx); 301 return; 302 case BPF_JSGT: 303 emit(rv_blt(rs, rd, rvoff >> 1), ctx); 304 return; 305 case BPF_JSLT: 306 emit(rv_blt(rd, rs, rvoff >> 1), ctx); 307 return; 308 case BPF_JSGE: 309 emit(rv_bge(rd, rs, rvoff >> 1), ctx); 310 return; 311 case BPF_JSLE: 312 emit(rv_bge(rs, rd, rvoff >> 1), ctx); 313 } 314 } 315 316 static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, 317 struct rv_jit_context *ctx) 318 { 319 s64 upper, lower; 320 321 if (is_13b_int(rvoff)) { 322 emit_bcc(cond, rd, rs, rvoff, ctx); 323 return; 324 } 325 326 /* Adjust for jal */ 327 rvoff -= 4; 328 329 /* Transform, e.g.: 330 * bne rd,rs,foo 331 * to 332 * beq rd,rs,<.L1> 333 * (auipc foo) 334 * jal(r) foo 335 * .L1 336 */ 337 cond = invert_bpf_cond(cond); 338 if (is_21b_int(rvoff)) { 339 emit_bcc(cond, rd, rs, 8, ctx); 340 emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); 341 return; 342 } 343 344 /* 32b No need for an additional rvoff adjustment, since we 345 * get that from the auipc at PC', where PC = PC' + 4. 346 */ 347 upper = (rvoff + (1 << 11)) >> 12; 348 lower = rvoff & 0xfff; 349 350 emit_bcc(cond, rd, rs, 12, ctx); 351 emit(rv_auipc(RV_REG_T1, upper), ctx); 352 emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); 353 } 354 355 static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) 356 { 357 int tc_ninsn, off, start_insn = ctx->ninsns; 358 u8 tcc = rv_tail_call_reg(ctx); 359 360 /* a0: &ctx 361 * a1: &array 362 * a2: index 363 * 364 * if (index >= array->map.max_entries) 365 * goto out; 366 */ 367 tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : 368 ctx->offset[0]; 369 emit_zextw(RV_REG_A2, RV_REG_A2, ctx); 370 371 off = offsetof(struct bpf_array, map.max_entries); 372 if (is_12b_check(off, insn)) 373 return -1; 374 emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); 375 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 376 emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); 377 378 /* if (--TCC < 0) 379 * goto out; 380 */ 381 emit_addi(RV_REG_TCC, tcc, -1, ctx); 382 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 383 emit_branch(BPF_JSLT, RV_REG_TCC, RV_REG_ZERO, off, ctx); 384 385 /* prog = array->ptrs[index]; 386 * if (!prog) 387 * goto out; 388 */ 389 emit_sh3add(RV_REG_T2, RV_REG_A2, RV_REG_A1, ctx); 390 off = offsetof(struct bpf_array, ptrs); 391 if (is_12b_check(off, insn)) 392 return -1; 393 emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); 394 off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); 395 emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); 396 397 /* goto *(prog->bpf_func + 4); */ 398 off = offsetof(struct bpf_prog, bpf_func); 399 if (is_12b_check(off, insn)) 400 return -1; 401 emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); 402 __build_epilogue(true, ctx); 403 return 0; 404 } 405 406 static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, 407 struct rv_jit_context *ctx) 408 { 409 u8 code = insn->code; 410 411 switch (code) { 412 case BPF_JMP | BPF_JA: 413 case BPF_JMP | BPF_CALL: 414 case BPF_JMP | BPF_EXIT: 415 case BPF_JMP | BPF_TAIL_CALL: 416 break; 417 default: 418 *rd = bpf_to_rv_reg(insn->dst_reg, ctx); 419 } 420 421 if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || 422 code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || 423 code & BPF_LDX || code & BPF_STX) 424 *rs = bpf_to_rv_reg(insn->src_reg, ctx); 425 } 426 427 static int emit_jump_and_link(u8 rd, s64 rvoff, bool fixed_addr, 428 struct rv_jit_context *ctx) 429 { 430 s64 upper, lower; 431 432 if (rvoff && fixed_addr && is_21b_int(rvoff)) { 433 emit(rv_jal(rd, rvoff >> 1), ctx); 434 return 0; 435 } else if (in_auipc_jalr_range(rvoff)) { 436 upper = (rvoff + (1 << 11)) >> 12; 437 lower = rvoff & 0xfff; 438 emit(rv_auipc(RV_REG_T1, upper), ctx); 439 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); 440 return 0; 441 } 442 443 pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); 444 return -ERANGE; 445 } 446 447 static bool is_signed_bpf_cond(u8 cond) 448 { 449 return cond == BPF_JSGT || cond == BPF_JSLT || 450 cond == BPF_JSGE || cond == BPF_JSLE; 451 } 452 453 static int emit_call(u64 addr, bool fixed_addr, struct rv_jit_context *ctx) 454 { 455 s64 off = 0; 456 u64 ip; 457 458 if (addr && ctx->insns && ctx->ro_insns) { 459 /* 460 * Use the ro_insns(RX) to calculate the offset as the BPF 461 * program will finally run from this memory region. 462 */ 463 ip = (u64)(long)(ctx->ro_insns + ctx->ninsns); 464 off = addr - ip; 465 } 466 467 return emit_jump_and_link(RV_REG_RA, off, fixed_addr, ctx); 468 } 469 470 static inline void emit_kcfi(u32 hash, struct rv_jit_context *ctx) 471 { 472 if (IS_ENABLED(CONFIG_CFI_CLANG)) 473 emit(hash, ctx); 474 } 475 476 static void emit_ldx_insn(u8 rd, s16 off, u8 rs, u8 size, bool sign_ext, 477 struct rv_jit_context *ctx) 478 { 479 switch (size) { 480 case BPF_B: 481 emit(sign_ext ? rv_lb(rd, off, rs) : rv_lbu(rd, off, rs), ctx); 482 break; 483 case BPF_H: 484 emit(sign_ext ? rv_lh(rd, off, rs) : rv_lhu(rd, off, rs), ctx); 485 break; 486 case BPF_W: 487 emit(sign_ext ? rv_lw(rd, off, rs) : rv_lwu(rd, off, rs), ctx); 488 break; 489 case BPF_DW: 490 emit_ld(rd, off, rs, ctx); 491 break; 492 } 493 494 } 495 496 static void emit_stx_insn(u8 rd, s16 off, u8 rs, u8 size, struct rv_jit_context *ctx) 497 { 498 switch (size) { 499 case BPF_B: 500 emit(rv_sb(rd, off, rs), ctx); 501 break; 502 case BPF_H: 503 emit(rv_sh(rd, off, rs), ctx); 504 break; 505 case BPF_W: 506 emit_sw(rd, off, rs, ctx); 507 break; 508 case BPF_DW: 509 emit_sd(rd, off, rs, ctx); 510 break; 511 } 512 } 513 514 static void emit_ldx(u8 rd, s16 off, u8 rs, u8 size, bool sign_ext, 515 struct rv_jit_context *ctx) 516 { 517 if (is_12b_int(off)) { 518 ctx->ex_insn_off = ctx->ninsns; 519 emit_ldx_insn(rd, off, rs, size, sign_ext, ctx); 520 ctx->ex_jmp_off = ctx->ninsns; 521 return; 522 } 523 524 emit_imm(RV_REG_T1, off, ctx); 525 emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); 526 ctx->ex_insn_off = ctx->ninsns; 527 emit_ldx_insn(rd, 0, RV_REG_T1, size, sign_ext, ctx); 528 ctx->ex_jmp_off = ctx->ninsns; 529 } 530 531 static void emit_st(u8 rd, s16 off, s32 imm, u8 size, struct rv_jit_context *ctx) 532 { 533 emit_imm(RV_REG_T1, imm, ctx); 534 if (is_12b_int(off)) { 535 ctx->ex_insn_off = ctx->ninsns; 536 emit_stx_insn(rd, off, RV_REG_T1, size, ctx); 537 ctx->ex_jmp_off = ctx->ninsns; 538 return; 539 } 540 541 emit_imm(RV_REG_T2, off, ctx); 542 emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); 543 ctx->ex_insn_off = ctx->ninsns; 544 emit_stx_insn(RV_REG_T2, 0, RV_REG_T1, size, ctx); 545 ctx->ex_jmp_off = ctx->ninsns; 546 } 547 548 static void emit_stx(u8 rd, s16 off, u8 rs, u8 size, struct rv_jit_context *ctx) 549 { 550 if (is_12b_int(off)) { 551 ctx->ex_insn_off = ctx->ninsns; 552 emit_stx_insn(rd, off, rs, size, ctx); 553 ctx->ex_jmp_off = ctx->ninsns; 554 return; 555 } 556 557 emit_imm(RV_REG_T1, off, ctx); 558 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 559 ctx->ex_insn_off = ctx->ninsns; 560 emit_stx_insn(RV_REG_T1, 0, rs, size, ctx); 561 ctx->ex_jmp_off = ctx->ninsns; 562 } 563 564 static int emit_atomic_ld_st(u8 rd, u8 rs, const struct bpf_insn *insn, 565 struct rv_jit_context *ctx) 566 { 567 u8 code = insn->code; 568 s32 imm = insn->imm; 569 s16 off = insn->off; 570 571 switch (imm) { 572 /* dst_reg = load_acquire(src_reg + off16) */ 573 case BPF_LOAD_ACQ: 574 emit_ldx(rd, off, rs, BPF_SIZE(code), false, ctx); 575 emit_fence_r_rw(ctx); 576 577 /* If our next insn is a redundant zext, return 1 to tell 578 * build_body() to skip it. 579 */ 580 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 581 return 1; 582 break; 583 /* store_release(dst_reg + off16, src_reg) */ 584 case BPF_STORE_REL: 585 emit_fence_rw_w(ctx); 586 emit_stx(rd, off, rs, BPF_SIZE(code), ctx); 587 break; 588 default: 589 pr_err_once("bpf-jit: invalid atomic load/store opcode %02x\n", imm); 590 return -EINVAL; 591 } 592 593 return 0; 594 } 595 596 static int emit_atomic_rmw(u8 rd, u8 rs, const struct bpf_insn *insn, 597 struct rv_jit_context *ctx) 598 { 599 u8 code = insn->code; 600 s16 off = insn->off; 601 s32 imm = insn->imm; 602 bool is64; 603 604 if (BPF_SIZE(code) != BPF_W && BPF_SIZE(code) != BPF_DW) { 605 pr_err_once("bpf-jit: 1- and 2-byte RMW atomics are not supported\n"); 606 return -EINVAL; 607 } 608 is64 = BPF_SIZE(code) == BPF_DW; 609 610 if (off) { 611 if (is_12b_int(off)) { 612 emit_addi(RV_REG_T1, rd, off, ctx); 613 } else { 614 emit_imm(RV_REG_T1, off, ctx); 615 emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); 616 } 617 rd = RV_REG_T1; 618 } 619 620 switch (imm) { 621 /* lock *(u32/u64 *)(dst_reg + off16) <op>= src_reg */ 622 case BPF_ADD: 623 emit(is64 ? rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0) : 624 rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 625 break; 626 case BPF_AND: 627 emit(is64 ? rv_amoand_d(RV_REG_ZERO, rs, rd, 0, 0) : 628 rv_amoand_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 629 break; 630 case BPF_OR: 631 emit(is64 ? rv_amoor_d(RV_REG_ZERO, rs, rd, 0, 0) : 632 rv_amoor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 633 break; 634 case BPF_XOR: 635 emit(is64 ? rv_amoxor_d(RV_REG_ZERO, rs, rd, 0, 0) : 636 rv_amoxor_w(RV_REG_ZERO, rs, rd, 0, 0), ctx); 637 break; 638 /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */ 639 case BPF_ADD | BPF_FETCH: 640 emit(is64 ? rv_amoadd_d(rs, rs, rd, 1, 1) : 641 rv_amoadd_w(rs, rs, rd, 1, 1), ctx); 642 if (!is64) 643 emit_zextw(rs, rs, ctx); 644 break; 645 case BPF_AND | BPF_FETCH: 646 emit(is64 ? rv_amoand_d(rs, rs, rd, 1, 1) : 647 rv_amoand_w(rs, rs, rd, 1, 1), ctx); 648 if (!is64) 649 emit_zextw(rs, rs, ctx); 650 break; 651 case BPF_OR | BPF_FETCH: 652 emit(is64 ? rv_amoor_d(rs, rs, rd, 1, 1) : 653 rv_amoor_w(rs, rs, rd, 1, 1), ctx); 654 if (!is64) 655 emit_zextw(rs, rs, ctx); 656 break; 657 case BPF_XOR | BPF_FETCH: 658 emit(is64 ? rv_amoxor_d(rs, rs, rd, 1, 1) : 659 rv_amoxor_w(rs, rs, rd, 1, 1), ctx); 660 if (!is64) 661 emit_zextw(rs, rs, ctx); 662 break; 663 /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */ 664 case BPF_XCHG: 665 emit(is64 ? rv_amoswap_d(rs, rs, rd, 1, 1) : 666 rv_amoswap_w(rs, rs, rd, 1, 1), ctx); 667 if (!is64) 668 emit_zextw(rs, rs, ctx); 669 break; 670 /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ 671 case BPF_CMPXCHG: 672 emit_cmpxchg(rd, rs, regmap[BPF_REG_0], is64, ctx); 673 break; 674 default: 675 pr_err_once("bpf-jit: invalid atomic RMW opcode %02x\n", imm); 676 return -EINVAL; 677 } 678 679 return 0; 680 } 681 682 #define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) 683 #define BPF_FIXUP_REG_MASK GENMASK(31, 27) 684 #define REG_DONT_CLEAR_MARKER 0 /* RV_REG_ZERO unused in pt_regmap */ 685 686 bool ex_handler_bpf(const struct exception_table_entry *ex, 687 struct pt_regs *regs) 688 { 689 off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); 690 int regs_offset = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); 691 692 if (regs_offset != REG_DONT_CLEAR_MARKER) 693 *(unsigned long *)((void *)regs + pt_regmap[regs_offset]) = 0; 694 regs->epc = (unsigned long)&ex->fixup - offset; 695 696 return true; 697 } 698 699 /* For accesses to BTF pointers, add an entry to the exception table */ 700 static int add_exception_handler(const struct bpf_insn *insn, int dst_reg, 701 struct rv_jit_context *ctx) 702 { 703 struct exception_table_entry *ex; 704 unsigned long pc; 705 off_t ins_offset; 706 off_t fixup_offset; 707 708 if (!ctx->insns || !ctx->ro_insns || !ctx->prog->aux->extable || 709 ctx->ex_insn_off <= 0 || ctx->ex_jmp_off <= 0) 710 return 0; 711 712 if (BPF_MODE(insn->code) != BPF_PROBE_MEM && 713 BPF_MODE(insn->code) != BPF_PROBE_MEMSX && 714 BPF_MODE(insn->code) != BPF_PROBE_MEM32) 715 return 0; 716 717 if (WARN_ON_ONCE(ctx->nexentries >= ctx->prog->aux->num_exentries)) 718 return -EINVAL; 719 720 if (WARN_ON_ONCE(ctx->ex_insn_off > ctx->ninsns || ctx->ex_jmp_off > ctx->ninsns)) 721 return -EINVAL; 722 723 ex = &ctx->prog->aux->extable[ctx->nexentries]; 724 pc = (unsigned long)&ctx->ro_insns[ctx->ex_insn_off]; 725 726 /* 727 * This is the relative offset of the instruction that may fault from 728 * the exception table itself. This will be written to the exception 729 * table and if this instruction faults, the destination register will 730 * be set to '0' and the execution will jump to the next instruction. 731 */ 732 ins_offset = pc - (long)&ex->insn; 733 if (WARN_ON_ONCE(ins_offset >= 0 || ins_offset < INT_MIN)) 734 return -ERANGE; 735 736 /* 737 * Since the extable follows the program, the fixup offset is always 738 * negative and limited to BPF_JIT_REGION_SIZE. Store a positive value 739 * to keep things simple, and put the destination register in the upper 740 * bits. We don't need to worry about buildtime or runtime sort 741 * modifying the upper bits because the table is already sorted, and 742 * isn't part of the main exception table. 743 * 744 * The fixup_offset is set to the next instruction from the instruction 745 * that may fault. The execution will jump to this after handling the 746 * fault. 747 */ 748 fixup_offset = (long)&ex->fixup - (long)&ctx->ro_insns[ctx->ex_jmp_off]; 749 if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, fixup_offset)) 750 return -ERANGE; 751 752 /* 753 * The offsets above have been calculated using the RO buffer but we 754 * need to use the R/W buffer for writes. 755 * switch ex to rw buffer for writing. 756 */ 757 ex = (void *)ctx->insns + ((void *)ex - (void *)ctx->ro_insns); 758 759 ex->insn = ins_offset; 760 761 ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, fixup_offset) | 762 FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); 763 ex->type = EX_TYPE_BPF; 764 765 ctx->ex_insn_off = 0; 766 ctx->ex_jmp_off = 0; 767 ctx->nexentries++; 768 return 0; 769 } 770 771 static int gen_jump_or_nops(void *target, void *ip, u32 *insns, bool is_call) 772 { 773 s64 rvoff; 774 struct rv_jit_context ctx; 775 776 ctx.ninsns = 0; 777 ctx.insns = (u16 *)insns; 778 779 if (!target) { 780 emit(rv_nop(), &ctx); 781 emit(rv_nop(), &ctx); 782 return 0; 783 } 784 785 rvoff = (s64)(target - ip); 786 return emit_jump_and_link(is_call ? RV_REG_T0 : RV_REG_ZERO, rvoff, false, &ctx); 787 } 788 789 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type poke_type, 790 void *old_addr, void *new_addr) 791 { 792 u32 old_insns[RV_FENTRY_NINSNS], new_insns[RV_FENTRY_NINSNS]; 793 bool is_call = poke_type == BPF_MOD_CALL; 794 int ret; 795 796 if (!is_kernel_text((unsigned long)ip) && 797 !is_bpf_text_address((unsigned long)ip)) 798 return -ENOTSUPP; 799 800 ret = gen_jump_or_nops(old_addr, ip, old_insns, is_call); 801 if (ret) 802 return ret; 803 804 if (memcmp(ip, old_insns, RV_FENTRY_NBYTES)) 805 return -EFAULT; 806 807 ret = gen_jump_or_nops(new_addr, ip, new_insns, is_call); 808 if (ret) 809 return ret; 810 811 cpus_read_lock(); 812 mutex_lock(&text_mutex); 813 if (memcmp(ip, new_insns, RV_FENTRY_NBYTES)) 814 ret = patch_text(ip, new_insns, RV_FENTRY_NBYTES); 815 mutex_unlock(&text_mutex); 816 cpus_read_unlock(); 817 818 return ret; 819 } 820 821 static void store_args(int nr_arg_slots, int args_off, struct rv_jit_context *ctx) 822 { 823 int i; 824 825 for (i = 0; i < nr_arg_slots; i++) { 826 if (i < RV_MAX_REG_ARGS) { 827 emit_sd(RV_REG_FP, -args_off, RV_REG_A0 + i, ctx); 828 } else { 829 /* skip slots for T0 and FP of traced function */ 830 emit_ld(RV_REG_T1, 16 + (i - RV_MAX_REG_ARGS) * 8, RV_REG_FP, ctx); 831 emit_sd(RV_REG_FP, -args_off, RV_REG_T1, ctx); 832 } 833 args_off -= 8; 834 } 835 } 836 837 static void restore_args(int nr_reg_args, int args_off, struct rv_jit_context *ctx) 838 { 839 int i; 840 841 for (i = 0; i < nr_reg_args; i++) { 842 emit_ld(RV_REG_A0 + i, -args_off, RV_REG_FP, ctx); 843 args_off -= 8; 844 } 845 } 846 847 static void restore_stack_args(int nr_stack_args, int args_off, int stk_arg_off, 848 struct rv_jit_context *ctx) 849 { 850 int i; 851 852 for (i = 0; i < nr_stack_args; i++) { 853 emit_ld(RV_REG_T1, -(args_off - RV_MAX_REG_ARGS * 8), RV_REG_FP, ctx); 854 emit_sd(RV_REG_FP, -stk_arg_off, RV_REG_T1, ctx); 855 args_off -= 8; 856 stk_arg_off -= 8; 857 } 858 } 859 860 static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_off, 861 int run_ctx_off, bool save_ret, struct rv_jit_context *ctx) 862 { 863 int ret, branch_off; 864 struct bpf_prog *p = l->link.prog; 865 int cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 866 867 if (l->cookie) { 868 emit_imm(RV_REG_T1, l->cookie, ctx); 869 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_T1, ctx); 870 } else { 871 emit_sd(RV_REG_FP, -run_ctx_off + cookie_off, RV_REG_ZERO, ctx); 872 } 873 874 /* arg1: prog */ 875 emit_imm(RV_REG_A0, (const s64)p, ctx); 876 /* arg2: &run_ctx */ 877 emit_addi(RV_REG_A1, RV_REG_FP, -run_ctx_off, ctx); 878 ret = emit_call((const u64)bpf_trampoline_enter(p), true, ctx); 879 if (ret) 880 return ret; 881 882 /* store prog start time */ 883 emit_mv(RV_REG_S1, RV_REG_A0, ctx); 884 885 /* if (__bpf_prog_enter(prog) == 0) 886 * goto skip_exec_of_prog; 887 */ 888 branch_off = ctx->ninsns; 889 /* nop reserved for conditional jump */ 890 emit(rv_nop(), ctx); 891 892 /* arg1: &args_off */ 893 emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx); 894 if (!p->jited) 895 /* arg2: progs[i]->insnsi for interpreter */ 896 emit_imm(RV_REG_A1, (const s64)p->insnsi, ctx); 897 ret = emit_call((const u64)p->bpf_func, true, ctx); 898 if (ret) 899 return ret; 900 901 if (save_ret) { 902 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 903 emit_sd(RV_REG_FP, -(retval_off - 8), regmap[BPF_REG_0], ctx); 904 } 905 906 /* update branch with beqz */ 907 if (ctx->insns) { 908 int offset = ninsns_rvoff(ctx->ninsns - branch_off); 909 u32 insn = rv_beq(RV_REG_A0, RV_REG_ZERO, offset >> 1); 910 *(u32 *)(ctx->insns + branch_off) = insn; 911 } 912 913 /* arg1: prog */ 914 emit_imm(RV_REG_A0, (const s64)p, ctx); 915 /* arg2: prog start time */ 916 emit_mv(RV_REG_A1, RV_REG_S1, ctx); 917 /* arg3: &run_ctx */ 918 emit_addi(RV_REG_A2, RV_REG_FP, -run_ctx_off, ctx); 919 ret = emit_call((const u64)bpf_trampoline_exit(p), true, ctx); 920 921 return ret; 922 } 923 924 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, 925 const struct btf_func_model *m, 926 struct bpf_tramp_links *tlinks, 927 void *func_addr, u32 flags, 928 struct rv_jit_context *ctx) 929 { 930 int i, ret, offset; 931 int *branches_off = NULL; 932 int stack_size = 0, nr_arg_slots = 0; 933 int retval_off, args_off, nregs_off, ip_off, run_ctx_off, sreg_off, stk_arg_off; 934 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 935 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 936 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 937 bool is_struct_ops = flags & BPF_TRAMP_F_INDIRECT; 938 void *orig_call = func_addr; 939 bool save_ret; 940 u32 insn; 941 942 /* Two types of generated trampoline stack layout: 943 * 944 * 1. trampoline called from function entry 945 * -------------------------------------- 946 * FP + 8 [ RA to parent func ] return address to parent 947 * function 948 * FP + 0 [ FP of parent func ] frame pointer of parent 949 * function 950 * FP - 8 [ T0 to traced func ] return address of traced 951 * function 952 * FP - 16 [ FP of traced func ] frame pointer of traced 953 * function 954 * -------------------------------------- 955 * 956 * 2. trampoline called directly 957 * -------------------------------------- 958 * FP - 8 [ RA to caller func ] return address to caller 959 * function 960 * FP - 16 [ FP of caller func ] frame pointer of caller 961 * function 962 * -------------------------------------- 963 * 964 * FP - retval_off [ return value ] BPF_TRAMP_F_CALL_ORIG or 965 * BPF_TRAMP_F_RET_FENTRY_RET 966 * [ argN ] 967 * [ ... ] 968 * FP - args_off [ arg1 ] 969 * 970 * FP - nregs_off [ regs count ] 971 * 972 * FP - ip_off [ traced func ] BPF_TRAMP_F_IP_ARG 973 * 974 * FP - run_ctx_off [ bpf_tramp_run_ctx ] 975 * 976 * FP - sreg_off [ callee saved reg ] 977 * 978 * [ pads ] pads for 16 bytes alignment 979 * 980 * [ stack_argN ] 981 * [ ... ] 982 * FP - stk_arg_off [ stack_arg1 ] BPF_TRAMP_F_CALL_ORIG 983 */ 984 985 if (flags & (BPF_TRAMP_F_ORIG_STACK | BPF_TRAMP_F_SHARE_IPMODIFY)) 986 return -ENOTSUPP; 987 988 if (m->nr_args > MAX_BPF_FUNC_ARGS) 989 return -ENOTSUPP; 990 991 for (i = 0; i < m->nr_args; i++) 992 nr_arg_slots += round_up(m->arg_size[i], 8) / 8; 993 994 /* room of trampoline frame to store return address and frame pointer */ 995 stack_size += 16; 996 997 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 998 if (save_ret) { 999 stack_size += 16; /* Save both A5 (BPF R0) and A0 */ 1000 retval_off = stack_size; 1001 } 1002 1003 stack_size += nr_arg_slots * 8; 1004 args_off = stack_size; 1005 1006 stack_size += 8; 1007 nregs_off = stack_size; 1008 1009 if (flags & BPF_TRAMP_F_IP_ARG) { 1010 stack_size += 8; 1011 ip_off = stack_size; 1012 } 1013 1014 stack_size += round_up(sizeof(struct bpf_tramp_run_ctx), 8); 1015 run_ctx_off = stack_size; 1016 1017 stack_size += 8; 1018 sreg_off = stack_size; 1019 1020 if ((flags & BPF_TRAMP_F_CALL_ORIG) && (nr_arg_slots - RV_MAX_REG_ARGS > 0)) 1021 stack_size += (nr_arg_slots - RV_MAX_REG_ARGS) * 8; 1022 1023 stack_size = round_up(stack_size, STACK_ALIGN); 1024 1025 /* room for args on stack must be at the top of stack */ 1026 stk_arg_off = stack_size; 1027 1028 if (!is_struct_ops) { 1029 /* For the trampoline called from function entry, 1030 * the frame of traced function and the frame of 1031 * trampoline need to be considered. 1032 */ 1033 emit_addi(RV_REG_SP, RV_REG_SP, -16, ctx); 1034 emit_sd(RV_REG_SP, 8, RV_REG_RA, ctx); 1035 emit_sd(RV_REG_SP, 0, RV_REG_FP, ctx); 1036 emit_addi(RV_REG_FP, RV_REG_SP, 16, ctx); 1037 1038 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 1039 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_T0, ctx); 1040 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 1041 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 1042 } else { 1043 /* emit kcfi hash */ 1044 emit_kcfi(cfi_get_func_hash(func_addr), ctx); 1045 /* For the trampoline called directly, just handle 1046 * the frame of trampoline. 1047 */ 1048 emit_addi(RV_REG_SP, RV_REG_SP, -stack_size, ctx); 1049 emit_sd(RV_REG_SP, stack_size - 8, RV_REG_RA, ctx); 1050 emit_sd(RV_REG_SP, stack_size - 16, RV_REG_FP, ctx); 1051 emit_addi(RV_REG_FP, RV_REG_SP, stack_size, ctx); 1052 } 1053 1054 /* callee saved register S1 to pass start time */ 1055 emit_sd(RV_REG_FP, -sreg_off, RV_REG_S1, ctx); 1056 1057 /* store ip address of the traced function */ 1058 if (flags & BPF_TRAMP_F_IP_ARG) { 1059 emit_imm(RV_REG_T1, (const s64)func_addr, ctx); 1060 emit_sd(RV_REG_FP, -ip_off, RV_REG_T1, ctx); 1061 } 1062 1063 emit_li(RV_REG_T1, nr_arg_slots, ctx); 1064 emit_sd(RV_REG_FP, -nregs_off, RV_REG_T1, ctx); 1065 1066 store_args(nr_arg_slots, args_off, ctx); 1067 1068 /* skip to actual body of traced function */ 1069 if (flags & BPF_TRAMP_F_SKIP_FRAME) 1070 orig_call += RV_FENTRY_NINSNS * 4; 1071 1072 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1073 emit_imm(RV_REG_A0, ctx->insns ? (const s64)im : RV_MAX_COUNT_IMM, ctx); 1074 ret = emit_call((const u64)__bpf_tramp_enter, true, ctx); 1075 if (ret) 1076 return ret; 1077 } 1078 1079 for (i = 0; i < fentry->nr_links; i++) { 1080 ret = invoke_bpf_prog(fentry->links[i], args_off, retval_off, run_ctx_off, 1081 flags & BPF_TRAMP_F_RET_FENTRY_RET, ctx); 1082 if (ret) 1083 return ret; 1084 } 1085 1086 if (fmod_ret->nr_links) { 1087 branches_off = kcalloc(fmod_ret->nr_links, sizeof(int), GFP_KERNEL); 1088 if (!branches_off) 1089 return -ENOMEM; 1090 1091 /* cleanup to avoid garbage return value confusion */ 1092 emit_sd(RV_REG_FP, -retval_off, RV_REG_ZERO, ctx); 1093 for (i = 0; i < fmod_ret->nr_links; i++) { 1094 ret = invoke_bpf_prog(fmod_ret->links[i], args_off, retval_off, 1095 run_ctx_off, true, ctx); 1096 if (ret) 1097 goto out; 1098 emit_ld(RV_REG_T1, -retval_off, RV_REG_FP, ctx); 1099 branches_off[i] = ctx->ninsns; 1100 /* nop reserved for conditional jump */ 1101 emit(rv_nop(), ctx); 1102 } 1103 } 1104 1105 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1106 restore_args(min_t(int, nr_arg_slots, RV_MAX_REG_ARGS), args_off, ctx); 1107 restore_stack_args(nr_arg_slots - RV_MAX_REG_ARGS, args_off, stk_arg_off, ctx); 1108 ret = emit_call((const u64)orig_call, true, ctx); 1109 if (ret) 1110 goto out; 1111 emit_sd(RV_REG_FP, -retval_off, RV_REG_A0, ctx); 1112 emit_sd(RV_REG_FP, -(retval_off - 8), regmap[BPF_REG_0], ctx); 1113 im->ip_after_call = ctx->ro_insns + ctx->ninsns; 1114 /* 2 nops reserved for auipc+jalr pair */ 1115 emit(rv_nop(), ctx); 1116 emit(rv_nop(), ctx); 1117 } 1118 1119 /* update branches saved in invoke_bpf_mod_ret with bnez */ 1120 for (i = 0; ctx->insns && i < fmod_ret->nr_links; i++) { 1121 offset = ninsns_rvoff(ctx->ninsns - branches_off[i]); 1122 insn = rv_bne(RV_REG_T1, RV_REG_ZERO, offset >> 1); 1123 *(u32 *)(ctx->insns + branches_off[i]) = insn; 1124 } 1125 1126 for (i = 0; i < fexit->nr_links; i++) { 1127 ret = invoke_bpf_prog(fexit->links[i], args_off, retval_off, 1128 run_ctx_off, false, ctx); 1129 if (ret) 1130 goto out; 1131 } 1132 1133 if (flags & BPF_TRAMP_F_CALL_ORIG) { 1134 im->ip_epilogue = ctx->ro_insns + ctx->ninsns; 1135 emit_imm(RV_REG_A0, ctx->insns ? (const s64)im : RV_MAX_COUNT_IMM, ctx); 1136 ret = emit_call((const u64)__bpf_tramp_exit, true, ctx); 1137 if (ret) 1138 goto out; 1139 } 1140 1141 if (flags & BPF_TRAMP_F_RESTORE_REGS) 1142 restore_args(min_t(int, nr_arg_slots, RV_MAX_REG_ARGS), args_off, ctx); 1143 1144 if (save_ret) { 1145 emit_ld(RV_REG_A0, -retval_off, RV_REG_FP, ctx); 1146 emit_ld(regmap[BPF_REG_0], -(retval_off - 8), RV_REG_FP, ctx); 1147 } 1148 1149 emit_ld(RV_REG_S1, -sreg_off, RV_REG_FP, ctx); 1150 1151 if (!is_struct_ops) { 1152 /* trampoline called from function entry */ 1153 emit_ld(RV_REG_T0, stack_size - 8, RV_REG_SP, ctx); 1154 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1155 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1156 1157 emit_ld(RV_REG_RA, 8, RV_REG_SP, ctx); 1158 emit_ld(RV_REG_FP, 0, RV_REG_SP, ctx); 1159 emit_addi(RV_REG_SP, RV_REG_SP, 16, ctx); 1160 1161 if (flags & BPF_TRAMP_F_SKIP_FRAME) 1162 /* return to parent function */ 1163 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1164 else 1165 /* return to traced function */ 1166 emit_jalr(RV_REG_ZERO, RV_REG_T0, 0, ctx); 1167 } else { 1168 /* trampoline called directly */ 1169 emit_ld(RV_REG_RA, stack_size - 8, RV_REG_SP, ctx); 1170 emit_ld(RV_REG_FP, stack_size - 16, RV_REG_SP, ctx); 1171 emit_addi(RV_REG_SP, RV_REG_SP, stack_size, ctx); 1172 1173 emit_jalr(RV_REG_ZERO, RV_REG_RA, 0, ctx); 1174 } 1175 1176 ret = ctx->ninsns; 1177 out: 1178 kfree(branches_off); 1179 return ret; 1180 } 1181 1182 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 1183 struct bpf_tramp_links *tlinks, void *func_addr) 1184 { 1185 struct bpf_tramp_image im; 1186 struct rv_jit_context ctx; 1187 int ret; 1188 1189 ctx.ninsns = 0; 1190 ctx.insns = NULL; 1191 ctx.ro_insns = NULL; 1192 ret = __arch_prepare_bpf_trampoline(&im, m, tlinks, func_addr, flags, &ctx); 1193 1194 return ret < 0 ? ret : ninsns_rvoff(ctx.ninsns); 1195 } 1196 1197 void *arch_alloc_bpf_trampoline(unsigned int size) 1198 { 1199 return bpf_prog_pack_alloc(size, bpf_fill_ill_insns); 1200 } 1201 1202 void arch_free_bpf_trampoline(void *image, unsigned int size) 1203 { 1204 bpf_prog_pack_free(image, size); 1205 } 1206 1207 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *ro_image, 1208 void *ro_image_end, const struct btf_func_model *m, 1209 u32 flags, struct bpf_tramp_links *tlinks, 1210 void *func_addr) 1211 { 1212 int ret; 1213 void *image, *res; 1214 struct rv_jit_context ctx; 1215 u32 size = ro_image_end - ro_image; 1216 1217 image = kvmalloc(size, GFP_KERNEL); 1218 if (!image) 1219 return -ENOMEM; 1220 1221 ctx.ninsns = 0; 1222 ctx.insns = image; 1223 ctx.ro_insns = ro_image; 1224 ret = __arch_prepare_bpf_trampoline(im, m, tlinks, func_addr, flags, &ctx); 1225 if (ret < 0) 1226 goto out; 1227 1228 if (WARN_ON(size < ninsns_rvoff(ctx.ninsns))) { 1229 ret = -E2BIG; 1230 goto out; 1231 } 1232 1233 res = bpf_arch_text_copy(ro_image, image, size); 1234 if (IS_ERR(res)) { 1235 ret = PTR_ERR(res); 1236 goto out; 1237 } 1238 1239 bpf_flush_icache(ro_image, ro_image_end); 1240 out: 1241 kvfree(image); 1242 return ret < 0 ? ret : size; 1243 } 1244 1245 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1246 bool extra_pass) 1247 { 1248 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || 1249 BPF_CLASS(insn->code) == BPF_JMP; 1250 int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; 1251 struct bpf_prog_aux *aux = ctx->prog->aux; 1252 u8 rd = -1, rs = -1, code = insn->code; 1253 s16 off = insn->off; 1254 s32 imm = insn->imm; 1255 1256 init_regs(&rd, &rs, insn, ctx); 1257 1258 switch (code) { 1259 /* dst = src */ 1260 case BPF_ALU | BPF_MOV | BPF_X: 1261 case BPF_ALU64 | BPF_MOV | BPF_X: 1262 if (insn_is_cast_user(insn)) { 1263 emit_mv(RV_REG_T1, rs, ctx); 1264 emit_zextw(RV_REG_T1, RV_REG_T1, ctx); 1265 emit_imm(rd, (ctx->user_vm_start >> 32) << 32, ctx); 1266 emit(rv_beq(RV_REG_T1, RV_REG_ZERO, 4), ctx); 1267 emit_or(RV_REG_T1, rd, RV_REG_T1, ctx); 1268 emit_mv(rd, RV_REG_T1, ctx); 1269 break; 1270 } else if (insn_is_mov_percpu_addr(insn)) { 1271 if (rd != rs) 1272 emit_mv(rd, rs, ctx); 1273 #ifdef CONFIG_SMP 1274 /* Load current CPU number in T1 */ 1275 emit_ld(RV_REG_T1, offsetof(struct thread_info, cpu), 1276 RV_REG_TP, ctx); 1277 /* Load address of __per_cpu_offset array in T2 */ 1278 emit_addr(RV_REG_T2, (u64)&__per_cpu_offset, extra_pass, ctx); 1279 /* Get address of __per_cpu_offset[cpu] in T1 */ 1280 emit_sh3add(RV_REG_T1, RV_REG_T1, RV_REG_T2, ctx); 1281 /* Load __per_cpu_offset[cpu] in T1 */ 1282 emit_ld(RV_REG_T1, 0, RV_REG_T1, ctx); 1283 /* Add the offset to Rd */ 1284 emit_add(rd, rd, RV_REG_T1, ctx); 1285 #endif 1286 } 1287 if (imm == 1) { 1288 /* Special mov32 for zext */ 1289 emit_zextw(rd, rd, ctx); 1290 break; 1291 } 1292 switch (insn->off) { 1293 case 0: 1294 emit_mv(rd, rs, ctx); 1295 break; 1296 case 8: 1297 emit_sextb(rd, rs, ctx); 1298 break; 1299 case 16: 1300 emit_sexth(rd, rs, ctx); 1301 break; 1302 case 32: 1303 emit_sextw(rd, rs, ctx); 1304 break; 1305 } 1306 if (!is64 && !aux->verifier_zext) 1307 emit_zextw(rd, rd, ctx); 1308 break; 1309 1310 /* dst = dst OP src */ 1311 case BPF_ALU | BPF_ADD | BPF_X: 1312 case BPF_ALU64 | BPF_ADD | BPF_X: 1313 emit_add(rd, rd, rs, ctx); 1314 if (!is64 && !aux->verifier_zext) 1315 emit_zextw(rd, rd, ctx); 1316 break; 1317 case BPF_ALU | BPF_SUB | BPF_X: 1318 case BPF_ALU64 | BPF_SUB | BPF_X: 1319 if (is64) 1320 emit_sub(rd, rd, rs, ctx); 1321 else 1322 emit_subw(rd, rd, rs, ctx); 1323 1324 if (!is64 && !aux->verifier_zext) 1325 emit_zextw(rd, rd, ctx); 1326 break; 1327 case BPF_ALU | BPF_AND | BPF_X: 1328 case BPF_ALU64 | BPF_AND | BPF_X: 1329 emit_and(rd, rd, rs, ctx); 1330 if (!is64 && !aux->verifier_zext) 1331 emit_zextw(rd, rd, ctx); 1332 break; 1333 case BPF_ALU | BPF_OR | BPF_X: 1334 case BPF_ALU64 | BPF_OR | BPF_X: 1335 emit_or(rd, rd, rs, ctx); 1336 if (!is64 && !aux->verifier_zext) 1337 emit_zextw(rd, rd, ctx); 1338 break; 1339 case BPF_ALU | BPF_XOR | BPF_X: 1340 case BPF_ALU64 | BPF_XOR | BPF_X: 1341 emit_xor(rd, rd, rs, ctx); 1342 if (!is64 && !aux->verifier_zext) 1343 emit_zextw(rd, rd, ctx); 1344 break; 1345 case BPF_ALU | BPF_MUL | BPF_X: 1346 case BPF_ALU64 | BPF_MUL | BPF_X: 1347 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); 1348 if (!is64 && !aux->verifier_zext) 1349 emit_zextw(rd, rd, ctx); 1350 break; 1351 case BPF_ALU | BPF_DIV | BPF_X: 1352 case BPF_ALU64 | BPF_DIV | BPF_X: 1353 if (off) 1354 emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx); 1355 else 1356 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); 1357 if (!is64 && !aux->verifier_zext) 1358 emit_zextw(rd, rd, ctx); 1359 break; 1360 case BPF_ALU | BPF_MOD | BPF_X: 1361 case BPF_ALU64 | BPF_MOD | BPF_X: 1362 if (off) 1363 emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx); 1364 else 1365 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); 1366 if (!is64 && !aux->verifier_zext) 1367 emit_zextw(rd, rd, ctx); 1368 break; 1369 case BPF_ALU | BPF_LSH | BPF_X: 1370 case BPF_ALU64 | BPF_LSH | BPF_X: 1371 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); 1372 if (!is64 && !aux->verifier_zext) 1373 emit_zextw(rd, rd, ctx); 1374 break; 1375 case BPF_ALU | BPF_RSH | BPF_X: 1376 case BPF_ALU64 | BPF_RSH | BPF_X: 1377 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); 1378 if (!is64 && !aux->verifier_zext) 1379 emit_zextw(rd, rd, ctx); 1380 break; 1381 case BPF_ALU | BPF_ARSH | BPF_X: 1382 case BPF_ALU64 | BPF_ARSH | BPF_X: 1383 emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); 1384 if (!is64 && !aux->verifier_zext) 1385 emit_zextw(rd, rd, ctx); 1386 break; 1387 1388 /* dst = -dst */ 1389 case BPF_ALU | BPF_NEG: 1390 case BPF_ALU64 | BPF_NEG: 1391 emit_sub(rd, RV_REG_ZERO, rd, ctx); 1392 if (!is64 && !aux->verifier_zext) 1393 emit_zextw(rd, rd, ctx); 1394 break; 1395 1396 /* dst = BSWAP##imm(dst) */ 1397 case BPF_ALU | BPF_END | BPF_FROM_LE: 1398 switch (imm) { 1399 case 16: 1400 emit_zexth(rd, rd, ctx); 1401 break; 1402 case 32: 1403 if (!aux->verifier_zext) 1404 emit_zextw(rd, rd, ctx); 1405 break; 1406 case 64: 1407 /* Do nothing */ 1408 break; 1409 } 1410 break; 1411 case BPF_ALU | BPF_END | BPF_FROM_BE: 1412 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1413 emit_bswap(rd, imm, ctx); 1414 break; 1415 1416 /* dst = imm */ 1417 case BPF_ALU | BPF_MOV | BPF_K: 1418 case BPF_ALU64 | BPF_MOV | BPF_K: 1419 emit_imm(rd, imm, ctx); 1420 if (!is64 && !aux->verifier_zext) 1421 emit_zextw(rd, rd, ctx); 1422 break; 1423 1424 /* dst = dst OP imm */ 1425 case BPF_ALU | BPF_ADD | BPF_K: 1426 case BPF_ALU64 | BPF_ADD | BPF_K: 1427 if (is_12b_int(imm)) { 1428 emit_addi(rd, rd, imm, ctx); 1429 } else { 1430 emit_imm(RV_REG_T1, imm, ctx); 1431 emit_add(rd, rd, RV_REG_T1, ctx); 1432 } 1433 if (!is64 && !aux->verifier_zext) 1434 emit_zextw(rd, rd, ctx); 1435 break; 1436 case BPF_ALU | BPF_SUB | BPF_K: 1437 case BPF_ALU64 | BPF_SUB | BPF_K: 1438 if (is_12b_int(-imm)) { 1439 emit_addi(rd, rd, -imm, ctx); 1440 } else { 1441 emit_imm(RV_REG_T1, imm, ctx); 1442 emit_sub(rd, rd, RV_REG_T1, ctx); 1443 } 1444 if (!is64 && !aux->verifier_zext) 1445 emit_zextw(rd, rd, ctx); 1446 break; 1447 case BPF_ALU | BPF_AND | BPF_K: 1448 case BPF_ALU64 | BPF_AND | BPF_K: 1449 if (is_12b_int(imm)) { 1450 emit_andi(rd, rd, imm, ctx); 1451 } else { 1452 emit_imm(RV_REG_T1, imm, ctx); 1453 emit_and(rd, rd, RV_REG_T1, ctx); 1454 } 1455 if (!is64 && !aux->verifier_zext) 1456 emit_zextw(rd, rd, ctx); 1457 break; 1458 case BPF_ALU | BPF_OR | BPF_K: 1459 case BPF_ALU64 | BPF_OR | BPF_K: 1460 if (is_12b_int(imm)) { 1461 emit(rv_ori(rd, rd, imm), ctx); 1462 } else { 1463 emit_imm(RV_REG_T1, imm, ctx); 1464 emit_or(rd, rd, RV_REG_T1, ctx); 1465 } 1466 if (!is64 && !aux->verifier_zext) 1467 emit_zextw(rd, rd, ctx); 1468 break; 1469 case BPF_ALU | BPF_XOR | BPF_K: 1470 case BPF_ALU64 | BPF_XOR | BPF_K: 1471 if (is_12b_int(imm)) { 1472 emit(rv_xori(rd, rd, imm), ctx); 1473 } else { 1474 emit_imm(RV_REG_T1, imm, ctx); 1475 emit_xor(rd, rd, RV_REG_T1, ctx); 1476 } 1477 if (!is64 && !aux->verifier_zext) 1478 emit_zextw(rd, rd, ctx); 1479 break; 1480 case BPF_ALU | BPF_MUL | BPF_K: 1481 case BPF_ALU64 | BPF_MUL | BPF_K: 1482 emit_imm(RV_REG_T1, imm, ctx); 1483 emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : 1484 rv_mulw(rd, rd, RV_REG_T1), ctx); 1485 if (!is64 && !aux->verifier_zext) 1486 emit_zextw(rd, rd, ctx); 1487 break; 1488 case BPF_ALU | BPF_DIV | BPF_K: 1489 case BPF_ALU64 | BPF_DIV | BPF_K: 1490 emit_imm(RV_REG_T1, imm, ctx); 1491 if (off) 1492 emit(is64 ? rv_div(rd, rd, RV_REG_T1) : 1493 rv_divw(rd, rd, RV_REG_T1), ctx); 1494 else 1495 emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : 1496 rv_divuw(rd, rd, RV_REG_T1), ctx); 1497 if (!is64 && !aux->verifier_zext) 1498 emit_zextw(rd, rd, ctx); 1499 break; 1500 case BPF_ALU | BPF_MOD | BPF_K: 1501 case BPF_ALU64 | BPF_MOD | BPF_K: 1502 emit_imm(RV_REG_T1, imm, ctx); 1503 if (off) 1504 emit(is64 ? rv_rem(rd, rd, RV_REG_T1) : 1505 rv_remw(rd, rd, RV_REG_T1), ctx); 1506 else 1507 emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : 1508 rv_remuw(rd, rd, RV_REG_T1), ctx); 1509 if (!is64 && !aux->verifier_zext) 1510 emit_zextw(rd, rd, ctx); 1511 break; 1512 case BPF_ALU | BPF_LSH | BPF_K: 1513 case BPF_ALU64 | BPF_LSH | BPF_K: 1514 emit_slli(rd, rd, imm, ctx); 1515 1516 if (!is64 && !aux->verifier_zext) 1517 emit_zextw(rd, rd, ctx); 1518 break; 1519 case BPF_ALU | BPF_RSH | BPF_K: 1520 case BPF_ALU64 | BPF_RSH | BPF_K: 1521 if (is64) 1522 emit_srli(rd, rd, imm, ctx); 1523 else 1524 emit(rv_srliw(rd, rd, imm), ctx); 1525 1526 if (!is64 && !aux->verifier_zext) 1527 emit_zextw(rd, rd, ctx); 1528 break; 1529 case BPF_ALU | BPF_ARSH | BPF_K: 1530 case BPF_ALU64 | BPF_ARSH | BPF_K: 1531 if (is64) 1532 emit_srai(rd, rd, imm, ctx); 1533 else 1534 emit(rv_sraiw(rd, rd, imm), ctx); 1535 1536 if (!is64 && !aux->verifier_zext) 1537 emit_zextw(rd, rd, ctx); 1538 break; 1539 1540 /* JUMP off */ 1541 case BPF_JMP | BPF_JA: 1542 case BPF_JMP32 | BPF_JA: 1543 if (BPF_CLASS(code) == BPF_JMP) 1544 rvoff = rv_offset(i, off, ctx); 1545 else 1546 rvoff = rv_offset(i, imm, ctx); 1547 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1548 if (ret) 1549 return ret; 1550 break; 1551 1552 /* IF (dst COND src) JUMP off */ 1553 case BPF_JMP | BPF_JEQ | BPF_X: 1554 case BPF_JMP32 | BPF_JEQ | BPF_X: 1555 case BPF_JMP | BPF_JGT | BPF_X: 1556 case BPF_JMP32 | BPF_JGT | BPF_X: 1557 case BPF_JMP | BPF_JLT | BPF_X: 1558 case BPF_JMP32 | BPF_JLT | BPF_X: 1559 case BPF_JMP | BPF_JGE | BPF_X: 1560 case BPF_JMP32 | BPF_JGE | BPF_X: 1561 case BPF_JMP | BPF_JLE | BPF_X: 1562 case BPF_JMP32 | BPF_JLE | BPF_X: 1563 case BPF_JMP | BPF_JNE | BPF_X: 1564 case BPF_JMP32 | BPF_JNE | BPF_X: 1565 case BPF_JMP | BPF_JSGT | BPF_X: 1566 case BPF_JMP32 | BPF_JSGT | BPF_X: 1567 case BPF_JMP | BPF_JSLT | BPF_X: 1568 case BPF_JMP32 | BPF_JSLT | BPF_X: 1569 case BPF_JMP | BPF_JSGE | BPF_X: 1570 case BPF_JMP32 | BPF_JSGE | BPF_X: 1571 case BPF_JMP | BPF_JSLE | BPF_X: 1572 case BPF_JMP32 | BPF_JSLE | BPF_X: 1573 case BPF_JMP | BPF_JSET | BPF_X: 1574 case BPF_JMP32 | BPF_JSET | BPF_X: 1575 rvoff = rv_offset(i, off, ctx); 1576 if (!is64) { 1577 s = ctx->ninsns; 1578 if (is_signed_bpf_cond(BPF_OP(code))) { 1579 emit_sextw_alt(&rs, RV_REG_T1, ctx); 1580 emit_sextw_alt(&rd, RV_REG_T2, ctx); 1581 } else { 1582 emit_zextw_alt(&rs, RV_REG_T1, ctx); 1583 emit_zextw_alt(&rd, RV_REG_T2, ctx); 1584 } 1585 e = ctx->ninsns; 1586 1587 /* Adjust for extra insns */ 1588 rvoff -= ninsns_rvoff(e - s); 1589 } 1590 1591 if (BPF_OP(code) == BPF_JSET) { 1592 /* Adjust for and */ 1593 rvoff -= 4; 1594 emit_and(RV_REG_T1, rd, rs, ctx); 1595 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1596 } else { 1597 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1598 } 1599 break; 1600 1601 /* IF (dst COND imm) JUMP off */ 1602 case BPF_JMP | BPF_JEQ | BPF_K: 1603 case BPF_JMP32 | BPF_JEQ | BPF_K: 1604 case BPF_JMP | BPF_JGT | BPF_K: 1605 case BPF_JMP32 | BPF_JGT | BPF_K: 1606 case BPF_JMP | BPF_JLT | BPF_K: 1607 case BPF_JMP32 | BPF_JLT | BPF_K: 1608 case BPF_JMP | BPF_JGE | BPF_K: 1609 case BPF_JMP32 | BPF_JGE | BPF_K: 1610 case BPF_JMP | BPF_JLE | BPF_K: 1611 case BPF_JMP32 | BPF_JLE | BPF_K: 1612 case BPF_JMP | BPF_JNE | BPF_K: 1613 case BPF_JMP32 | BPF_JNE | BPF_K: 1614 case BPF_JMP | BPF_JSGT | BPF_K: 1615 case BPF_JMP32 | BPF_JSGT | BPF_K: 1616 case BPF_JMP | BPF_JSLT | BPF_K: 1617 case BPF_JMP32 | BPF_JSLT | BPF_K: 1618 case BPF_JMP | BPF_JSGE | BPF_K: 1619 case BPF_JMP32 | BPF_JSGE | BPF_K: 1620 case BPF_JMP | BPF_JSLE | BPF_K: 1621 case BPF_JMP32 | BPF_JSLE | BPF_K: 1622 rvoff = rv_offset(i, off, ctx); 1623 s = ctx->ninsns; 1624 if (imm) 1625 emit_imm(RV_REG_T1, imm, ctx); 1626 rs = imm ? RV_REG_T1 : RV_REG_ZERO; 1627 if (!is64) { 1628 if (is_signed_bpf_cond(BPF_OP(code))) { 1629 emit_sextw_alt(&rd, RV_REG_T2, ctx); 1630 /* rs has been sign extended */ 1631 } else { 1632 emit_zextw_alt(&rd, RV_REG_T2, ctx); 1633 if (imm) 1634 emit_zextw(rs, rs, ctx); 1635 } 1636 } 1637 e = ctx->ninsns; 1638 1639 /* Adjust for extra insns */ 1640 rvoff -= ninsns_rvoff(e - s); 1641 emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); 1642 break; 1643 1644 case BPF_JMP | BPF_JSET | BPF_K: 1645 case BPF_JMP32 | BPF_JSET | BPF_K: 1646 rvoff = rv_offset(i, off, ctx); 1647 s = ctx->ninsns; 1648 if (is_12b_int(imm)) { 1649 emit_andi(RV_REG_T1, rd, imm, ctx); 1650 } else { 1651 emit_imm(RV_REG_T1, imm, ctx); 1652 emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); 1653 } 1654 /* For jset32, we should clear the upper 32 bits of t1, but 1655 * sign-extension is sufficient here and saves one instruction, 1656 * as t1 is used only in comparison against zero. 1657 */ 1658 if (!is64 && imm < 0) 1659 emit_sextw(RV_REG_T1, RV_REG_T1, ctx); 1660 e = ctx->ninsns; 1661 rvoff -= ninsns_rvoff(e - s); 1662 emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); 1663 break; 1664 1665 /* function call */ 1666 case BPF_JMP | BPF_CALL: 1667 { 1668 bool fixed_addr; 1669 u64 addr; 1670 1671 /* Inline calls to bpf_get_smp_processor_id() 1672 * 1673 * RV_REG_TP holds the address of the current CPU's task_struct and thread_info is 1674 * at offset 0 in task_struct. 1675 * Load cpu from thread_info: 1676 * Set R0 to ((struct thread_info *)(RV_REG_TP))->cpu 1677 * 1678 * This replicates the implementation of raw_smp_processor_id() on RISCV 1679 */ 1680 if (insn->src_reg == 0 && insn->imm == BPF_FUNC_get_smp_processor_id) { 1681 /* Load current CPU number in R0 */ 1682 emit_ld(bpf_to_rv_reg(BPF_REG_0, ctx), offsetof(struct thread_info, cpu), 1683 RV_REG_TP, ctx); 1684 break; 1685 } 1686 1687 mark_call(ctx); 1688 ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, 1689 &addr, &fixed_addr); 1690 if (ret < 0) 1691 return ret; 1692 1693 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) { 1694 const struct btf_func_model *fm; 1695 int idx; 1696 1697 fm = bpf_jit_find_kfunc_model(ctx->prog, insn); 1698 if (!fm) 1699 return -EINVAL; 1700 1701 for (idx = 0; idx < fm->nr_args; idx++) { 1702 u8 reg = bpf_to_rv_reg(BPF_REG_1 + idx, ctx); 1703 1704 if (fm->arg_size[idx] == sizeof(int)) 1705 emit_sextw(reg, reg, ctx); 1706 } 1707 } 1708 1709 ret = emit_call(addr, fixed_addr, ctx); 1710 if (ret) 1711 return ret; 1712 1713 if (insn->src_reg != BPF_PSEUDO_CALL) 1714 emit_mv(bpf_to_rv_reg(BPF_REG_0, ctx), RV_REG_A0, ctx); 1715 break; 1716 } 1717 /* tail call */ 1718 case BPF_JMP | BPF_TAIL_CALL: 1719 if (emit_bpf_tail_call(i, ctx)) 1720 return -1; 1721 break; 1722 1723 /* function return */ 1724 case BPF_JMP | BPF_EXIT: 1725 if (i == ctx->prog->len - 1) 1726 break; 1727 1728 rvoff = epilogue_offset(ctx); 1729 ret = emit_jump_and_link(RV_REG_ZERO, rvoff, true, ctx); 1730 if (ret) 1731 return ret; 1732 break; 1733 1734 /* dst = imm64 */ 1735 case BPF_LD | BPF_IMM | BPF_DW: 1736 { 1737 struct bpf_insn insn1 = insn[1]; 1738 u64 imm64; 1739 1740 imm64 = (u64)insn1.imm << 32 | (u32)imm; 1741 if (bpf_pseudo_func(insn)) { 1742 /* fixed-length insns for extra jit pass */ 1743 ret = emit_addr(rd, imm64, extra_pass, ctx); 1744 if (ret) 1745 return ret; 1746 } else { 1747 emit_imm(rd, imm64, ctx); 1748 } 1749 1750 return 1; 1751 } 1752 1753 /* LDX: dst = *(unsigned size *)(src + off) */ 1754 case BPF_LDX | BPF_MEM | BPF_B: 1755 case BPF_LDX | BPF_MEM | BPF_H: 1756 case BPF_LDX | BPF_MEM | BPF_W: 1757 case BPF_LDX | BPF_MEM | BPF_DW: 1758 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1759 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1760 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1761 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1762 /* LDSX: dst = *(signed size *)(src + off) */ 1763 case BPF_LDX | BPF_MEMSX | BPF_B: 1764 case BPF_LDX | BPF_MEMSX | BPF_H: 1765 case BPF_LDX | BPF_MEMSX | BPF_W: 1766 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1767 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1768 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1769 /* LDX | PROBE_MEM32: dst = *(unsigned size *)(src + RV_REG_ARENA + off) */ 1770 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1771 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1772 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1773 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1774 { 1775 bool sign_ext; 1776 1777 sign_ext = BPF_MODE(insn->code) == BPF_MEMSX || 1778 BPF_MODE(insn->code) == BPF_PROBE_MEMSX; 1779 1780 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1781 emit_add(RV_REG_T2, rs, RV_REG_ARENA, ctx); 1782 rs = RV_REG_T2; 1783 } 1784 1785 emit_ldx(rd, off, rs, BPF_SIZE(code), sign_ext, ctx); 1786 1787 ret = add_exception_handler(insn, rd, ctx); 1788 if (ret) 1789 return ret; 1790 1791 if (BPF_SIZE(code) != BPF_DW && insn_is_zext(&insn[1])) 1792 return 1; 1793 break; 1794 } 1795 1796 /* speculation barrier */ 1797 case BPF_ST | BPF_NOSPEC: 1798 break; 1799 1800 /* ST: *(size *)(dst + off) = imm */ 1801 case BPF_ST | BPF_MEM | BPF_B: 1802 case BPF_ST | BPF_MEM | BPF_H: 1803 case BPF_ST | BPF_MEM | BPF_W: 1804 case BPF_ST | BPF_MEM | BPF_DW: 1805 /* ST | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = imm */ 1806 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1807 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1808 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1809 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1810 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1811 emit_add(RV_REG_T3, rd, RV_REG_ARENA, ctx); 1812 rd = RV_REG_T3; 1813 } 1814 1815 emit_st(rd, off, imm, BPF_SIZE(code), ctx); 1816 1817 ret = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx); 1818 if (ret) 1819 return ret; 1820 break; 1821 1822 /* STX: *(size *)(dst + off) = src */ 1823 case BPF_STX | BPF_MEM | BPF_B: 1824 case BPF_STX | BPF_MEM | BPF_H: 1825 case BPF_STX | BPF_MEM | BPF_W: 1826 case BPF_STX | BPF_MEM | BPF_DW: 1827 /* STX | PROBE_MEM32: *(size *)(dst + RV_REG_ARENA + off) = src */ 1828 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1829 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1830 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1831 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1832 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32) { 1833 emit_add(RV_REG_T2, rd, RV_REG_ARENA, ctx); 1834 rd = RV_REG_T2; 1835 } 1836 1837 emit_stx(rd, off, rs, BPF_SIZE(code), ctx); 1838 1839 ret = add_exception_handler(insn, REG_DONT_CLEAR_MARKER, ctx); 1840 if (ret) 1841 return ret; 1842 break; 1843 1844 case BPF_STX | BPF_ATOMIC | BPF_B: 1845 case BPF_STX | BPF_ATOMIC | BPF_H: 1846 case BPF_STX | BPF_ATOMIC | BPF_W: 1847 case BPF_STX | BPF_ATOMIC | BPF_DW: 1848 if (bpf_atomic_is_load_store(insn)) 1849 ret = emit_atomic_ld_st(rd, rs, insn, ctx); 1850 else 1851 ret = emit_atomic_rmw(rd, rs, insn, ctx); 1852 if (ret) 1853 return ret; 1854 break; 1855 1856 default: 1857 pr_err("bpf-jit: unknown opcode %02x\n", code); 1858 return -EINVAL; 1859 } 1860 1861 return 0; 1862 } 1863 1864 void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog) 1865 { 1866 int i, stack_adjust = 0, store_offset, bpf_stack_adjust; 1867 1868 bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, STACK_ALIGN); 1869 if (bpf_stack_adjust) 1870 mark_fp(ctx); 1871 1872 if (seen_reg(RV_REG_RA, ctx)) 1873 stack_adjust += 8; 1874 stack_adjust += 8; /* RV_REG_FP */ 1875 if (seen_reg(RV_REG_S1, ctx)) 1876 stack_adjust += 8; 1877 if (seen_reg(RV_REG_S2, ctx)) 1878 stack_adjust += 8; 1879 if (seen_reg(RV_REG_S3, ctx)) 1880 stack_adjust += 8; 1881 if (seen_reg(RV_REG_S4, ctx)) 1882 stack_adjust += 8; 1883 if (seen_reg(RV_REG_S5, ctx)) 1884 stack_adjust += 8; 1885 if (seen_reg(RV_REG_S6, ctx)) 1886 stack_adjust += 8; 1887 if (ctx->arena_vm_start) 1888 stack_adjust += 8; 1889 1890 stack_adjust = round_up(stack_adjust, STACK_ALIGN); 1891 stack_adjust += bpf_stack_adjust; 1892 1893 store_offset = stack_adjust - 8; 1894 1895 /* emit kcfi type preamble immediately before the first insn */ 1896 emit_kcfi(is_subprog ? cfi_bpf_subprog_hash : cfi_bpf_hash, ctx); 1897 1898 /* nops reserved for auipc+jalr pair */ 1899 for (i = 0; i < RV_FENTRY_NINSNS; i++) 1900 emit(rv_nop(), ctx); 1901 1902 /* First instruction is always setting the tail-call-counter 1903 * (TCC) register. This instruction is skipped for tail calls. 1904 * Force using a 4-byte (non-compressed) instruction. 1905 */ 1906 emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); 1907 1908 emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); 1909 1910 if (seen_reg(RV_REG_RA, ctx)) { 1911 emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); 1912 store_offset -= 8; 1913 } 1914 emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); 1915 store_offset -= 8; 1916 if (seen_reg(RV_REG_S1, ctx)) { 1917 emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); 1918 store_offset -= 8; 1919 } 1920 if (seen_reg(RV_REG_S2, ctx)) { 1921 emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); 1922 store_offset -= 8; 1923 } 1924 if (seen_reg(RV_REG_S3, ctx)) { 1925 emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); 1926 store_offset -= 8; 1927 } 1928 if (seen_reg(RV_REG_S4, ctx)) { 1929 emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); 1930 store_offset -= 8; 1931 } 1932 if (seen_reg(RV_REG_S5, ctx)) { 1933 emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); 1934 store_offset -= 8; 1935 } 1936 if (seen_reg(RV_REG_S6, ctx)) { 1937 emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); 1938 store_offset -= 8; 1939 } 1940 if (ctx->arena_vm_start) { 1941 emit_sd(RV_REG_SP, store_offset, RV_REG_ARENA, ctx); 1942 store_offset -= 8; 1943 } 1944 1945 emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); 1946 1947 if (bpf_stack_adjust) 1948 emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); 1949 1950 /* Program contains calls and tail calls, so RV_REG_TCC need 1951 * to be saved across calls. 1952 */ 1953 if (seen_tail_call(ctx) && seen_call(ctx)) 1954 emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); 1955 1956 ctx->stack_size = stack_adjust; 1957 1958 if (ctx->arena_vm_start) 1959 emit_imm(RV_REG_ARENA, ctx->arena_vm_start, ctx); 1960 } 1961 1962 void bpf_jit_build_epilogue(struct rv_jit_context *ctx) 1963 { 1964 __build_epilogue(false, ctx); 1965 } 1966 1967 bool bpf_jit_supports_kfunc_call(void) 1968 { 1969 return true; 1970 } 1971 1972 bool bpf_jit_supports_ptr_xchg(void) 1973 { 1974 return true; 1975 } 1976 1977 bool bpf_jit_supports_arena(void) 1978 { 1979 return true; 1980 } 1981 1982 bool bpf_jit_supports_percpu_insn(void) 1983 { 1984 return true; 1985 } 1986 1987 bool bpf_jit_inlines_helper_call(s32 imm) 1988 { 1989 switch (imm) { 1990 case BPF_FUNC_get_smp_processor_id: 1991 return true; 1992 default: 1993 return false; 1994 } 1995 } 1996