1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common functionality for RV32 and RV64 BPF JIT compilers 4 * 5 * Copyright (c) 2019 Björn Töpel <bjorn.topel@gmail.com> 6 * 7 */ 8 9 #ifndef _BPF_JIT_H 10 #define _BPF_JIT_H 11 12 #include <linux/bpf.h> 13 #include <linux/filter.h> 14 #include <asm/cacheflush.h> 15 16 static inline bool rvc_enabled(void) 17 { 18 return IS_ENABLED(CONFIG_RISCV_ISA_C); 19 } 20 21 static inline bool rvzba_enabled(void) 22 { 23 return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA); 24 } 25 26 static inline bool rvzbb_enabled(void) 27 { 28 return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); 29 } 30 31 enum { 32 RV_REG_ZERO = 0, /* The constant value 0 */ 33 RV_REG_RA = 1, /* Return address */ 34 RV_REG_SP = 2, /* Stack pointer */ 35 RV_REG_GP = 3, /* Global pointer */ 36 RV_REG_TP = 4, /* Thread pointer */ 37 RV_REG_T0 = 5, /* Temporaries */ 38 RV_REG_T1 = 6, 39 RV_REG_T2 = 7, 40 RV_REG_FP = 8, /* Saved register/frame pointer */ 41 RV_REG_S1 = 9, /* Saved register */ 42 RV_REG_A0 = 10, /* Function argument/return values */ 43 RV_REG_A1 = 11, /* Function arguments */ 44 RV_REG_A2 = 12, 45 RV_REG_A3 = 13, 46 RV_REG_A4 = 14, 47 RV_REG_A5 = 15, 48 RV_REG_A6 = 16, 49 RV_REG_A7 = 17, 50 RV_REG_S2 = 18, /* Saved registers */ 51 RV_REG_S3 = 19, 52 RV_REG_S4 = 20, 53 RV_REG_S5 = 21, 54 RV_REG_S6 = 22, 55 RV_REG_S7 = 23, 56 RV_REG_S8 = 24, 57 RV_REG_S9 = 25, 58 RV_REG_S10 = 26, 59 RV_REG_S11 = 27, 60 RV_REG_T3 = 28, /* Temporaries */ 61 RV_REG_T4 = 29, 62 RV_REG_T5 = 30, 63 RV_REG_T6 = 31, 64 }; 65 66 static inline bool is_creg(u8 reg) 67 { 68 return (1 << reg) & (BIT(RV_REG_FP) | 69 BIT(RV_REG_S1) | 70 BIT(RV_REG_A0) | 71 BIT(RV_REG_A1) | 72 BIT(RV_REG_A2) | 73 BIT(RV_REG_A3) | 74 BIT(RV_REG_A4) | 75 BIT(RV_REG_A5)); 76 } 77 78 struct rv_jit_context { 79 struct bpf_prog *prog; 80 u16 *insns; /* RV insns */ 81 u16 *ro_insns; 82 int ninsns; 83 int prologue_len; 84 int epilogue_offset; 85 int *offset; /* BPF to RV */ 86 int nexentries; 87 unsigned long flags; 88 int stack_size; 89 u64 arena_vm_start; 90 u64 user_vm_start; 91 }; 92 93 /* Convert from ninsns to bytes. */ 94 static inline int ninsns_rvoff(int ninsns) 95 { 96 return ninsns << 1; 97 } 98 99 struct rv_jit_data { 100 struct bpf_binary_header *header; 101 struct bpf_binary_header *ro_header; 102 u8 *image; 103 u8 *ro_image; 104 struct rv_jit_context ctx; 105 }; 106 107 static inline void bpf_fill_ill_insns(void *area, unsigned int size) 108 { 109 memset(area, 0, size); 110 } 111 112 static inline void bpf_flush_icache(void *start, void *end) 113 { 114 flush_icache_range((unsigned long)start, (unsigned long)end); 115 } 116 117 /* Emit a 4-byte riscv instruction. */ 118 static inline void emit(const u32 insn, struct rv_jit_context *ctx) 119 { 120 if (ctx->insns) { 121 ctx->insns[ctx->ninsns] = insn; 122 ctx->insns[ctx->ninsns + 1] = (insn >> 16); 123 } 124 125 ctx->ninsns += 2; 126 } 127 128 /* Emit a 2-byte riscv compressed instruction. */ 129 static inline void emitc(const u16 insn, struct rv_jit_context *ctx) 130 { 131 BUILD_BUG_ON(!rvc_enabled()); 132 133 if (ctx->insns) 134 ctx->insns[ctx->ninsns] = insn; 135 136 ctx->ninsns++; 137 } 138 139 static inline int epilogue_offset(struct rv_jit_context *ctx) 140 { 141 int to = ctx->epilogue_offset, from = ctx->ninsns; 142 143 return ninsns_rvoff(to - from); 144 } 145 146 /* Return -1 or inverted cond. */ 147 static inline int invert_bpf_cond(u8 cond) 148 { 149 switch (cond) { 150 case BPF_JEQ: 151 return BPF_JNE; 152 case BPF_JGT: 153 return BPF_JLE; 154 case BPF_JLT: 155 return BPF_JGE; 156 case BPF_JGE: 157 return BPF_JLT; 158 case BPF_JLE: 159 return BPF_JGT; 160 case BPF_JNE: 161 return BPF_JEQ; 162 case BPF_JSGT: 163 return BPF_JSLE; 164 case BPF_JSLT: 165 return BPF_JSGE; 166 case BPF_JSGE: 167 return BPF_JSLT; 168 case BPF_JSLE: 169 return BPF_JSGT; 170 } 171 return -1; 172 } 173 174 static inline bool is_6b_int(long val) 175 { 176 return -(1L << 5) <= val && val < (1L << 5); 177 } 178 179 static inline bool is_7b_uint(unsigned long val) 180 { 181 return val < (1UL << 7); 182 } 183 184 static inline bool is_8b_uint(unsigned long val) 185 { 186 return val < (1UL << 8); 187 } 188 189 static inline bool is_9b_uint(unsigned long val) 190 { 191 return val < (1UL << 9); 192 } 193 194 static inline bool is_10b_int(long val) 195 { 196 return -(1L << 9) <= val && val < (1L << 9); 197 } 198 199 static inline bool is_10b_uint(unsigned long val) 200 { 201 return val < (1UL << 10); 202 } 203 204 static inline bool is_12b_int(long val) 205 { 206 return -(1L << 11) <= val && val < (1L << 11); 207 } 208 209 static inline int is_12b_check(int off, int insn) 210 { 211 if (!is_12b_int(off)) { 212 pr_err("bpf-jit: insn=%d 12b < offset=%d not supported yet!\n", 213 insn, (int)off); 214 return -1; 215 } 216 return 0; 217 } 218 219 static inline bool is_13b_int(long val) 220 { 221 return -(1L << 12) <= val && val < (1L << 12); 222 } 223 224 static inline bool is_21b_int(long val) 225 { 226 return -(1L << 20) <= val && val < (1L << 20); 227 } 228 229 static inline int rv_offset(int insn, int off, struct rv_jit_context *ctx) 230 { 231 int from, to; 232 233 off++; /* BPF branch is from PC+1, RV is from PC */ 234 from = (insn > 0) ? ctx->offset[insn - 1] : ctx->prologue_len; 235 to = (insn + off > 0) ? ctx->offset[insn + off - 1] : ctx->prologue_len; 236 return ninsns_rvoff(to - from); 237 } 238 239 /* Instruction formats. */ 240 241 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, 242 u8 opcode) 243 { 244 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | 245 (rd << 7) | opcode; 246 } 247 248 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) 249 { 250 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | 251 opcode; 252 } 253 254 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) 255 { 256 u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f; 257 258 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | 259 (imm4_0 << 7) | opcode; 260 } 261 262 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) 263 { 264 u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4); 265 u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10); 266 267 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | 268 (imm4_1 << 7) | opcode; 269 } 270 271 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) 272 { 273 return (imm31_12 << 12) | (rd << 7) | opcode; 274 } 275 276 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode) 277 { 278 u32 imm; 279 280 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) | 281 ((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11); 282 283 return (imm << 12) | (rd << 7) | opcode; 284 } 285 286 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, 287 u8 funct3, u8 rd, u8 opcode) 288 { 289 u8 funct7 = (funct5 << 2) | (aq << 1) | rl; 290 291 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); 292 } 293 294 /* RISC-V compressed instruction formats. */ 295 296 static inline u16 rv_cr_insn(u8 funct4, u8 rd, u8 rs2, u8 op) 297 { 298 return (funct4 << 12) | (rd << 7) | (rs2 << 2) | op; 299 } 300 301 static inline u16 rv_ci_insn(u8 funct3, u32 imm6, u8 rd, u8 op) 302 { 303 u32 imm; 304 305 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); 306 return (funct3 << 13) | (rd << 7) | op | imm; 307 } 308 309 static inline u16 rv_css_insn(u8 funct3, u32 uimm, u8 rs2, u8 op) 310 { 311 return (funct3 << 13) | (uimm << 7) | (rs2 << 2) | op; 312 } 313 314 static inline u16 rv_ciw_insn(u8 funct3, u32 uimm, u8 rd, u8 op) 315 { 316 return (funct3 << 13) | (uimm << 5) | ((rd & 0x7) << 2) | op; 317 } 318 319 static inline u16 rv_cl_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rd, 320 u8 op) 321 { 322 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) | 323 (imm_lo << 5) | ((rd & 0x7) << 2) | op; 324 } 325 326 static inline u16 rv_cs_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rs2, 327 u8 op) 328 { 329 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) | 330 (imm_lo << 5) | ((rs2 & 0x7) << 2) | op; 331 } 332 333 static inline u16 rv_ca_insn(u8 funct6, u8 rd, u8 funct2, u8 rs2, u8 op) 334 { 335 return (funct6 << 10) | ((rd & 0x7) << 7) | (funct2 << 5) | 336 ((rs2 & 0x7) << 2) | op; 337 } 338 339 static inline u16 rv_cb_insn(u8 funct3, u32 imm6, u8 funct2, u8 rd, u8 op) 340 { 341 u32 imm; 342 343 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2); 344 return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm; 345 } 346 347 /* Instructions shared by both RV32 and RV64. */ 348 349 static inline u32 rv_addi(u8 rd, u8 rs1, u16 imm11_0) 350 { 351 return rv_i_insn(imm11_0, rs1, 0, rd, 0x13); 352 } 353 354 static inline u32 rv_andi(u8 rd, u8 rs1, u16 imm11_0) 355 { 356 return rv_i_insn(imm11_0, rs1, 7, rd, 0x13); 357 } 358 359 static inline u32 rv_ori(u8 rd, u8 rs1, u16 imm11_0) 360 { 361 return rv_i_insn(imm11_0, rs1, 6, rd, 0x13); 362 } 363 364 static inline u32 rv_xori(u8 rd, u8 rs1, u16 imm11_0) 365 { 366 return rv_i_insn(imm11_0, rs1, 4, rd, 0x13); 367 } 368 369 static inline u32 rv_slli(u8 rd, u8 rs1, u16 imm11_0) 370 { 371 return rv_i_insn(imm11_0, rs1, 1, rd, 0x13); 372 } 373 374 static inline u32 rv_srli(u8 rd, u8 rs1, u16 imm11_0) 375 { 376 return rv_i_insn(imm11_0, rs1, 5, rd, 0x13); 377 } 378 379 static inline u32 rv_srai(u8 rd, u8 rs1, u16 imm11_0) 380 { 381 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13); 382 } 383 384 static inline u32 rv_lui(u8 rd, u32 imm31_12) 385 { 386 return rv_u_insn(imm31_12, rd, 0x37); 387 } 388 389 static inline u32 rv_auipc(u8 rd, u32 imm31_12) 390 { 391 return rv_u_insn(imm31_12, rd, 0x17); 392 } 393 394 static inline u32 rv_add(u8 rd, u8 rs1, u8 rs2) 395 { 396 return rv_r_insn(0, rs2, rs1, 0, rd, 0x33); 397 } 398 399 static inline u32 rv_sub(u8 rd, u8 rs1, u8 rs2) 400 { 401 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33); 402 } 403 404 static inline u32 rv_sltu(u8 rd, u8 rs1, u8 rs2) 405 { 406 return rv_r_insn(0, rs2, rs1, 3, rd, 0x33); 407 } 408 409 static inline u32 rv_and(u8 rd, u8 rs1, u8 rs2) 410 { 411 return rv_r_insn(0, rs2, rs1, 7, rd, 0x33); 412 } 413 414 static inline u32 rv_or(u8 rd, u8 rs1, u8 rs2) 415 { 416 return rv_r_insn(0, rs2, rs1, 6, rd, 0x33); 417 } 418 419 static inline u32 rv_xor(u8 rd, u8 rs1, u8 rs2) 420 { 421 return rv_r_insn(0, rs2, rs1, 4, rd, 0x33); 422 } 423 424 static inline u32 rv_sll(u8 rd, u8 rs1, u8 rs2) 425 { 426 return rv_r_insn(0, rs2, rs1, 1, rd, 0x33); 427 } 428 429 static inline u32 rv_srl(u8 rd, u8 rs1, u8 rs2) 430 { 431 return rv_r_insn(0, rs2, rs1, 5, rd, 0x33); 432 } 433 434 static inline u32 rv_sra(u8 rd, u8 rs1, u8 rs2) 435 { 436 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33); 437 } 438 439 static inline u32 rv_mul(u8 rd, u8 rs1, u8 rs2) 440 { 441 return rv_r_insn(1, rs2, rs1, 0, rd, 0x33); 442 } 443 444 static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2) 445 { 446 return rv_r_insn(1, rs2, rs1, 3, rd, 0x33); 447 } 448 449 static inline u32 rv_div(u8 rd, u8 rs1, u8 rs2) 450 { 451 return rv_r_insn(1, rs2, rs1, 4, rd, 0x33); 452 } 453 454 static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2) 455 { 456 return rv_r_insn(1, rs2, rs1, 5, rd, 0x33); 457 } 458 459 static inline u32 rv_rem(u8 rd, u8 rs1, u8 rs2) 460 { 461 return rv_r_insn(1, rs2, rs1, 6, rd, 0x33); 462 } 463 464 static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2) 465 { 466 return rv_r_insn(1, rs2, rs1, 7, rd, 0x33); 467 } 468 469 static inline u32 rv_jal(u8 rd, u32 imm20_1) 470 { 471 return rv_j_insn(imm20_1, rd, 0x6f); 472 } 473 474 static inline u32 rv_jalr(u8 rd, u8 rs1, u16 imm11_0) 475 { 476 return rv_i_insn(imm11_0, rs1, 0, rd, 0x67); 477 } 478 479 static inline u32 rv_beq(u8 rs1, u8 rs2, u16 imm12_1) 480 { 481 return rv_b_insn(imm12_1, rs2, rs1, 0, 0x63); 482 } 483 484 static inline u32 rv_bne(u8 rs1, u8 rs2, u16 imm12_1) 485 { 486 return rv_b_insn(imm12_1, rs2, rs1, 1, 0x63); 487 } 488 489 static inline u32 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1) 490 { 491 return rv_b_insn(imm12_1, rs2, rs1, 6, 0x63); 492 } 493 494 static inline u32 rv_bgtu(u8 rs1, u8 rs2, u16 imm12_1) 495 { 496 return rv_bltu(rs2, rs1, imm12_1); 497 } 498 499 static inline u32 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1) 500 { 501 return rv_b_insn(imm12_1, rs2, rs1, 7, 0x63); 502 } 503 504 static inline u32 rv_bleu(u8 rs1, u8 rs2, u16 imm12_1) 505 { 506 return rv_bgeu(rs2, rs1, imm12_1); 507 } 508 509 static inline u32 rv_blt(u8 rs1, u8 rs2, u16 imm12_1) 510 { 511 return rv_b_insn(imm12_1, rs2, rs1, 4, 0x63); 512 } 513 514 static inline u32 rv_bgt(u8 rs1, u8 rs2, u16 imm12_1) 515 { 516 return rv_blt(rs2, rs1, imm12_1); 517 } 518 519 static inline u32 rv_bge(u8 rs1, u8 rs2, u16 imm12_1) 520 { 521 return rv_b_insn(imm12_1, rs2, rs1, 5, 0x63); 522 } 523 524 static inline u32 rv_ble(u8 rs1, u8 rs2, u16 imm12_1) 525 { 526 return rv_bge(rs2, rs1, imm12_1); 527 } 528 529 static inline u32 rv_lb(u8 rd, u16 imm11_0, u8 rs1) 530 { 531 return rv_i_insn(imm11_0, rs1, 0, rd, 0x03); 532 } 533 534 static inline u32 rv_lh(u8 rd, u16 imm11_0, u8 rs1) 535 { 536 return rv_i_insn(imm11_0, rs1, 1, rd, 0x03); 537 } 538 539 static inline u32 rv_lw(u8 rd, u16 imm11_0, u8 rs1) 540 { 541 return rv_i_insn(imm11_0, rs1, 2, rd, 0x03); 542 } 543 544 static inline u32 rv_lbu(u8 rd, u16 imm11_0, u8 rs1) 545 { 546 return rv_i_insn(imm11_0, rs1, 4, rd, 0x03); 547 } 548 549 static inline u32 rv_lhu(u8 rd, u16 imm11_0, u8 rs1) 550 { 551 return rv_i_insn(imm11_0, rs1, 5, rd, 0x03); 552 } 553 554 static inline u32 rv_sb(u8 rs1, u16 imm11_0, u8 rs2) 555 { 556 return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23); 557 } 558 559 static inline u32 rv_sh(u8 rs1, u16 imm11_0, u8 rs2) 560 { 561 return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23); 562 } 563 564 static inline u32 rv_sw(u8 rs1, u16 imm11_0, u8 rs2) 565 { 566 return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23); 567 } 568 569 static inline u32 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 570 { 571 return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f); 572 } 573 574 static inline u32 rv_amoand_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 575 { 576 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 2, rd, 0x2f); 577 } 578 579 static inline u32 rv_amoor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 580 { 581 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 2, rd, 0x2f); 582 } 583 584 static inline u32 rv_amoxor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 585 { 586 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 2, rd, 0x2f); 587 } 588 589 static inline u32 rv_amoswap_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 590 { 591 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 2, rd, 0x2f); 592 } 593 594 static inline u32 rv_lr_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 595 { 596 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 2, rd, 0x2f); 597 } 598 599 static inline u32 rv_sc_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 600 { 601 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 2, rd, 0x2f); 602 } 603 604 static inline u32 rv_fence(u8 pred, u8 succ) 605 { 606 u16 imm11_0 = pred << 4 | succ; 607 608 return rv_i_insn(imm11_0, 0, 0, 0, 0xf); 609 } 610 611 static inline u32 rv_nop(void) 612 { 613 return rv_i_insn(0, 0, 0, 0, 0x13); 614 } 615 616 /* RVC instructions. */ 617 618 static inline u16 rvc_addi4spn(u8 rd, u32 imm10) 619 { 620 u32 imm; 621 622 imm = ((imm10 & 0x30) << 2) | ((imm10 & 0x3c0) >> 4) | 623 ((imm10 & 0x4) >> 1) | ((imm10 & 0x8) >> 3); 624 return rv_ciw_insn(0x0, imm, rd, 0x0); 625 } 626 627 static inline u16 rvc_lw(u8 rd, u32 imm7, u8 rs1) 628 { 629 u32 imm_hi, imm_lo; 630 631 imm_hi = (imm7 & 0x38) >> 3; 632 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6); 633 return rv_cl_insn(0x2, imm_hi, rs1, imm_lo, rd, 0x0); 634 } 635 636 static inline u16 rvc_sw(u8 rs1, u32 imm7, u8 rs2) 637 { 638 u32 imm_hi, imm_lo; 639 640 imm_hi = (imm7 & 0x38) >> 3; 641 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6); 642 return rv_cs_insn(0x6, imm_hi, rs1, imm_lo, rs2, 0x0); 643 } 644 645 static inline u16 rvc_addi(u8 rd, u32 imm6) 646 { 647 return rv_ci_insn(0, imm6, rd, 0x1); 648 } 649 650 static inline u16 rvc_li(u8 rd, u32 imm6) 651 { 652 return rv_ci_insn(0x2, imm6, rd, 0x1); 653 } 654 655 static inline u16 rvc_addi16sp(u32 imm10) 656 { 657 u32 imm; 658 659 imm = ((imm10 & 0x200) >> 4) | (imm10 & 0x10) | ((imm10 & 0x40) >> 3) | 660 ((imm10 & 0x180) >> 6) | ((imm10 & 0x20) >> 5); 661 return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1); 662 } 663 664 static inline u16 rvc_lui(u8 rd, u32 imm6) 665 { 666 return rv_ci_insn(0x3, imm6, rd, 0x1); 667 } 668 669 static inline u16 rvc_srli(u8 rd, u32 imm6) 670 { 671 return rv_cb_insn(0x4, imm6, 0, rd, 0x1); 672 } 673 674 static inline u16 rvc_srai(u8 rd, u32 imm6) 675 { 676 return rv_cb_insn(0x4, imm6, 0x1, rd, 0x1); 677 } 678 679 static inline u16 rvc_andi(u8 rd, u32 imm6) 680 { 681 return rv_cb_insn(0x4, imm6, 0x2, rd, 0x1); 682 } 683 684 static inline u16 rvc_sub(u8 rd, u8 rs) 685 { 686 return rv_ca_insn(0x23, rd, 0, rs, 0x1); 687 } 688 689 static inline u16 rvc_xor(u8 rd, u8 rs) 690 { 691 return rv_ca_insn(0x23, rd, 0x1, rs, 0x1); 692 } 693 694 static inline u16 rvc_or(u8 rd, u8 rs) 695 { 696 return rv_ca_insn(0x23, rd, 0x2, rs, 0x1); 697 } 698 699 static inline u16 rvc_and(u8 rd, u8 rs) 700 { 701 return rv_ca_insn(0x23, rd, 0x3, rs, 0x1); 702 } 703 704 static inline u16 rvc_slli(u8 rd, u32 imm6) 705 { 706 return rv_ci_insn(0, imm6, rd, 0x2); 707 } 708 709 static inline u16 rvc_lwsp(u8 rd, u32 imm8) 710 { 711 u32 imm; 712 713 imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c); 714 return rv_ci_insn(0x2, imm, rd, 0x2); 715 } 716 717 static inline u16 rvc_jr(u8 rs1) 718 { 719 return rv_cr_insn(0x8, rs1, RV_REG_ZERO, 0x2); 720 } 721 722 static inline u16 rvc_mv(u8 rd, u8 rs) 723 { 724 return rv_cr_insn(0x8, rd, rs, 0x2); 725 } 726 727 static inline u16 rvc_jalr(u8 rs1) 728 { 729 return rv_cr_insn(0x9, rs1, RV_REG_ZERO, 0x2); 730 } 731 732 static inline u16 rvc_add(u8 rd, u8 rs) 733 { 734 return rv_cr_insn(0x9, rd, rs, 0x2); 735 } 736 737 static inline u16 rvc_swsp(u32 imm8, u8 rs2) 738 { 739 u32 imm; 740 741 imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6); 742 return rv_css_insn(0x6, imm, rs2, 0x2); 743 } 744 745 /* RVZBB instructions. */ 746 static inline u32 rvzbb_sextb(u8 rd, u8 rs1) 747 { 748 return rv_i_insn(0x604, rs1, 1, rd, 0x13); 749 } 750 751 static inline u32 rvzbb_sexth(u8 rd, u8 rs1) 752 { 753 return rv_i_insn(0x605, rs1, 1, rd, 0x13); 754 } 755 756 static inline u32 rvzbb_zexth(u8 rd, u8 rs) 757 { 758 if (IS_ENABLED(CONFIG_64BIT)) 759 return rv_i_insn(0x80, rs, 4, rd, 0x3b); 760 761 return rv_i_insn(0x80, rs, 4, rd, 0x33); 762 } 763 764 static inline u32 rvzbb_rev8(u8 rd, u8 rs) 765 { 766 if (IS_ENABLED(CONFIG_64BIT)) 767 return rv_i_insn(0x6b8, rs, 5, rd, 0x13); 768 769 return rv_i_insn(0x698, rs, 5, rd, 0x13); 770 } 771 772 /* 773 * RV64-only instructions. 774 * 775 * These instructions are not available on RV32. Wrap them below a #if to 776 * ensure that the RV32 JIT doesn't emit any of these instructions. 777 */ 778 779 #if __riscv_xlen == 64 780 781 static inline u32 rv_addiw(u8 rd, u8 rs1, u16 imm11_0) 782 { 783 return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b); 784 } 785 786 static inline u32 rv_slliw(u8 rd, u8 rs1, u16 imm11_0) 787 { 788 return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b); 789 } 790 791 static inline u32 rv_srliw(u8 rd, u8 rs1, u16 imm11_0) 792 { 793 return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b); 794 } 795 796 static inline u32 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0) 797 { 798 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b); 799 } 800 801 static inline u32 rv_addw(u8 rd, u8 rs1, u8 rs2) 802 { 803 return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b); 804 } 805 806 static inline u32 rv_subw(u8 rd, u8 rs1, u8 rs2) 807 { 808 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b); 809 } 810 811 static inline u32 rv_sllw(u8 rd, u8 rs1, u8 rs2) 812 { 813 return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b); 814 } 815 816 static inline u32 rv_srlw(u8 rd, u8 rs1, u8 rs2) 817 { 818 return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b); 819 } 820 821 static inline u32 rv_sraw(u8 rd, u8 rs1, u8 rs2) 822 { 823 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b); 824 } 825 826 static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2) 827 { 828 return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b); 829 } 830 831 static inline u32 rv_divw(u8 rd, u8 rs1, u8 rs2) 832 { 833 return rv_r_insn(1, rs2, rs1, 4, rd, 0x3b); 834 } 835 836 static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2) 837 { 838 return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b); 839 } 840 841 static inline u32 rv_remw(u8 rd, u8 rs1, u8 rs2) 842 { 843 return rv_r_insn(1, rs2, rs1, 6, rd, 0x3b); 844 } 845 846 static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2) 847 { 848 return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b); 849 } 850 851 static inline u32 rv_ld(u8 rd, u16 imm11_0, u8 rs1) 852 { 853 return rv_i_insn(imm11_0, rs1, 3, rd, 0x03); 854 } 855 856 static inline u32 rv_lwu(u8 rd, u16 imm11_0, u8 rs1) 857 { 858 return rv_i_insn(imm11_0, rs1, 6, rd, 0x03); 859 } 860 861 static inline u32 rv_sd(u8 rs1, u16 imm11_0, u8 rs2) 862 { 863 return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23); 864 } 865 866 static inline u32 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 867 { 868 return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f); 869 } 870 871 static inline u32 rv_amoand_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 872 { 873 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 3, rd, 0x2f); 874 } 875 876 static inline u32 rv_amoor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 877 { 878 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 3, rd, 0x2f); 879 } 880 881 static inline u32 rv_amoxor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 882 { 883 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 3, rd, 0x2f); 884 } 885 886 static inline u32 rv_amoswap_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 887 { 888 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 3, rd, 0x2f); 889 } 890 891 static inline u32 rv_lr_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 892 { 893 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 3, rd, 0x2f); 894 } 895 896 static inline u32 rv_sc_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl) 897 { 898 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 3, rd, 0x2f); 899 } 900 901 /* RV64-only RVC instructions. */ 902 903 static inline u16 rvc_ld(u8 rd, u32 imm8, u8 rs1) 904 { 905 u32 imm_hi, imm_lo; 906 907 imm_hi = (imm8 & 0x38) >> 3; 908 imm_lo = (imm8 & 0xc0) >> 6; 909 return rv_cl_insn(0x3, imm_hi, rs1, imm_lo, rd, 0x0); 910 } 911 912 static inline u16 rvc_sd(u8 rs1, u32 imm8, u8 rs2) 913 { 914 u32 imm_hi, imm_lo; 915 916 imm_hi = (imm8 & 0x38) >> 3; 917 imm_lo = (imm8 & 0xc0) >> 6; 918 return rv_cs_insn(0x7, imm_hi, rs1, imm_lo, rs2, 0x0); 919 } 920 921 static inline u16 rvc_subw(u8 rd, u8 rs) 922 { 923 return rv_ca_insn(0x27, rd, 0, rs, 0x1); 924 } 925 926 static inline u16 rvc_addiw(u8 rd, u32 imm6) 927 { 928 return rv_ci_insn(0x1, imm6, rd, 0x1); 929 } 930 931 static inline u16 rvc_ldsp(u8 rd, u32 imm9) 932 { 933 u32 imm; 934 935 imm = ((imm9 & 0x1c0) >> 6) | (imm9 & 0x38); 936 return rv_ci_insn(0x3, imm, rd, 0x2); 937 } 938 939 static inline u16 rvc_sdsp(u32 imm9, u8 rs2) 940 { 941 u32 imm; 942 943 imm = (imm9 & 0x38) | ((imm9 & 0x1c0) >> 6); 944 return rv_css_insn(0x7, imm, rs2, 0x2); 945 } 946 947 /* RV64-only ZBA instructions. */ 948 949 static inline u32 rvzba_zextw(u8 rd, u8 rs1) 950 { 951 /* add.uw rd, rs1, ZERO */ 952 return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b); 953 } 954 955 #endif /* __riscv_xlen == 64 */ 956 957 /* Helper functions that emit RVC instructions when possible. */ 958 959 static inline void emit_jalr(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 960 { 961 if (rvc_enabled() && rd == RV_REG_RA && rs && !imm) 962 emitc(rvc_jalr(rs), ctx); 963 else if (rvc_enabled() && !rd && rs && !imm) 964 emitc(rvc_jr(rs), ctx); 965 else 966 emit(rv_jalr(rd, rs, imm), ctx); 967 } 968 969 static inline void emit_mv(u8 rd, u8 rs, struct rv_jit_context *ctx) 970 { 971 if (rvc_enabled() && rd && rs) 972 emitc(rvc_mv(rd, rs), ctx); 973 else 974 emit(rv_addi(rd, rs, 0), ctx); 975 } 976 977 static inline void emit_add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 978 { 979 if (rvc_enabled() && rd && rd == rs1 && rs2) 980 emitc(rvc_add(rd, rs2), ctx); 981 else 982 emit(rv_add(rd, rs1, rs2), ctx); 983 } 984 985 static inline void emit_addi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 986 { 987 if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf)) 988 emitc(rvc_addi16sp(imm), ctx); 989 else if (rvc_enabled() && is_creg(rd) && rs == RV_REG_SP && is_10b_uint(imm) && 990 !(imm & 0x3) && imm) 991 emitc(rvc_addi4spn(rd, imm), ctx); 992 else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm)) 993 emitc(rvc_addi(rd, imm), ctx); 994 else 995 emit(rv_addi(rd, rs, imm), ctx); 996 } 997 998 static inline void emit_li(u8 rd, s32 imm, struct rv_jit_context *ctx) 999 { 1000 if (rvc_enabled() && rd && is_6b_int(imm)) 1001 emitc(rvc_li(rd, imm), ctx); 1002 else 1003 emit(rv_addi(rd, RV_REG_ZERO, imm), ctx); 1004 } 1005 1006 static inline void emit_lui(u8 rd, s32 imm, struct rv_jit_context *ctx) 1007 { 1008 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm) 1009 emitc(rvc_lui(rd, imm), ctx); 1010 else 1011 emit(rv_lui(rd, imm), ctx); 1012 } 1013 1014 static inline void emit_slli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 1015 { 1016 if (rvc_enabled() && rd && rd == rs && imm && (u32)imm < __riscv_xlen) 1017 emitc(rvc_slli(rd, imm), ctx); 1018 else 1019 emit(rv_slli(rd, rs, imm), ctx); 1020 } 1021 1022 static inline void emit_andi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 1023 { 1024 if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm)) 1025 emitc(rvc_andi(rd, imm), ctx); 1026 else 1027 emit(rv_andi(rd, rs, imm), ctx); 1028 } 1029 1030 static inline void emit_srli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 1031 { 1032 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen) 1033 emitc(rvc_srli(rd, imm), ctx); 1034 else 1035 emit(rv_srli(rd, rs, imm), ctx); 1036 } 1037 1038 static inline void emit_srai(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 1039 { 1040 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen) 1041 emitc(rvc_srai(rd, imm), ctx); 1042 else 1043 emit(rv_srai(rd, rs, imm), ctx); 1044 } 1045 1046 static inline void emit_sub(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1047 { 1048 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) 1049 emitc(rvc_sub(rd, rs2), ctx); 1050 else 1051 emit(rv_sub(rd, rs1, rs2), ctx); 1052 } 1053 1054 static inline void emit_or(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1055 { 1056 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) 1057 emitc(rvc_or(rd, rs2), ctx); 1058 else 1059 emit(rv_or(rd, rs1, rs2), ctx); 1060 } 1061 1062 static inline void emit_and(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1063 { 1064 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) 1065 emitc(rvc_and(rd, rs2), ctx); 1066 else 1067 emit(rv_and(rd, rs1, rs2), ctx); 1068 } 1069 1070 static inline void emit_xor(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1071 { 1072 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) 1073 emitc(rvc_xor(rd, rs2), ctx); 1074 else 1075 emit(rv_xor(rd, rs1, rs2), ctx); 1076 } 1077 1078 static inline void emit_lw(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx) 1079 { 1080 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3)) 1081 emitc(rvc_lwsp(rd, off), ctx); 1082 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_7b_uint(off) && !(off & 0x3)) 1083 emitc(rvc_lw(rd, off, rs1), ctx); 1084 else 1085 emit(rv_lw(rd, off, rs1), ctx); 1086 } 1087 1088 static inline void emit_sw(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx) 1089 { 1090 if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3)) 1091 emitc(rvc_swsp(off, rs2), ctx); 1092 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_7b_uint(off) && !(off & 0x3)) 1093 emitc(rvc_sw(rs1, off, rs2), ctx); 1094 else 1095 emit(rv_sw(rs1, off, rs2), ctx); 1096 } 1097 1098 /* RV64-only helper functions. */ 1099 #if __riscv_xlen == 64 1100 1101 static inline void emit_addiw(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx) 1102 { 1103 if (rvc_enabled() && rd && rd == rs && is_6b_int(imm)) 1104 emitc(rvc_addiw(rd, imm), ctx); 1105 else 1106 emit(rv_addiw(rd, rs, imm), ctx); 1107 } 1108 1109 static inline void emit_ld(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx) 1110 { 1111 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7)) 1112 emitc(rvc_ldsp(rd, off), ctx); 1113 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_8b_uint(off) && !(off & 0x7)) 1114 emitc(rvc_ld(rd, off, rs1), ctx); 1115 else 1116 emit(rv_ld(rd, off, rs1), ctx); 1117 } 1118 1119 static inline void emit_sd(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx) 1120 { 1121 if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7)) 1122 emitc(rvc_sdsp(off, rs2), ctx); 1123 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_8b_uint(off) && !(off & 0x7)) 1124 emitc(rvc_sd(rs1, off, rs2), ctx); 1125 else 1126 emit(rv_sd(rs1, off, rs2), ctx); 1127 } 1128 1129 static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx) 1130 { 1131 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2)) 1132 emitc(rvc_subw(rd, rs2), ctx); 1133 else 1134 emit(rv_subw(rd, rs1, rs2), ctx); 1135 } 1136 1137 static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx) 1138 { 1139 if (rvzbb_enabled()) { 1140 emit(rvzbb_sextb(rd, rs), ctx); 1141 return; 1142 } 1143 1144 emit_slli(rd, rs, 56, ctx); 1145 emit_srai(rd, rd, 56, ctx); 1146 } 1147 1148 static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx) 1149 { 1150 if (rvzbb_enabled()) { 1151 emit(rvzbb_sexth(rd, rs), ctx); 1152 return; 1153 } 1154 1155 emit_slli(rd, rs, 48, ctx); 1156 emit_srai(rd, rd, 48, ctx); 1157 } 1158 1159 static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx) 1160 { 1161 emit_addiw(rd, rs, 0, ctx); 1162 } 1163 1164 static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx) 1165 { 1166 if (rvzbb_enabled()) { 1167 emit(rvzbb_zexth(rd, rs), ctx); 1168 return; 1169 } 1170 1171 emit_slli(rd, rs, 48, ctx); 1172 emit_srli(rd, rd, 48, ctx); 1173 } 1174 1175 static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx) 1176 { 1177 if (rvzba_enabled()) { 1178 emit(rvzba_zextw(rd, rs), ctx); 1179 return; 1180 } 1181 1182 emit_slli(rd, rs, 32, ctx); 1183 emit_srli(rd, rd, 32, ctx); 1184 } 1185 1186 static inline void emit_bswap(u8 rd, s32 imm, struct rv_jit_context *ctx) 1187 { 1188 if (rvzbb_enabled()) { 1189 int bits = 64 - imm; 1190 1191 emit(rvzbb_rev8(rd, rd), ctx); 1192 if (bits) 1193 emit_srli(rd, rd, bits, ctx); 1194 return; 1195 } 1196 1197 emit_li(RV_REG_T2, 0, ctx); 1198 1199 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1200 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1201 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1202 emit_srli(rd, rd, 8, ctx); 1203 if (imm == 16) 1204 goto out_be; 1205 1206 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1207 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1208 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1209 emit_srli(rd, rd, 8, ctx); 1210 1211 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1212 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1213 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1214 emit_srli(rd, rd, 8, ctx); 1215 if (imm == 32) 1216 goto out_be; 1217 1218 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1219 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1220 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1221 emit_srli(rd, rd, 8, ctx); 1222 1223 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1224 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1225 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1226 emit_srli(rd, rd, 8, ctx); 1227 1228 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1229 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1230 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1231 emit_srli(rd, rd, 8, ctx); 1232 1233 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1234 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1235 emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); 1236 emit_srli(rd, rd, 8, ctx); 1237 out_be: 1238 emit_andi(RV_REG_T1, rd, 0xff, ctx); 1239 emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); 1240 1241 emit_mv(rd, RV_REG_T2, ctx); 1242 } 1243 1244 #endif /* __riscv_xlen == 64 */ 1245 1246 void bpf_jit_build_prologue(struct rv_jit_context *ctx, bool is_subprog); 1247 void bpf_jit_build_epilogue(struct rv_jit_context *ctx); 1248 1249 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, 1250 bool extra_pass); 1251 1252 #endif /* _BPF_JIT_H */ 1253