1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/entry-kvm.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/kdebug.h> 14 #include <linux/module.h> 15 #include <linux/percpu.h> 16 #include <linux/vmalloc.h> 17 #include <linux/sched/signal.h> 18 #include <linux/fs.h> 19 #include <linux/kvm_host.h> 20 #include <asm/cacheflush.h> 21 #include <asm/kvm_nacl.h> 22 #include <asm/kvm_vcpu_vector.h> 23 24 #define CREATE_TRACE_POINTS 25 #include "trace.h" 26 27 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 28 KVM_GENERIC_VCPU_STATS(), 29 STATS_DESC_COUNTER(VCPU, ecall_exit_stat), 30 STATS_DESC_COUNTER(VCPU, wfi_exit_stat), 31 STATS_DESC_COUNTER(VCPU, wrs_exit_stat), 32 STATS_DESC_COUNTER(VCPU, mmio_exit_user), 33 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), 34 STATS_DESC_COUNTER(VCPU, csr_exit_user), 35 STATS_DESC_COUNTER(VCPU, csr_exit_kernel), 36 STATS_DESC_COUNTER(VCPU, signal_exits), 37 STATS_DESC_COUNTER(VCPU, exits), 38 STATS_DESC_COUNTER(VCPU, instr_illegal_exits), 39 STATS_DESC_COUNTER(VCPU, load_misaligned_exits), 40 STATS_DESC_COUNTER(VCPU, store_misaligned_exits), 41 STATS_DESC_COUNTER(VCPU, load_access_exits), 42 STATS_DESC_COUNTER(VCPU, store_access_exits), 43 }; 44 45 const struct kvm_stats_header kvm_vcpu_stats_header = { 46 .name_size = KVM_STATS_NAME_SIZE, 47 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 48 .id_offset = sizeof(struct kvm_stats_header), 49 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 50 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 51 sizeof(kvm_vcpu_stats_desc), 52 }; 53 54 static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu *vcpu, 55 bool kvm_sbi_reset) 56 { 57 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 58 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 59 void *vector_datap = cntx->vector.datap; 60 61 memset(cntx, 0, sizeof(*cntx)); 62 memset(csr, 0, sizeof(*csr)); 63 memset(&vcpu->arch.smstateen_csr, 0, sizeof(vcpu->arch.smstateen_csr)); 64 65 /* Restore datap as it's not a part of the guest context. */ 66 cntx->vector.datap = vector_datap; 67 68 if (kvm_sbi_reset) 69 kvm_riscv_vcpu_sbi_load_reset_state(vcpu); 70 71 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ 72 cntx->sstatus = SR_SPP | SR_SPIE; 73 74 cntx->hstatus |= HSTATUS_VTW; 75 cntx->hstatus |= HSTATUS_SPVP; 76 cntx->hstatus |= HSTATUS_SPV; 77 } 78 79 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu, bool kvm_sbi_reset) 80 { 81 bool loaded; 82 83 /** 84 * The preemption should be disabled here because it races with 85 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which 86 * also calls vcpu_load/put. 87 */ 88 get_cpu(); 89 loaded = (vcpu->cpu != -1); 90 if (loaded) 91 kvm_arch_vcpu_put(vcpu); 92 93 vcpu->arch.last_exit_cpu = -1; 94 95 kvm_riscv_vcpu_context_reset(vcpu, kvm_sbi_reset); 96 97 kvm_riscv_vcpu_fp_reset(vcpu); 98 99 kvm_riscv_vcpu_vector_reset(vcpu); 100 101 kvm_riscv_vcpu_timer_reset(vcpu); 102 103 kvm_riscv_vcpu_aia_reset(vcpu); 104 105 bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS); 106 bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); 107 108 kvm_riscv_vcpu_pmu_reset(vcpu); 109 110 vcpu->arch.hfence_head = 0; 111 vcpu->arch.hfence_tail = 0; 112 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); 113 114 kvm_riscv_vcpu_sbi_sta_reset(vcpu); 115 116 /* Reset the guest CSRs for hotplug usecase */ 117 if (loaded) 118 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 119 put_cpu(); 120 } 121 122 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 123 { 124 return 0; 125 } 126 127 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 128 { 129 int rc; 130 131 spin_lock_init(&vcpu->arch.mp_state_lock); 132 133 /* Mark this VCPU never ran */ 134 vcpu->arch.ran_atleast_once = false; 135 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; 136 bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); 137 138 /* Setup ISA features available to VCPU */ 139 kvm_riscv_vcpu_setup_isa(vcpu); 140 141 /* Setup vendor, arch, and implementation details */ 142 vcpu->arch.mvendorid = sbi_get_mvendorid(); 143 vcpu->arch.marchid = sbi_get_marchid(); 144 vcpu->arch.mimpid = sbi_get_mimpid(); 145 146 /* Setup VCPU hfence queue */ 147 spin_lock_init(&vcpu->arch.hfence_lock); 148 149 spin_lock_init(&vcpu->arch.reset_state.lock); 150 151 if (kvm_riscv_vcpu_alloc_vector_context(vcpu)) 152 return -ENOMEM; 153 154 /* Setup VCPU timer */ 155 kvm_riscv_vcpu_timer_init(vcpu); 156 157 /* setup performance monitoring */ 158 kvm_riscv_vcpu_pmu_init(vcpu); 159 160 /* Setup VCPU AIA */ 161 rc = kvm_riscv_vcpu_aia_init(vcpu); 162 if (rc) 163 return rc; 164 165 /* 166 * Setup SBI extensions 167 * NOTE: This must be the last thing to be initialized. 168 */ 169 kvm_riscv_vcpu_sbi_init(vcpu); 170 171 /* Reset VCPU */ 172 kvm_riscv_reset_vcpu(vcpu, false); 173 174 return 0; 175 } 176 177 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 178 { 179 /** 180 * vcpu with id 0 is the designated boot cpu. 181 * Keep all vcpus with non-zero id in power-off state so that 182 * they can be brought up using SBI HSM extension. 183 */ 184 if (vcpu->vcpu_idx != 0) 185 kvm_riscv_vcpu_power_off(vcpu); 186 } 187 188 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 189 { 190 /* Cleanup VCPU AIA context */ 191 kvm_riscv_vcpu_aia_deinit(vcpu); 192 193 /* Cleanup VCPU timer */ 194 kvm_riscv_vcpu_timer_deinit(vcpu); 195 196 kvm_riscv_vcpu_pmu_deinit(vcpu); 197 198 /* Free unused pages pre-allocated for G-stage page table mappings */ 199 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 200 201 /* Free vector context space for host and guest kernel */ 202 kvm_riscv_vcpu_free_vector_context(vcpu); 203 } 204 205 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 206 { 207 return kvm_riscv_vcpu_timer_pending(vcpu); 208 } 209 210 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 211 { 212 kvm_riscv_aia_wakeon_hgei(vcpu, true); 213 } 214 215 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 216 { 217 kvm_riscv_aia_wakeon_hgei(vcpu, false); 218 } 219 220 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 221 { 222 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && 223 !kvm_riscv_vcpu_stopped(vcpu) && !vcpu->arch.pause); 224 } 225 226 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 227 { 228 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 229 } 230 231 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 232 { 233 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; 234 } 235 236 #ifdef CONFIG_GUEST_PERF_EVENTS 237 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 238 { 239 return vcpu->arch.guest_context.sepc; 240 } 241 #endif 242 243 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 244 { 245 return VM_FAULT_SIGBUS; 246 } 247 248 long kvm_arch_vcpu_async_ioctl(struct file *filp, 249 unsigned int ioctl, unsigned long arg) 250 { 251 struct kvm_vcpu *vcpu = filp->private_data; 252 void __user *argp = (void __user *)arg; 253 254 if (ioctl == KVM_INTERRUPT) { 255 struct kvm_interrupt irq; 256 257 if (copy_from_user(&irq, argp, sizeof(irq))) 258 return -EFAULT; 259 260 if (irq.irq == KVM_INTERRUPT_SET) 261 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); 262 else 263 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); 264 } 265 266 return -ENOIOCTLCMD; 267 } 268 269 long kvm_arch_vcpu_ioctl(struct file *filp, 270 unsigned int ioctl, unsigned long arg) 271 { 272 struct kvm_vcpu *vcpu = filp->private_data; 273 void __user *argp = (void __user *)arg; 274 long r = -EINVAL; 275 276 switch (ioctl) { 277 case KVM_SET_ONE_REG: 278 case KVM_GET_ONE_REG: { 279 struct kvm_one_reg reg; 280 281 r = -EFAULT; 282 if (copy_from_user(®, argp, sizeof(reg))) 283 break; 284 285 if (ioctl == KVM_SET_ONE_REG) 286 r = kvm_riscv_vcpu_set_reg(vcpu, ®); 287 else 288 r = kvm_riscv_vcpu_get_reg(vcpu, ®); 289 break; 290 } 291 case KVM_GET_REG_LIST: { 292 struct kvm_reg_list __user *user_list = argp; 293 struct kvm_reg_list reg_list; 294 unsigned int n; 295 296 r = -EFAULT; 297 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 298 break; 299 n = reg_list.n; 300 reg_list.n = kvm_riscv_vcpu_num_regs(vcpu); 301 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 302 break; 303 r = -E2BIG; 304 if (n < reg_list.n) 305 break; 306 r = kvm_riscv_vcpu_copy_reg_indices(vcpu, user_list->reg); 307 break; 308 } 309 default: 310 break; 311 } 312 313 return r; 314 } 315 316 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 317 struct kvm_sregs *sregs) 318 { 319 return -EINVAL; 320 } 321 322 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 323 struct kvm_sregs *sregs) 324 { 325 return -EINVAL; 326 } 327 328 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 329 { 330 return -EINVAL; 331 } 332 333 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 334 { 335 return -EINVAL; 336 } 337 338 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 339 struct kvm_translation *tr) 340 { 341 return -EINVAL; 342 } 343 344 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 345 { 346 return -EINVAL; 347 } 348 349 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 350 { 351 return -EINVAL; 352 } 353 354 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) 355 { 356 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 357 unsigned long mask, val; 358 359 if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) { 360 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0); 361 val = READ_ONCE(vcpu->arch.irqs_pending[0]) & mask; 362 363 csr->hvip &= ~mask; 364 csr->hvip |= val; 365 } 366 367 /* Flush AIA high interrupts */ 368 kvm_riscv_vcpu_aia_flush_interrupts(vcpu); 369 } 370 371 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 372 { 373 unsigned long hvip; 374 struct kvm_vcpu_arch *v = &vcpu->arch; 375 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 376 377 /* Read current HVIP and VSIE CSRs */ 378 csr->vsie = ncsr_read(CSR_VSIE); 379 380 /* Sync-up HVIP.VSSIP bit changes does by Guest */ 381 hvip = ncsr_read(CSR_HVIP); 382 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { 383 if (hvip & (1UL << IRQ_VS_SOFT)) { 384 if (!test_and_set_bit(IRQ_VS_SOFT, 385 v->irqs_pending_mask)) 386 set_bit(IRQ_VS_SOFT, v->irqs_pending); 387 } else { 388 if (!test_and_set_bit(IRQ_VS_SOFT, 389 v->irqs_pending_mask)) 390 clear_bit(IRQ_VS_SOFT, v->irqs_pending); 391 } 392 } 393 394 /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ 395 if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { 396 if (!(hvip & (1UL << IRQ_PMU_OVF)) && 397 !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) 398 clear_bit(IRQ_PMU_OVF, v->irqs_pending); 399 } 400 401 /* Sync-up AIA high interrupts */ 402 kvm_riscv_vcpu_aia_sync_interrupts(vcpu); 403 404 /* Sync-up timer CSRs */ 405 kvm_riscv_vcpu_timer_sync(vcpu); 406 } 407 408 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 409 { 410 /* 411 * We only allow VS-mode software, timer, and external 412 * interrupts when irq is one of the local interrupts 413 * defined by RISC-V privilege specification. 414 */ 415 if (irq < IRQ_LOCAL_MAX && 416 irq != IRQ_VS_SOFT && 417 irq != IRQ_VS_TIMER && 418 irq != IRQ_VS_EXT && 419 irq != IRQ_PMU_OVF) 420 return -EINVAL; 421 422 set_bit(irq, vcpu->arch.irqs_pending); 423 smp_mb__before_atomic(); 424 set_bit(irq, vcpu->arch.irqs_pending_mask); 425 426 kvm_vcpu_kick(vcpu); 427 428 return 0; 429 } 430 431 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 432 { 433 /* 434 * We only allow VS-mode software, timer, counter overflow and external 435 * interrupts when irq is one of the local interrupts 436 * defined by RISC-V privilege specification. 437 */ 438 if (irq < IRQ_LOCAL_MAX && 439 irq != IRQ_VS_SOFT && 440 irq != IRQ_VS_TIMER && 441 irq != IRQ_VS_EXT && 442 irq != IRQ_PMU_OVF) 443 return -EINVAL; 444 445 clear_bit(irq, vcpu->arch.irqs_pending); 446 smp_mb__before_atomic(); 447 set_bit(irq, vcpu->arch.irqs_pending_mask); 448 449 return 0; 450 } 451 452 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask) 453 { 454 unsigned long ie; 455 456 ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) 457 << VSIP_TO_HVIP_SHIFT) & (unsigned long)mask; 458 ie |= vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK & 459 (unsigned long)mask; 460 if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie) 461 return true; 462 463 /* Check AIA high interrupts */ 464 return kvm_riscv_vcpu_aia_has_interrupts(vcpu, mask); 465 } 466 467 void __kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 468 { 469 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_STOPPED); 470 kvm_make_request(KVM_REQ_SLEEP, vcpu); 471 kvm_vcpu_kick(vcpu); 472 } 473 474 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 475 { 476 spin_lock(&vcpu->arch.mp_state_lock); 477 __kvm_riscv_vcpu_power_off(vcpu); 478 spin_unlock(&vcpu->arch.mp_state_lock); 479 } 480 481 void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 482 { 483 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_RUNNABLE); 484 kvm_vcpu_wake_up(vcpu); 485 } 486 487 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 488 { 489 spin_lock(&vcpu->arch.mp_state_lock); 490 __kvm_riscv_vcpu_power_on(vcpu); 491 spin_unlock(&vcpu->arch.mp_state_lock); 492 } 493 494 bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu) 495 { 496 return READ_ONCE(vcpu->arch.mp_state.mp_state) == KVM_MP_STATE_STOPPED; 497 } 498 499 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 500 struct kvm_mp_state *mp_state) 501 { 502 *mp_state = READ_ONCE(vcpu->arch.mp_state); 503 504 return 0; 505 } 506 507 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 508 struct kvm_mp_state *mp_state) 509 { 510 int ret = 0; 511 512 spin_lock(&vcpu->arch.mp_state_lock); 513 514 switch (mp_state->mp_state) { 515 case KVM_MP_STATE_RUNNABLE: 516 WRITE_ONCE(vcpu->arch.mp_state, *mp_state); 517 break; 518 case KVM_MP_STATE_STOPPED: 519 __kvm_riscv_vcpu_power_off(vcpu); 520 break; 521 case KVM_MP_STATE_INIT_RECEIVED: 522 if (vcpu->kvm->arch.mp_state_reset) 523 kvm_riscv_reset_vcpu(vcpu, false); 524 else 525 ret = -EINVAL; 526 break; 527 default: 528 ret = -EINVAL; 529 } 530 531 spin_unlock(&vcpu->arch.mp_state_lock); 532 533 return ret; 534 } 535 536 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 537 struct kvm_guest_debug *dbg) 538 { 539 if (dbg->control & KVM_GUESTDBG_ENABLE) { 540 vcpu->guest_debug = dbg->control; 541 vcpu->arch.cfg.hedeleg &= ~BIT(EXC_BREAKPOINT); 542 } else { 543 vcpu->guest_debug = 0; 544 vcpu->arch.cfg.hedeleg |= BIT(EXC_BREAKPOINT); 545 } 546 547 return 0; 548 } 549 550 static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) 551 { 552 const unsigned long *isa = vcpu->arch.isa; 553 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 554 555 if (riscv_isa_extension_available(isa, SVPBMT)) 556 cfg->henvcfg |= ENVCFG_PBMTE; 557 558 if (riscv_isa_extension_available(isa, SSTC)) 559 cfg->henvcfg |= ENVCFG_STCE; 560 561 if (riscv_isa_extension_available(isa, ZICBOM)) 562 cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); 563 564 if (riscv_isa_extension_available(isa, ZICBOZ)) 565 cfg->henvcfg |= ENVCFG_CBZE; 566 567 if (riscv_isa_extension_available(isa, SVADU) && 568 !riscv_isa_extension_available(isa, SVADE)) 569 cfg->henvcfg |= ENVCFG_ADUE; 570 571 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { 572 cfg->hstateen0 |= SMSTATEEN0_HSENVCFG; 573 if (riscv_isa_extension_available(isa, SSAIA)) 574 cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC | 575 SMSTATEEN0_AIA | 576 SMSTATEEN0_AIA_ISEL; 577 if (riscv_isa_extension_available(isa, SMSTATEEN)) 578 cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0; 579 } 580 581 cfg->hedeleg = KVM_HEDELEG_DEFAULT; 582 if (vcpu->guest_debug) 583 cfg->hedeleg &= ~BIT(EXC_BREAKPOINT); 584 } 585 586 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 587 { 588 void *nsh; 589 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 590 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 591 592 if (kvm_riscv_nacl_sync_csr_available()) { 593 nsh = nacl_shmem(); 594 nacl_csr_write(nsh, CSR_VSSTATUS, csr->vsstatus); 595 nacl_csr_write(nsh, CSR_VSIE, csr->vsie); 596 nacl_csr_write(nsh, CSR_VSTVEC, csr->vstvec); 597 nacl_csr_write(nsh, CSR_VSSCRATCH, csr->vsscratch); 598 nacl_csr_write(nsh, CSR_VSEPC, csr->vsepc); 599 nacl_csr_write(nsh, CSR_VSCAUSE, csr->vscause); 600 nacl_csr_write(nsh, CSR_VSTVAL, csr->vstval); 601 nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg); 602 nacl_csr_write(nsh, CSR_HVIP, csr->hvip); 603 nacl_csr_write(nsh, CSR_VSATP, csr->vsatp); 604 nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg); 605 if (IS_ENABLED(CONFIG_32BIT)) 606 nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32); 607 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { 608 nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0); 609 if (IS_ENABLED(CONFIG_32BIT)) 610 nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32); 611 } 612 } else { 613 csr_write(CSR_VSSTATUS, csr->vsstatus); 614 csr_write(CSR_VSIE, csr->vsie); 615 csr_write(CSR_VSTVEC, csr->vstvec); 616 csr_write(CSR_VSSCRATCH, csr->vsscratch); 617 csr_write(CSR_VSEPC, csr->vsepc); 618 csr_write(CSR_VSCAUSE, csr->vscause); 619 csr_write(CSR_VSTVAL, csr->vstval); 620 csr_write(CSR_HEDELEG, cfg->hedeleg); 621 csr_write(CSR_HVIP, csr->hvip); 622 csr_write(CSR_VSATP, csr->vsatp); 623 csr_write(CSR_HENVCFG, cfg->henvcfg); 624 if (IS_ENABLED(CONFIG_32BIT)) 625 csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); 626 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { 627 csr_write(CSR_HSTATEEN0, cfg->hstateen0); 628 if (IS_ENABLED(CONFIG_32BIT)) 629 csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32); 630 } 631 } 632 633 kvm_riscv_gstage_update_hgatp(vcpu); 634 635 kvm_riscv_vcpu_timer_restore(vcpu); 636 637 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); 638 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, 639 vcpu->arch.isa); 640 kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); 641 kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, 642 vcpu->arch.isa); 643 644 kvm_riscv_vcpu_aia_load(vcpu, cpu); 645 646 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 647 648 vcpu->cpu = cpu; 649 } 650 651 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 652 { 653 void *nsh; 654 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 655 656 vcpu->cpu = -1; 657 658 kvm_riscv_vcpu_aia_put(vcpu); 659 660 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, 661 vcpu->arch.isa); 662 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); 663 664 kvm_riscv_vcpu_timer_save(vcpu); 665 kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, 666 vcpu->arch.isa); 667 kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); 668 669 if (kvm_riscv_nacl_available()) { 670 nsh = nacl_shmem(); 671 csr->vsstatus = nacl_csr_read(nsh, CSR_VSSTATUS); 672 csr->vsie = nacl_csr_read(nsh, CSR_VSIE); 673 csr->vstvec = nacl_csr_read(nsh, CSR_VSTVEC); 674 csr->vsscratch = nacl_csr_read(nsh, CSR_VSSCRATCH); 675 csr->vsepc = nacl_csr_read(nsh, CSR_VSEPC); 676 csr->vscause = nacl_csr_read(nsh, CSR_VSCAUSE); 677 csr->vstval = nacl_csr_read(nsh, CSR_VSTVAL); 678 csr->hvip = nacl_csr_read(nsh, CSR_HVIP); 679 csr->vsatp = nacl_csr_read(nsh, CSR_VSATP); 680 } else { 681 csr->vsstatus = csr_read(CSR_VSSTATUS); 682 csr->vsie = csr_read(CSR_VSIE); 683 csr->vstvec = csr_read(CSR_VSTVEC); 684 csr->vsscratch = csr_read(CSR_VSSCRATCH); 685 csr->vsepc = csr_read(CSR_VSEPC); 686 csr->vscause = csr_read(CSR_VSCAUSE); 687 csr->vstval = csr_read(CSR_VSTVAL); 688 csr->hvip = csr_read(CSR_HVIP); 689 csr->vsatp = csr_read(CSR_VSATP); 690 } 691 } 692 693 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) 694 { 695 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu); 696 697 if (kvm_request_pending(vcpu)) { 698 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { 699 kvm_vcpu_srcu_read_unlock(vcpu); 700 rcuwait_wait_event(wait, 701 (!kvm_riscv_vcpu_stopped(vcpu)) && (!vcpu->arch.pause), 702 TASK_INTERRUPTIBLE); 703 kvm_vcpu_srcu_read_lock(vcpu); 704 705 if (kvm_riscv_vcpu_stopped(vcpu) || vcpu->arch.pause) { 706 /* 707 * Awaken to handle a signal, request to 708 * sleep again later. 709 */ 710 kvm_make_request(KVM_REQ_SLEEP, vcpu); 711 } 712 } 713 714 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) 715 kvm_riscv_reset_vcpu(vcpu, true); 716 717 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) 718 kvm_riscv_gstage_update_hgatp(vcpu); 719 720 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) 721 kvm_riscv_fence_i_process(vcpu); 722 723 /* 724 * The generic KVM_REQ_TLB_FLUSH is same as 725 * KVM_REQ_HFENCE_GVMA_VMID_ALL 726 */ 727 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) 728 kvm_riscv_hfence_gvma_vmid_all_process(vcpu); 729 730 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) 731 kvm_riscv_hfence_vvma_all_process(vcpu); 732 733 if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) 734 kvm_riscv_hfence_process(vcpu); 735 736 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 737 kvm_riscv_vcpu_record_steal_time(vcpu); 738 } 739 } 740 741 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 742 { 743 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 744 745 ncsr_write(CSR_HVIP, csr->hvip); 746 kvm_riscv_vcpu_aia_update_hvip(vcpu); 747 } 748 749 static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu) 750 { 751 struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; 752 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 753 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 754 755 vcpu->arch.host_scounteren = csr_swap(CSR_SCOUNTEREN, csr->scounteren); 756 vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg); 757 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && 758 (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) 759 vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0, 760 smcsr->sstateen0); 761 } 762 763 static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu) 764 { 765 struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; 766 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 767 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 768 769 csr->scounteren = csr_swap(CSR_SCOUNTEREN, vcpu->arch.host_scounteren); 770 csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); 771 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && 772 (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) 773 smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0, 774 vcpu->arch.host_sstateen0); 775 } 776 777 /* 778 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 779 * the vCPU is running. 780 * 781 * This must be noinstr as instrumentation may make use of RCU, and this is not 782 * safe during the EQS. 783 */ 784 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu, 785 struct kvm_cpu_trap *trap) 786 { 787 void *nsh; 788 struct kvm_cpu_context *gcntx = &vcpu->arch.guest_context; 789 struct kvm_cpu_context *hcntx = &vcpu->arch.host_context; 790 791 /* 792 * We save trap CSRs (such as SEPC, SCAUSE, STVAL, HTVAL, and 793 * HTINST) here because we do local_irq_enable() after this 794 * function in kvm_arch_vcpu_ioctl_run() which can result in 795 * an interrupt immediately after local_irq_enable() and can 796 * potentially change trap CSRs. 797 */ 798 799 kvm_riscv_vcpu_swap_in_guest_state(vcpu); 800 guest_state_enter_irqoff(); 801 802 if (kvm_riscv_nacl_sync_sret_available()) { 803 nsh = nacl_shmem(); 804 805 if (kvm_riscv_nacl_autoswap_csr_available()) { 806 hcntx->hstatus = 807 nacl_csr_read(nsh, CSR_HSTATUS); 808 nacl_scratch_write_long(nsh, 809 SBI_NACL_SHMEM_AUTOSWAP_OFFSET + 810 SBI_NACL_SHMEM_AUTOSWAP_HSTATUS, 811 gcntx->hstatus); 812 nacl_scratch_write_long(nsh, 813 SBI_NACL_SHMEM_AUTOSWAP_OFFSET, 814 SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS); 815 } else if (kvm_riscv_nacl_sync_csr_available()) { 816 hcntx->hstatus = nacl_csr_swap(nsh, 817 CSR_HSTATUS, gcntx->hstatus); 818 } else { 819 hcntx->hstatus = csr_swap(CSR_HSTATUS, gcntx->hstatus); 820 } 821 822 nacl_scratch_write_longs(nsh, 823 SBI_NACL_SHMEM_SRET_OFFSET + 824 SBI_NACL_SHMEM_SRET_X(1), 825 &gcntx->ra, 826 SBI_NACL_SHMEM_SRET_X_LAST); 827 828 __kvm_riscv_nacl_switch_to(&vcpu->arch, SBI_EXT_NACL, 829 SBI_EXT_NACL_SYNC_SRET); 830 831 if (kvm_riscv_nacl_autoswap_csr_available()) { 832 nacl_scratch_write_long(nsh, 833 SBI_NACL_SHMEM_AUTOSWAP_OFFSET, 834 0); 835 gcntx->hstatus = nacl_scratch_read_long(nsh, 836 SBI_NACL_SHMEM_AUTOSWAP_OFFSET + 837 SBI_NACL_SHMEM_AUTOSWAP_HSTATUS); 838 } else { 839 gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus); 840 } 841 842 trap->htval = nacl_csr_read(nsh, CSR_HTVAL); 843 trap->htinst = nacl_csr_read(nsh, CSR_HTINST); 844 } else { 845 hcntx->hstatus = csr_swap(CSR_HSTATUS, gcntx->hstatus); 846 847 __kvm_riscv_switch_to(&vcpu->arch); 848 849 gcntx->hstatus = csr_swap(CSR_HSTATUS, hcntx->hstatus); 850 851 trap->htval = csr_read(CSR_HTVAL); 852 trap->htinst = csr_read(CSR_HTINST); 853 } 854 855 trap->sepc = gcntx->sepc; 856 trap->scause = csr_read(CSR_SCAUSE); 857 trap->stval = csr_read(CSR_STVAL); 858 859 vcpu->arch.last_exit_cpu = vcpu->cpu; 860 guest_state_exit_irqoff(); 861 kvm_riscv_vcpu_swap_in_host_state(vcpu); 862 } 863 864 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 865 { 866 int ret; 867 struct kvm_cpu_trap trap; 868 struct kvm_run *run = vcpu->run; 869 870 if (!vcpu->arch.ran_atleast_once) 871 kvm_riscv_vcpu_setup_config(vcpu); 872 873 /* Mark this VCPU ran at least once */ 874 vcpu->arch.ran_atleast_once = true; 875 876 kvm_vcpu_srcu_read_lock(vcpu); 877 878 switch (run->exit_reason) { 879 case KVM_EXIT_MMIO: 880 /* Process MMIO value returned from user-space */ 881 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); 882 break; 883 case KVM_EXIT_RISCV_SBI: 884 /* Process SBI value returned from user-space */ 885 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); 886 break; 887 case KVM_EXIT_RISCV_CSR: 888 /* Process CSR value returned from user-space */ 889 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run); 890 break; 891 default: 892 ret = 0; 893 break; 894 } 895 if (ret) { 896 kvm_vcpu_srcu_read_unlock(vcpu); 897 return ret; 898 } 899 900 if (!vcpu->wants_to_run) { 901 kvm_vcpu_srcu_read_unlock(vcpu); 902 return -EINTR; 903 } 904 905 vcpu_load(vcpu); 906 907 kvm_sigset_activate(vcpu); 908 909 ret = 1; 910 run->exit_reason = KVM_EXIT_UNKNOWN; 911 while (ret > 0) { 912 /* Check conditions before entering the guest */ 913 ret = xfer_to_guest_mode_handle_work(vcpu); 914 if (ret) 915 continue; 916 ret = 1; 917 918 kvm_riscv_gstage_vmid_update(vcpu); 919 920 kvm_riscv_check_vcpu_requests(vcpu); 921 922 preempt_disable(); 923 924 /* Update AIA HW state before entering guest */ 925 ret = kvm_riscv_vcpu_aia_update(vcpu); 926 if (ret <= 0) { 927 preempt_enable(); 928 continue; 929 } 930 931 local_irq_disable(); 932 933 /* 934 * Ensure we set mode to IN_GUEST_MODE after we disable 935 * interrupts and before the final VCPU requests check. 936 * See the comment in kvm_vcpu_exiting_guest_mode() and 937 * Documentation/virt/kvm/vcpu-requests.rst 938 */ 939 vcpu->mode = IN_GUEST_MODE; 940 941 kvm_vcpu_srcu_read_unlock(vcpu); 942 smp_mb__after_srcu_read_unlock(); 943 944 /* 945 * We might have got VCPU interrupts updated asynchronously 946 * so update it in HW. 947 */ 948 kvm_riscv_vcpu_flush_interrupts(vcpu); 949 950 /* Update HVIP CSR for current CPU */ 951 kvm_riscv_update_hvip(vcpu); 952 953 if (kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || 954 kvm_request_pending(vcpu) || 955 xfer_to_guest_mode_work_pending()) { 956 vcpu->mode = OUTSIDE_GUEST_MODE; 957 local_irq_enable(); 958 preempt_enable(); 959 kvm_vcpu_srcu_read_lock(vcpu); 960 continue; 961 } 962 963 /* 964 * Cleanup stale TLB enteries 965 * 966 * Note: This should be done after G-stage VMID has been 967 * updated using kvm_riscv_gstage_vmid_ver_changed() 968 */ 969 kvm_riscv_local_tlb_sanitize(vcpu); 970 971 trace_kvm_entry(vcpu); 972 973 guest_timing_enter_irqoff(); 974 975 kvm_riscv_vcpu_enter_exit(vcpu, &trap); 976 977 vcpu->mode = OUTSIDE_GUEST_MODE; 978 vcpu->stat.exits++; 979 980 /* Syncup interrupts state with HW */ 981 kvm_riscv_vcpu_sync_interrupts(vcpu); 982 983 /* 984 * We must ensure that any pending interrupts are taken before 985 * we exit guest timing so that timer ticks are accounted as 986 * guest time. Transiently unmask interrupts so that any 987 * pending interrupts are taken. 988 * 989 * There's no barrier which ensures that pending interrupts are 990 * recognised, so we just hope that the CPU takes any pending 991 * interrupts between the enable and disable. 992 */ 993 local_irq_enable(); 994 local_irq_disable(); 995 996 guest_timing_exit_irqoff(); 997 998 local_irq_enable(); 999 1000 trace_kvm_exit(&trap); 1001 1002 preempt_enable(); 1003 1004 kvm_vcpu_srcu_read_lock(vcpu); 1005 1006 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); 1007 } 1008 1009 kvm_sigset_deactivate(vcpu); 1010 1011 vcpu_put(vcpu); 1012 1013 kvm_vcpu_srcu_read_unlock(vcpu); 1014 1015 return ret; 1016 } 1017