1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/entry-kvm.h> 11 #include <linux/errno.h> 12 #include <linux/err.h> 13 #include <linux/kdebug.h> 14 #include <linux/module.h> 15 #include <linux/percpu.h> 16 #include <linux/vmalloc.h> 17 #include <linux/sched/signal.h> 18 #include <linux/fs.h> 19 #include <linux/kvm_host.h> 20 #include <asm/csr.h> 21 #include <asm/cacheflush.h> 22 #include <asm/kvm_vcpu_vector.h> 23 24 #define CREATE_TRACE_POINTS 25 #include "trace.h" 26 27 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 28 KVM_GENERIC_VCPU_STATS(), 29 STATS_DESC_COUNTER(VCPU, ecall_exit_stat), 30 STATS_DESC_COUNTER(VCPU, wfi_exit_stat), 31 STATS_DESC_COUNTER(VCPU, wrs_exit_stat), 32 STATS_DESC_COUNTER(VCPU, mmio_exit_user), 33 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel), 34 STATS_DESC_COUNTER(VCPU, csr_exit_user), 35 STATS_DESC_COUNTER(VCPU, csr_exit_kernel), 36 STATS_DESC_COUNTER(VCPU, signal_exits), 37 STATS_DESC_COUNTER(VCPU, exits) 38 }; 39 40 const struct kvm_stats_header kvm_vcpu_stats_header = { 41 .name_size = KVM_STATS_NAME_SIZE, 42 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 43 .id_offset = sizeof(struct kvm_stats_header), 44 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 45 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 46 sizeof(kvm_vcpu_stats_desc), 47 }; 48 49 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) 50 { 51 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 52 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 53 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; 54 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; 55 bool loaded; 56 57 /** 58 * The preemption should be disabled here because it races with 59 * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which 60 * also calls vcpu_load/put. 61 */ 62 get_cpu(); 63 loaded = (vcpu->cpu != -1); 64 if (loaded) 65 kvm_arch_vcpu_put(vcpu); 66 67 vcpu->arch.last_exit_cpu = -1; 68 69 memcpy(csr, reset_csr, sizeof(*csr)); 70 71 spin_lock(&vcpu->arch.reset_cntx_lock); 72 memcpy(cntx, reset_cntx, sizeof(*cntx)); 73 spin_unlock(&vcpu->arch.reset_cntx_lock); 74 75 kvm_riscv_vcpu_fp_reset(vcpu); 76 77 kvm_riscv_vcpu_vector_reset(vcpu); 78 79 kvm_riscv_vcpu_timer_reset(vcpu); 80 81 kvm_riscv_vcpu_aia_reset(vcpu); 82 83 bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS); 84 bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS); 85 86 kvm_riscv_vcpu_pmu_reset(vcpu); 87 88 vcpu->arch.hfence_head = 0; 89 vcpu->arch.hfence_tail = 0; 90 memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue)); 91 92 kvm_riscv_vcpu_sbi_sta_reset(vcpu); 93 94 /* Reset the guest CSRs for hotplug usecase */ 95 if (loaded) 96 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 97 put_cpu(); 98 } 99 100 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 101 { 102 return 0; 103 } 104 105 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 106 { 107 int rc; 108 struct kvm_cpu_context *cntx; 109 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; 110 111 spin_lock_init(&vcpu->arch.mp_state_lock); 112 113 /* Mark this VCPU never ran */ 114 vcpu->arch.ran_atleast_once = false; 115 vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO; 116 bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX); 117 118 /* Setup ISA features available to VCPU */ 119 kvm_riscv_vcpu_setup_isa(vcpu); 120 121 /* Setup vendor, arch, and implementation details */ 122 vcpu->arch.mvendorid = sbi_get_mvendorid(); 123 vcpu->arch.marchid = sbi_get_marchid(); 124 vcpu->arch.mimpid = sbi_get_mimpid(); 125 126 /* Setup VCPU hfence queue */ 127 spin_lock_init(&vcpu->arch.hfence_lock); 128 129 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ 130 spin_lock_init(&vcpu->arch.reset_cntx_lock); 131 132 spin_lock(&vcpu->arch.reset_cntx_lock); 133 cntx = &vcpu->arch.guest_reset_context; 134 cntx->sstatus = SR_SPP | SR_SPIE; 135 cntx->hstatus = 0; 136 cntx->hstatus |= HSTATUS_VTW; 137 cntx->hstatus |= HSTATUS_SPVP; 138 cntx->hstatus |= HSTATUS_SPV; 139 spin_unlock(&vcpu->arch.reset_cntx_lock); 140 141 if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) 142 return -ENOMEM; 143 144 /* By default, make CY, TM, and IR counters accessible in VU mode */ 145 reset_csr->scounteren = 0x7; 146 147 /* Setup VCPU timer */ 148 kvm_riscv_vcpu_timer_init(vcpu); 149 150 /* setup performance monitoring */ 151 kvm_riscv_vcpu_pmu_init(vcpu); 152 153 /* Setup VCPU AIA */ 154 rc = kvm_riscv_vcpu_aia_init(vcpu); 155 if (rc) 156 return rc; 157 158 /* 159 * Setup SBI extensions 160 * NOTE: This must be the last thing to be initialized. 161 */ 162 kvm_riscv_vcpu_sbi_init(vcpu); 163 164 /* Reset VCPU */ 165 kvm_riscv_reset_vcpu(vcpu); 166 167 return 0; 168 } 169 170 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 171 { 172 /** 173 * vcpu with id 0 is the designated boot cpu. 174 * Keep all vcpus with non-zero id in power-off state so that 175 * they can be brought up using SBI HSM extension. 176 */ 177 if (vcpu->vcpu_idx != 0) 178 kvm_riscv_vcpu_power_off(vcpu); 179 } 180 181 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 182 { 183 /* Cleanup VCPU AIA context */ 184 kvm_riscv_vcpu_aia_deinit(vcpu); 185 186 /* Cleanup VCPU timer */ 187 kvm_riscv_vcpu_timer_deinit(vcpu); 188 189 kvm_riscv_vcpu_pmu_deinit(vcpu); 190 191 /* Free unused pages pre-allocated for G-stage page table mappings */ 192 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 193 194 /* Free vector context space for host and guest kernel */ 195 kvm_riscv_vcpu_free_vector_context(vcpu); 196 } 197 198 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 199 { 200 return kvm_riscv_vcpu_timer_pending(vcpu); 201 } 202 203 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) 204 { 205 kvm_riscv_aia_wakeon_hgei(vcpu, true); 206 } 207 208 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) 209 { 210 kvm_riscv_aia_wakeon_hgei(vcpu, false); 211 } 212 213 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 214 { 215 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) && 216 !kvm_riscv_vcpu_stopped(vcpu) && !vcpu->arch.pause); 217 } 218 219 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 220 { 221 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 222 } 223 224 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 225 { 226 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false; 227 } 228 229 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 230 { 231 return VM_FAULT_SIGBUS; 232 } 233 234 long kvm_arch_vcpu_async_ioctl(struct file *filp, 235 unsigned int ioctl, unsigned long arg) 236 { 237 struct kvm_vcpu *vcpu = filp->private_data; 238 void __user *argp = (void __user *)arg; 239 240 if (ioctl == KVM_INTERRUPT) { 241 struct kvm_interrupt irq; 242 243 if (copy_from_user(&irq, argp, sizeof(irq))) 244 return -EFAULT; 245 246 if (irq.irq == KVM_INTERRUPT_SET) 247 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT); 248 else 249 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT); 250 } 251 252 return -ENOIOCTLCMD; 253 } 254 255 long kvm_arch_vcpu_ioctl(struct file *filp, 256 unsigned int ioctl, unsigned long arg) 257 { 258 struct kvm_vcpu *vcpu = filp->private_data; 259 void __user *argp = (void __user *)arg; 260 long r = -EINVAL; 261 262 switch (ioctl) { 263 case KVM_SET_ONE_REG: 264 case KVM_GET_ONE_REG: { 265 struct kvm_one_reg reg; 266 267 r = -EFAULT; 268 if (copy_from_user(®, argp, sizeof(reg))) 269 break; 270 271 if (ioctl == KVM_SET_ONE_REG) 272 r = kvm_riscv_vcpu_set_reg(vcpu, ®); 273 else 274 r = kvm_riscv_vcpu_get_reg(vcpu, ®); 275 break; 276 } 277 case KVM_GET_REG_LIST: { 278 struct kvm_reg_list __user *user_list = argp; 279 struct kvm_reg_list reg_list; 280 unsigned int n; 281 282 r = -EFAULT; 283 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 284 break; 285 n = reg_list.n; 286 reg_list.n = kvm_riscv_vcpu_num_regs(vcpu); 287 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 288 break; 289 r = -E2BIG; 290 if (n < reg_list.n) 291 break; 292 r = kvm_riscv_vcpu_copy_reg_indices(vcpu, user_list->reg); 293 break; 294 } 295 default: 296 break; 297 } 298 299 return r; 300 } 301 302 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 303 struct kvm_sregs *sregs) 304 { 305 return -EINVAL; 306 } 307 308 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 309 struct kvm_sregs *sregs) 310 { 311 return -EINVAL; 312 } 313 314 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 315 { 316 return -EINVAL; 317 } 318 319 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 320 { 321 return -EINVAL; 322 } 323 324 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 325 struct kvm_translation *tr) 326 { 327 return -EINVAL; 328 } 329 330 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 331 { 332 return -EINVAL; 333 } 334 335 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 336 { 337 return -EINVAL; 338 } 339 340 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu) 341 { 342 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 343 unsigned long mask, val; 344 345 if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) { 346 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0); 347 val = READ_ONCE(vcpu->arch.irqs_pending[0]) & mask; 348 349 csr->hvip &= ~mask; 350 csr->hvip |= val; 351 } 352 353 /* Flush AIA high interrupts */ 354 kvm_riscv_vcpu_aia_flush_interrupts(vcpu); 355 } 356 357 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) 358 { 359 unsigned long hvip; 360 struct kvm_vcpu_arch *v = &vcpu->arch; 361 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 362 363 /* Read current HVIP and VSIE CSRs */ 364 csr->vsie = csr_read(CSR_VSIE); 365 366 /* Sync-up HVIP.VSSIP bit changes does by Guest */ 367 hvip = csr_read(CSR_HVIP); 368 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) { 369 if (hvip & (1UL << IRQ_VS_SOFT)) { 370 if (!test_and_set_bit(IRQ_VS_SOFT, 371 v->irqs_pending_mask)) 372 set_bit(IRQ_VS_SOFT, v->irqs_pending); 373 } else { 374 if (!test_and_set_bit(IRQ_VS_SOFT, 375 v->irqs_pending_mask)) 376 clear_bit(IRQ_VS_SOFT, v->irqs_pending); 377 } 378 } 379 380 /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ 381 if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { 382 if (!(hvip & (1UL << IRQ_PMU_OVF)) && 383 !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) 384 clear_bit(IRQ_PMU_OVF, v->irqs_pending); 385 } 386 387 /* Sync-up AIA high interrupts */ 388 kvm_riscv_vcpu_aia_sync_interrupts(vcpu); 389 390 /* Sync-up timer CSRs */ 391 kvm_riscv_vcpu_timer_sync(vcpu); 392 } 393 394 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 395 { 396 /* 397 * We only allow VS-mode software, timer, and external 398 * interrupts when irq is one of the local interrupts 399 * defined by RISC-V privilege specification. 400 */ 401 if (irq < IRQ_LOCAL_MAX && 402 irq != IRQ_VS_SOFT && 403 irq != IRQ_VS_TIMER && 404 irq != IRQ_VS_EXT && 405 irq != IRQ_PMU_OVF) 406 return -EINVAL; 407 408 set_bit(irq, vcpu->arch.irqs_pending); 409 smp_mb__before_atomic(); 410 set_bit(irq, vcpu->arch.irqs_pending_mask); 411 412 kvm_vcpu_kick(vcpu); 413 414 return 0; 415 } 416 417 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) 418 { 419 /* 420 * We only allow VS-mode software, timer, counter overflow and external 421 * interrupts when irq is one of the local interrupts 422 * defined by RISC-V privilege specification. 423 */ 424 if (irq < IRQ_LOCAL_MAX && 425 irq != IRQ_VS_SOFT && 426 irq != IRQ_VS_TIMER && 427 irq != IRQ_VS_EXT && 428 irq != IRQ_PMU_OVF) 429 return -EINVAL; 430 431 clear_bit(irq, vcpu->arch.irqs_pending); 432 smp_mb__before_atomic(); 433 set_bit(irq, vcpu->arch.irqs_pending_mask); 434 435 return 0; 436 } 437 438 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask) 439 { 440 unsigned long ie; 441 442 ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK) 443 << VSIP_TO_HVIP_SHIFT) & (unsigned long)mask; 444 ie |= vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK & 445 (unsigned long)mask; 446 if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie) 447 return true; 448 449 /* Check AIA high interrupts */ 450 return kvm_riscv_vcpu_aia_has_interrupts(vcpu, mask); 451 } 452 453 void __kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 454 { 455 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_STOPPED); 456 kvm_make_request(KVM_REQ_SLEEP, vcpu); 457 kvm_vcpu_kick(vcpu); 458 } 459 460 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu) 461 { 462 spin_lock(&vcpu->arch.mp_state_lock); 463 __kvm_riscv_vcpu_power_off(vcpu); 464 spin_unlock(&vcpu->arch.mp_state_lock); 465 } 466 467 void __kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 468 { 469 WRITE_ONCE(vcpu->arch.mp_state.mp_state, KVM_MP_STATE_RUNNABLE); 470 kvm_vcpu_wake_up(vcpu); 471 } 472 473 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu) 474 { 475 spin_lock(&vcpu->arch.mp_state_lock); 476 __kvm_riscv_vcpu_power_on(vcpu); 477 spin_unlock(&vcpu->arch.mp_state_lock); 478 } 479 480 bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu) 481 { 482 return READ_ONCE(vcpu->arch.mp_state.mp_state) == KVM_MP_STATE_STOPPED; 483 } 484 485 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 486 struct kvm_mp_state *mp_state) 487 { 488 *mp_state = READ_ONCE(vcpu->arch.mp_state); 489 490 return 0; 491 } 492 493 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 494 struct kvm_mp_state *mp_state) 495 { 496 int ret = 0; 497 498 spin_lock(&vcpu->arch.mp_state_lock); 499 500 switch (mp_state->mp_state) { 501 case KVM_MP_STATE_RUNNABLE: 502 WRITE_ONCE(vcpu->arch.mp_state, *mp_state); 503 break; 504 case KVM_MP_STATE_STOPPED: 505 __kvm_riscv_vcpu_power_off(vcpu); 506 break; 507 default: 508 ret = -EINVAL; 509 } 510 511 spin_unlock(&vcpu->arch.mp_state_lock); 512 513 return ret; 514 } 515 516 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 517 struct kvm_guest_debug *dbg) 518 { 519 if (dbg->control & KVM_GUESTDBG_ENABLE) { 520 vcpu->guest_debug = dbg->control; 521 vcpu->arch.cfg.hedeleg &= ~BIT(EXC_BREAKPOINT); 522 } else { 523 vcpu->guest_debug = 0; 524 vcpu->arch.cfg.hedeleg |= BIT(EXC_BREAKPOINT); 525 } 526 527 return 0; 528 } 529 530 static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) 531 { 532 const unsigned long *isa = vcpu->arch.isa; 533 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 534 535 if (riscv_isa_extension_available(isa, SVPBMT)) 536 cfg->henvcfg |= ENVCFG_PBMTE; 537 538 if (riscv_isa_extension_available(isa, SSTC)) 539 cfg->henvcfg |= ENVCFG_STCE; 540 541 if (riscv_isa_extension_available(isa, ZICBOM)) 542 cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); 543 544 if (riscv_isa_extension_available(isa, ZICBOZ)) 545 cfg->henvcfg |= ENVCFG_CBZE; 546 547 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { 548 cfg->hstateen0 |= SMSTATEEN0_HSENVCFG; 549 if (riscv_isa_extension_available(isa, SSAIA)) 550 cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC | 551 SMSTATEEN0_AIA | 552 SMSTATEEN0_AIA_ISEL; 553 if (riscv_isa_extension_available(isa, SMSTATEEN)) 554 cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0; 555 } 556 557 cfg->hedeleg = KVM_HEDELEG_DEFAULT; 558 if (vcpu->guest_debug) 559 cfg->hedeleg &= ~BIT(EXC_BREAKPOINT); 560 } 561 562 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 563 { 564 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 565 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 566 567 csr_write(CSR_VSSTATUS, csr->vsstatus); 568 csr_write(CSR_VSIE, csr->vsie); 569 csr_write(CSR_VSTVEC, csr->vstvec); 570 csr_write(CSR_VSSCRATCH, csr->vsscratch); 571 csr_write(CSR_VSEPC, csr->vsepc); 572 csr_write(CSR_VSCAUSE, csr->vscause); 573 csr_write(CSR_VSTVAL, csr->vstval); 574 csr_write(CSR_HEDELEG, cfg->hedeleg); 575 csr_write(CSR_HVIP, csr->hvip); 576 csr_write(CSR_VSATP, csr->vsatp); 577 csr_write(CSR_HENVCFG, cfg->henvcfg); 578 if (IS_ENABLED(CONFIG_32BIT)) 579 csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); 580 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { 581 csr_write(CSR_HSTATEEN0, cfg->hstateen0); 582 if (IS_ENABLED(CONFIG_32BIT)) 583 csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32); 584 } 585 586 kvm_riscv_gstage_update_hgatp(vcpu); 587 588 kvm_riscv_vcpu_timer_restore(vcpu); 589 590 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); 591 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, 592 vcpu->arch.isa); 593 kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); 594 kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, 595 vcpu->arch.isa); 596 597 kvm_riscv_vcpu_aia_load(vcpu, cpu); 598 599 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 600 601 vcpu->cpu = cpu; 602 } 603 604 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 605 { 606 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 607 608 vcpu->cpu = -1; 609 610 kvm_riscv_vcpu_aia_put(vcpu); 611 612 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context, 613 vcpu->arch.isa); 614 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); 615 616 kvm_riscv_vcpu_timer_save(vcpu); 617 kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, 618 vcpu->arch.isa); 619 kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); 620 621 csr->vsstatus = csr_read(CSR_VSSTATUS); 622 csr->vsie = csr_read(CSR_VSIE); 623 csr->vstvec = csr_read(CSR_VSTVEC); 624 csr->vsscratch = csr_read(CSR_VSSCRATCH); 625 csr->vsepc = csr_read(CSR_VSEPC); 626 csr->vscause = csr_read(CSR_VSCAUSE); 627 csr->vstval = csr_read(CSR_VSTVAL); 628 csr->hvip = csr_read(CSR_HVIP); 629 csr->vsatp = csr_read(CSR_VSATP); 630 } 631 632 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu) 633 { 634 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu); 635 636 if (kvm_request_pending(vcpu)) { 637 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) { 638 kvm_vcpu_srcu_read_unlock(vcpu); 639 rcuwait_wait_event(wait, 640 (!kvm_riscv_vcpu_stopped(vcpu)) && (!vcpu->arch.pause), 641 TASK_INTERRUPTIBLE); 642 kvm_vcpu_srcu_read_lock(vcpu); 643 644 if (kvm_riscv_vcpu_stopped(vcpu) || vcpu->arch.pause) { 645 /* 646 * Awaken to handle a signal, request to 647 * sleep again later. 648 */ 649 kvm_make_request(KVM_REQ_SLEEP, vcpu); 650 } 651 } 652 653 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu)) 654 kvm_riscv_reset_vcpu(vcpu); 655 656 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu)) 657 kvm_riscv_gstage_update_hgatp(vcpu); 658 659 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu)) 660 kvm_riscv_fence_i_process(vcpu); 661 662 /* 663 * The generic KVM_REQ_TLB_FLUSH is same as 664 * KVM_REQ_HFENCE_GVMA_VMID_ALL 665 */ 666 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu)) 667 kvm_riscv_hfence_gvma_vmid_all_process(vcpu); 668 669 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu)) 670 kvm_riscv_hfence_vvma_all_process(vcpu); 671 672 if (kvm_check_request(KVM_REQ_HFENCE, vcpu)) 673 kvm_riscv_hfence_process(vcpu); 674 675 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 676 kvm_riscv_vcpu_record_steal_time(vcpu); 677 } 678 } 679 680 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) 681 { 682 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 683 684 csr_write(CSR_HVIP, csr->hvip); 685 kvm_riscv_vcpu_aia_update_hvip(vcpu); 686 } 687 688 static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu) 689 { 690 struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; 691 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 692 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 693 694 vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg); 695 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && 696 (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) 697 vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0, 698 smcsr->sstateen0); 699 } 700 701 static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu) 702 { 703 struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; 704 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; 705 struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; 706 707 csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); 708 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && 709 (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) 710 smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0, 711 vcpu->arch.host_sstateen0); 712 } 713 714 /* 715 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while 716 * the vCPU is running. 717 * 718 * This must be noinstr as instrumentation may make use of RCU, and this is not 719 * safe during the EQS. 720 */ 721 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) 722 { 723 kvm_riscv_vcpu_swap_in_guest_state(vcpu); 724 guest_state_enter_irqoff(); 725 __kvm_riscv_switch_to(&vcpu->arch); 726 vcpu->arch.last_exit_cpu = vcpu->cpu; 727 guest_state_exit_irqoff(); 728 kvm_riscv_vcpu_swap_in_host_state(vcpu); 729 } 730 731 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 732 { 733 int ret; 734 struct kvm_cpu_trap trap; 735 struct kvm_run *run = vcpu->run; 736 737 if (!vcpu->arch.ran_atleast_once) 738 kvm_riscv_vcpu_setup_config(vcpu); 739 740 /* Mark this VCPU ran at least once */ 741 vcpu->arch.ran_atleast_once = true; 742 743 kvm_vcpu_srcu_read_lock(vcpu); 744 745 switch (run->exit_reason) { 746 case KVM_EXIT_MMIO: 747 /* Process MMIO value returned from user-space */ 748 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run); 749 break; 750 case KVM_EXIT_RISCV_SBI: 751 /* Process SBI value returned from user-space */ 752 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run); 753 break; 754 case KVM_EXIT_RISCV_CSR: 755 /* Process CSR value returned from user-space */ 756 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run); 757 break; 758 default: 759 ret = 0; 760 break; 761 } 762 if (ret) { 763 kvm_vcpu_srcu_read_unlock(vcpu); 764 return ret; 765 } 766 767 if (!vcpu->wants_to_run) { 768 kvm_vcpu_srcu_read_unlock(vcpu); 769 return -EINTR; 770 } 771 772 vcpu_load(vcpu); 773 774 kvm_sigset_activate(vcpu); 775 776 ret = 1; 777 run->exit_reason = KVM_EXIT_UNKNOWN; 778 while (ret > 0) { 779 /* Check conditions before entering the guest */ 780 ret = xfer_to_guest_mode_handle_work(vcpu); 781 if (ret) 782 continue; 783 ret = 1; 784 785 kvm_riscv_gstage_vmid_update(vcpu); 786 787 kvm_riscv_check_vcpu_requests(vcpu); 788 789 preempt_disable(); 790 791 /* Update AIA HW state before entering guest */ 792 ret = kvm_riscv_vcpu_aia_update(vcpu); 793 if (ret <= 0) { 794 preempt_enable(); 795 continue; 796 } 797 798 local_irq_disable(); 799 800 /* 801 * Ensure we set mode to IN_GUEST_MODE after we disable 802 * interrupts and before the final VCPU requests check. 803 * See the comment in kvm_vcpu_exiting_guest_mode() and 804 * Documentation/virt/kvm/vcpu-requests.rst 805 */ 806 vcpu->mode = IN_GUEST_MODE; 807 808 kvm_vcpu_srcu_read_unlock(vcpu); 809 smp_mb__after_srcu_read_unlock(); 810 811 /* 812 * We might have got VCPU interrupts updated asynchronously 813 * so update it in HW. 814 */ 815 kvm_riscv_vcpu_flush_interrupts(vcpu); 816 817 /* Update HVIP CSR for current CPU */ 818 kvm_riscv_update_hvip(vcpu); 819 820 if (kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) || 821 kvm_request_pending(vcpu) || 822 xfer_to_guest_mode_work_pending()) { 823 vcpu->mode = OUTSIDE_GUEST_MODE; 824 local_irq_enable(); 825 preempt_enable(); 826 kvm_vcpu_srcu_read_lock(vcpu); 827 continue; 828 } 829 830 /* 831 * Cleanup stale TLB enteries 832 * 833 * Note: This should be done after G-stage VMID has been 834 * updated using kvm_riscv_gstage_vmid_ver_changed() 835 */ 836 kvm_riscv_local_tlb_sanitize(vcpu); 837 838 trace_kvm_entry(vcpu); 839 840 guest_timing_enter_irqoff(); 841 842 kvm_riscv_vcpu_enter_exit(vcpu); 843 844 vcpu->mode = OUTSIDE_GUEST_MODE; 845 vcpu->stat.exits++; 846 847 /* 848 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might 849 * get an interrupt between __kvm_riscv_switch_to() and 850 * local_irq_enable() which can potentially change CSRs. 851 */ 852 trap.sepc = vcpu->arch.guest_context.sepc; 853 trap.scause = csr_read(CSR_SCAUSE); 854 trap.stval = csr_read(CSR_STVAL); 855 trap.htval = csr_read(CSR_HTVAL); 856 trap.htinst = csr_read(CSR_HTINST); 857 858 /* Syncup interrupts state with HW */ 859 kvm_riscv_vcpu_sync_interrupts(vcpu); 860 861 /* 862 * We must ensure that any pending interrupts are taken before 863 * we exit guest timing so that timer ticks are accounted as 864 * guest time. Transiently unmask interrupts so that any 865 * pending interrupts are taken. 866 * 867 * There's no barrier which ensures that pending interrupts are 868 * recognised, so we just hope that the CPU takes any pending 869 * interrupts between the enable and disable. 870 */ 871 local_irq_enable(); 872 local_irq_disable(); 873 874 guest_timing_exit_irqoff(); 875 876 local_irq_enable(); 877 878 trace_kvm_exit(&trap); 879 880 preempt_enable(); 881 882 kvm_vcpu_srcu_read_lock(vcpu); 883 884 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap); 885 } 886 887 kvm_sigset_deactivate(vcpu); 888 889 vcpu_put(vcpu); 890 891 kvm_vcpu_srcu_read_unlock(vcpu); 892 893 return ret; 894 } 895