1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 4 * Copyright (C) 2022 Ventana Micro Systems Inc. 5 * 6 * Authors: 7 * Anup Patel <apatel@ventanamicro.com> 8 */ 9 10 #include <linux/bits.h> 11 #include <linux/irqchip/riscv-imsic.h> 12 #include <linux/kvm_host.h> 13 #include <linux/uaccess.h> 14 #include <asm/kvm_isa.h> 15 16 static int aia_create(struct kvm_device *dev, u32 type) 17 { 18 int ret; 19 unsigned long i; 20 struct kvm *kvm = dev->kvm; 21 struct kvm_vcpu *vcpu; 22 23 if (irqchip_in_kernel(kvm)) 24 return -EEXIST; 25 26 if (kvm_riscv_isa_check_host(SSAIA)) 27 return -ENODEV; 28 29 ret = -EBUSY; 30 if (kvm_trylock_all_vcpus(kvm)) 31 return ret; 32 33 kvm_for_each_vcpu(i, vcpu, kvm) { 34 if (vcpu->arch.ran_atleast_once) 35 goto out_unlock; 36 } 37 ret = 0; 38 39 kvm->arch.aia.in_kernel = true; 40 41 out_unlock: 42 kvm_unlock_all_vcpus(kvm); 43 return ret; 44 } 45 46 static void aia_destroy(struct kvm_device *dev) 47 { 48 kfree(dev); 49 } 50 51 static int aia_config(struct kvm *kvm, unsigned long type, 52 u32 *nr, bool write) 53 { 54 struct kvm_aia *aia = &kvm->arch.aia; 55 56 /* Writes can only be done before irqchip is initialized */ 57 if (write && kvm_riscv_aia_initialized(kvm)) 58 return -EBUSY; 59 60 switch (type) { 61 case KVM_DEV_RISCV_AIA_CONFIG_MODE: 62 if (write) { 63 switch (*nr) { 64 case KVM_DEV_RISCV_AIA_MODE_EMUL: 65 break; 66 case KVM_DEV_RISCV_AIA_MODE_HWACCEL: 67 case KVM_DEV_RISCV_AIA_MODE_AUTO: 68 /* 69 * HW Acceleration and Auto modes only 70 * supported on host with non-zero guest 71 * external interrupts (i.e. non-zero 72 * VS-level IMSIC pages). 73 */ 74 if (!atomic_read(&kvm_riscv_aia_nr_hgei)) 75 return -EINVAL; 76 break; 77 default: 78 return -EINVAL; 79 } 80 aia->mode = *nr; 81 } else 82 *nr = aia->mode; 83 break; 84 case KVM_DEV_RISCV_AIA_CONFIG_IDS: 85 if (write) { 86 if ((*nr < KVM_DEV_RISCV_AIA_IDS_MIN) || 87 (*nr >= KVM_DEV_RISCV_AIA_IDS_MAX) || 88 ((*nr & KVM_DEV_RISCV_AIA_IDS_MIN) != 89 KVM_DEV_RISCV_AIA_IDS_MIN) || 90 (kvm_riscv_aia_max_ids <= *nr)) 91 return -EINVAL; 92 aia->nr_ids = *nr; 93 } else 94 *nr = aia->nr_ids; 95 break; 96 case KVM_DEV_RISCV_AIA_CONFIG_SRCS: 97 if (write) { 98 if ((*nr >= KVM_DEV_RISCV_AIA_SRCS_MAX) || 99 (*nr >= kvm_riscv_aia_max_ids)) 100 return -EINVAL; 101 aia->nr_sources = *nr; 102 } else 103 *nr = aia->nr_sources; 104 break; 105 case KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS: 106 if (write) { 107 if (*nr >= KVM_DEV_RISCV_AIA_GROUP_BITS_MAX) 108 return -EINVAL; 109 aia->nr_group_bits = *nr; 110 } else 111 *nr = aia->nr_group_bits; 112 break; 113 case KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT: 114 if (write) { 115 if ((*nr < KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN) || 116 (*nr >= KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX)) 117 return -EINVAL; 118 aia->nr_group_shift = *nr; 119 } else 120 *nr = aia->nr_group_shift; 121 break; 122 case KVM_DEV_RISCV_AIA_CONFIG_HART_BITS: 123 if (write) { 124 if (*nr >= KVM_DEV_RISCV_AIA_HART_BITS_MAX) 125 return -EINVAL; 126 aia->nr_hart_bits = *nr; 127 } else 128 *nr = aia->nr_hart_bits; 129 break; 130 case KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS: 131 if (write) { 132 if (*nr >= KVM_DEV_RISCV_AIA_GUEST_BITS_MAX) 133 return -EINVAL; 134 aia->nr_guest_bits = *nr; 135 } else 136 *nr = aia->nr_guest_bits; 137 break; 138 default: 139 return -ENXIO; 140 } 141 142 return 0; 143 } 144 145 static int aia_aplic_addr(struct kvm *kvm, u64 *addr, bool write) 146 { 147 struct kvm_aia *aia = &kvm->arch.aia; 148 149 if (write) { 150 /* Writes can only be done before irqchip is initialized */ 151 if (kvm_riscv_aia_initialized(kvm)) 152 return -EBUSY; 153 154 if (*addr & (KVM_DEV_RISCV_APLIC_ALIGN - 1)) 155 return -EINVAL; 156 157 aia->aplic_addr = *addr; 158 } else 159 *addr = aia->aplic_addr; 160 161 return 0; 162 } 163 164 static int aia_imsic_addr(struct kvm *kvm, u64 *addr, 165 unsigned long vcpu_idx, bool write) 166 { 167 struct kvm_vcpu *vcpu; 168 struct kvm_vcpu_aia *vcpu_aia; 169 170 vcpu = kvm_get_vcpu(kvm, vcpu_idx); 171 if (!vcpu) 172 return -EINVAL; 173 vcpu_aia = &vcpu->arch.aia_context; 174 175 if (write) { 176 /* Writes can only be done before irqchip is initialized */ 177 if (kvm_riscv_aia_initialized(kvm)) 178 return -EBUSY; 179 180 if (*addr & (KVM_DEV_RISCV_IMSIC_ALIGN - 1)) 181 return -EINVAL; 182 } 183 184 mutex_lock(&vcpu->mutex); 185 if (write) 186 vcpu_aia->imsic_addr = *addr; 187 else 188 *addr = vcpu_aia->imsic_addr; 189 mutex_unlock(&vcpu->mutex); 190 191 return 0; 192 } 193 194 static gpa_t aia_imsic_ppn(struct kvm_aia *aia, gpa_t addr) 195 { 196 u32 h, l; 197 gpa_t mask = 0; 198 199 h = aia->nr_hart_bits + aia->nr_guest_bits + 200 IMSIC_MMIO_PAGE_SHIFT - 1; 201 mask = GENMASK_ULL(h, 0); 202 203 if (aia->nr_group_bits) { 204 h = aia->nr_group_bits + aia->nr_group_shift - 1; 205 l = aia->nr_group_shift; 206 mask |= GENMASK_ULL(h, l); 207 } 208 209 return (addr & ~mask) >> IMSIC_MMIO_PAGE_SHIFT; 210 } 211 212 static u32 aia_imsic_hart_index(struct kvm_aia *aia, gpa_t addr) 213 { 214 u32 hart = 0, group = 0; 215 216 if (aia->nr_hart_bits) 217 hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) & 218 GENMASK_ULL(aia->nr_hart_bits - 1, 0); 219 if (aia->nr_group_bits) 220 group = (addr >> aia->nr_group_shift) & 221 GENMASK_ULL(aia->nr_group_bits - 1, 0); 222 223 return (group << aia->nr_hart_bits) | hart; 224 } 225 226 static int aia_init(struct kvm *kvm) 227 { 228 int ret, i; 229 unsigned long idx; 230 struct kvm_vcpu *vcpu; 231 struct kvm_vcpu_aia *vaia; 232 struct kvm_aia *aia = &kvm->arch.aia; 233 gpa_t base_ppn = KVM_RISCV_AIA_UNDEF_ADDR; 234 235 /* Irqchip can be initialized only once */ 236 if (kvm_riscv_aia_initialized(kvm)) 237 return -EBUSY; 238 239 /* We might be in the middle of creating a VCPU? */ 240 if (kvm->created_vcpus != atomic_read(&kvm->online_vcpus)) 241 return -EBUSY; 242 243 /* Number of sources should be less than or equals number of IDs */ 244 if (aia->nr_ids < aia->nr_sources) 245 return -EINVAL; 246 247 /* APLIC base is required for non-zero number of sources */ 248 if (aia->nr_sources && aia->aplic_addr == KVM_RISCV_AIA_UNDEF_ADDR) 249 return -EINVAL; 250 251 /* Group index bits must not overlap guest and HART index bits. */ 252 if (aia->nr_group_bits && 253 aia->nr_group_shift < (IMSIC_MMIO_PAGE_SHIFT + 254 aia->nr_guest_bits + aia->nr_hart_bits)) 255 return -EINVAL; 256 257 /* Initialize APLIC */ 258 ret = kvm_riscv_aia_aplic_init(kvm); 259 if (ret) 260 return ret; 261 262 /* Iterate over each VCPU */ 263 kvm_for_each_vcpu(idx, vcpu, kvm) { 264 vaia = &vcpu->arch.aia_context; 265 266 /* IMSIC base is required */ 267 if (vaia->imsic_addr == KVM_RISCV_AIA_UNDEF_ADDR) { 268 ret = -EINVAL; 269 goto fail_cleanup_imsics; 270 } 271 272 /* All IMSICs should have matching base PPN */ 273 if (base_ppn == KVM_RISCV_AIA_UNDEF_ADDR) 274 base_ppn = aia_imsic_ppn(aia, vaia->imsic_addr); 275 if (base_ppn != aia_imsic_ppn(aia, vaia->imsic_addr)) { 276 ret = -EINVAL; 277 goto fail_cleanup_imsics; 278 } 279 280 /* Update HART index of the IMSIC based on IMSIC base */ 281 vaia->hart_index = aia_imsic_hart_index(aia, 282 vaia->imsic_addr); 283 284 /* Initialize IMSIC for this VCPU */ 285 ret = kvm_riscv_vcpu_aia_imsic_init(vcpu); 286 if (ret) 287 goto fail_cleanup_imsics; 288 } 289 290 /* Set the initialized flag */ 291 kvm->arch.aia.initialized = true; 292 293 return 0; 294 295 fail_cleanup_imsics: 296 for (i = idx - 1; i >= 0; i--) { 297 vcpu = kvm_get_vcpu(kvm, i); 298 if (!vcpu) 299 continue; 300 kvm_riscv_vcpu_aia_imsic_cleanup(vcpu); 301 } 302 kvm_riscv_aia_aplic_cleanup(kvm); 303 return ret; 304 } 305 306 static int aia_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) 307 { 308 u32 nr; 309 u64 addr; 310 int nr_vcpus, r = -ENXIO; 311 unsigned long v, type = (unsigned long)attr->attr; 312 void __user *uaddr = (void __user *)(long)attr->addr; 313 314 switch (attr->group) { 315 case KVM_DEV_RISCV_AIA_GRP_CONFIG: 316 if (copy_from_user(&nr, uaddr, sizeof(nr))) 317 return -EFAULT; 318 319 mutex_lock(&dev->kvm->lock); 320 r = aia_config(dev->kvm, type, &nr, true); 321 mutex_unlock(&dev->kvm->lock); 322 323 break; 324 325 case KVM_DEV_RISCV_AIA_GRP_ADDR: 326 if (copy_from_user(&addr, uaddr, sizeof(addr))) 327 return -EFAULT; 328 329 nr_vcpus = atomic_read(&dev->kvm->online_vcpus); 330 mutex_lock(&dev->kvm->lock); 331 if (type == KVM_DEV_RISCV_AIA_ADDR_APLIC) 332 r = aia_aplic_addr(dev->kvm, &addr, true); 333 else if (type < KVM_DEV_RISCV_AIA_ADDR_IMSIC(nr_vcpus)) 334 r = aia_imsic_addr(dev->kvm, &addr, 335 type - KVM_DEV_RISCV_AIA_ADDR_IMSIC(0), true); 336 mutex_unlock(&dev->kvm->lock); 337 338 break; 339 340 case KVM_DEV_RISCV_AIA_GRP_CTRL: 341 switch (type) { 342 case KVM_DEV_RISCV_AIA_CTRL_INIT: 343 mutex_lock(&dev->kvm->lock); 344 r = aia_init(dev->kvm); 345 mutex_unlock(&dev->kvm->lock); 346 break; 347 } 348 349 break; 350 case KVM_DEV_RISCV_AIA_GRP_APLIC: 351 if (copy_from_user(&nr, uaddr, sizeof(nr))) 352 return -EFAULT; 353 354 mutex_lock(&dev->kvm->lock); 355 r = kvm_riscv_aia_aplic_set_attr(dev->kvm, type, nr); 356 mutex_unlock(&dev->kvm->lock); 357 358 break; 359 case KVM_DEV_RISCV_AIA_GRP_IMSIC: 360 if (copy_from_user(&v, uaddr, sizeof(v))) 361 return -EFAULT; 362 363 mutex_lock(&dev->kvm->lock); 364 r = kvm_riscv_aia_imsic_rw_attr(dev->kvm, type, true, &v); 365 mutex_unlock(&dev->kvm->lock); 366 367 break; 368 } 369 370 return r; 371 } 372 373 static int aia_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) 374 { 375 u32 nr; 376 u64 addr; 377 int nr_vcpus, r = -ENXIO; 378 void __user *uaddr = (void __user *)(long)attr->addr; 379 unsigned long v, type = (unsigned long)attr->attr; 380 381 switch (attr->group) { 382 case KVM_DEV_RISCV_AIA_GRP_CONFIG: 383 if (copy_from_user(&nr, uaddr, sizeof(nr))) 384 return -EFAULT; 385 386 mutex_lock(&dev->kvm->lock); 387 r = aia_config(dev->kvm, type, &nr, false); 388 mutex_unlock(&dev->kvm->lock); 389 if (r) 390 return r; 391 392 if (copy_to_user(uaddr, &nr, sizeof(nr))) 393 return -EFAULT; 394 395 break; 396 case KVM_DEV_RISCV_AIA_GRP_ADDR: 397 if (copy_from_user(&addr, uaddr, sizeof(addr))) 398 return -EFAULT; 399 400 nr_vcpus = atomic_read(&dev->kvm->online_vcpus); 401 mutex_lock(&dev->kvm->lock); 402 if (type == KVM_DEV_RISCV_AIA_ADDR_APLIC) 403 r = aia_aplic_addr(dev->kvm, &addr, false); 404 else if (type < KVM_DEV_RISCV_AIA_ADDR_IMSIC(nr_vcpus)) 405 r = aia_imsic_addr(dev->kvm, &addr, 406 type - KVM_DEV_RISCV_AIA_ADDR_IMSIC(0), false); 407 mutex_unlock(&dev->kvm->lock); 408 if (r) 409 return r; 410 411 if (copy_to_user(uaddr, &addr, sizeof(addr))) 412 return -EFAULT; 413 414 break; 415 case KVM_DEV_RISCV_AIA_GRP_APLIC: 416 if (copy_from_user(&nr, uaddr, sizeof(nr))) 417 return -EFAULT; 418 419 mutex_lock(&dev->kvm->lock); 420 r = kvm_riscv_aia_aplic_get_attr(dev->kvm, type, &nr); 421 mutex_unlock(&dev->kvm->lock); 422 if (r) 423 return r; 424 425 if (copy_to_user(uaddr, &nr, sizeof(nr))) 426 return -EFAULT; 427 428 break; 429 case KVM_DEV_RISCV_AIA_GRP_IMSIC: 430 if (copy_from_user(&v, uaddr, sizeof(v))) 431 return -EFAULT; 432 433 mutex_lock(&dev->kvm->lock); 434 r = kvm_riscv_aia_imsic_rw_attr(dev->kvm, type, false, &v); 435 mutex_unlock(&dev->kvm->lock); 436 if (r) 437 return r; 438 439 if (copy_to_user(uaddr, &v, sizeof(v))) 440 return -EFAULT; 441 442 break; 443 } 444 445 return r; 446 } 447 448 static int aia_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) 449 { 450 int nr_vcpus, r = -ENXIO; 451 452 switch (attr->group) { 453 case KVM_DEV_RISCV_AIA_GRP_CONFIG: 454 switch (attr->attr) { 455 case KVM_DEV_RISCV_AIA_CONFIG_MODE: 456 case KVM_DEV_RISCV_AIA_CONFIG_IDS: 457 case KVM_DEV_RISCV_AIA_CONFIG_SRCS: 458 case KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS: 459 case KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT: 460 case KVM_DEV_RISCV_AIA_CONFIG_HART_BITS: 461 case KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS: 462 return 0; 463 } 464 break; 465 case KVM_DEV_RISCV_AIA_GRP_ADDR: 466 nr_vcpus = atomic_read(&dev->kvm->online_vcpus); 467 if (attr->attr == KVM_DEV_RISCV_AIA_ADDR_APLIC) 468 return 0; 469 else if (attr->attr < KVM_DEV_RISCV_AIA_ADDR_IMSIC(nr_vcpus)) 470 return 0; 471 break; 472 case KVM_DEV_RISCV_AIA_GRP_CTRL: 473 switch (attr->attr) { 474 case KVM_DEV_RISCV_AIA_CTRL_INIT: 475 return 0; 476 } 477 break; 478 case KVM_DEV_RISCV_AIA_GRP_APLIC: 479 mutex_lock(&dev->kvm->lock); 480 r = kvm_riscv_aia_aplic_has_attr(dev->kvm, attr->attr); 481 mutex_unlock(&dev->kvm->lock); 482 break; 483 case KVM_DEV_RISCV_AIA_GRP_IMSIC: 484 mutex_lock(&dev->kvm->lock); 485 r = kvm_riscv_aia_imsic_has_attr(dev->kvm, attr->attr); 486 mutex_unlock(&dev->kvm->lock); 487 break; 488 } 489 490 return r; 491 } 492 493 struct kvm_device_ops kvm_riscv_aia_device_ops = { 494 .name = "kvm-riscv-aia", 495 .create = aia_create, 496 .destroy = aia_destroy, 497 .set_attr = aia_set_attr, 498 .get_attr = aia_get_attr, 499 .has_attr = aia_has_attr, 500 }; 501 502 int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu) 503 { 504 /* Proceed only if AIA was initialized successfully */ 505 if (!kvm_riscv_aia_initialized(vcpu->kvm)) 506 return 1; 507 508 /* Update the IMSIC HW state before entering guest mode */ 509 return kvm_riscv_vcpu_aia_imsic_update(vcpu); 510 } 511 512 void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu) 513 { 514 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; 515 516 if (!kvm_riscv_aia_available()) 517 return; 518 memset(csr, 0, sizeof(*csr)); 519 520 /* Proceed only if AIA was initialized successfully */ 521 if (!kvm_riscv_aia_initialized(vcpu->kvm)) 522 return; 523 524 /* Reset the IMSIC context */ 525 kvm_riscv_vcpu_aia_imsic_reset(vcpu); 526 } 527 528 void kvm_riscv_vcpu_aia_init(struct kvm_vcpu *vcpu) 529 { 530 struct kvm_vcpu_aia *vaia = &vcpu->arch.aia_context; 531 532 if (!kvm_riscv_aia_available()) 533 return; 534 535 /* 536 * We don't do any memory allocations over here because these 537 * will be done after AIA device is initialized by the user-space. 538 * 539 * Refer, aia_init() implementation for more details. 540 */ 541 542 /* Initialize default values in AIA vcpu context */ 543 vaia->imsic_addr = KVM_RISCV_AIA_UNDEF_ADDR; 544 vaia->hart_index = vcpu->vcpu_idx; 545 } 546 547 void kvm_riscv_vcpu_aia_deinit(struct kvm_vcpu *vcpu) 548 { 549 /* Proceed only if AIA was initialized successfully */ 550 if (!kvm_riscv_aia_initialized(vcpu->kvm)) 551 return; 552 553 /* Cleanup IMSIC context */ 554 kvm_riscv_vcpu_aia_imsic_cleanup(vcpu); 555 } 556 557 int kvm_riscv_aia_inject_msi_by_id(struct kvm *kvm, u32 hart_index, 558 u32 guest_index, u32 iid) 559 { 560 unsigned long idx; 561 struct kvm_vcpu *vcpu; 562 563 /* Proceed only if AIA was initialized successfully */ 564 if (!kvm_riscv_aia_initialized(kvm)) 565 return -EBUSY; 566 567 /* Inject MSI to matching VCPU */ 568 kvm_for_each_vcpu(idx, vcpu, kvm) { 569 if (vcpu->arch.aia_context.hart_index == hart_index) 570 return kvm_riscv_vcpu_aia_imsic_inject(vcpu, 571 guest_index, 572 0, iid); 573 } 574 575 return 0; 576 } 577 578 int kvm_riscv_aia_inject_msi(struct kvm *kvm, struct kvm_msi *msi) 579 { 580 gpa_t tppn, ippn; 581 unsigned long idx; 582 struct kvm_vcpu *vcpu; 583 u32 g, toff, iid = msi->data; 584 struct kvm_aia *aia = &kvm->arch.aia; 585 gpa_t target = (((gpa_t)msi->address_hi) << 32) | msi->address_lo; 586 587 /* Proceed only if AIA was initialized successfully */ 588 if (!kvm_riscv_aia_initialized(kvm)) 589 return -EBUSY; 590 591 /* Convert target address to target PPN */ 592 tppn = target >> IMSIC_MMIO_PAGE_SHIFT; 593 594 /* Extract and clear Guest ID from target PPN */ 595 g = tppn & (BIT(aia->nr_guest_bits) - 1); 596 tppn &= ~((gpa_t)(BIT(aia->nr_guest_bits) - 1)); 597 598 /* Inject MSI to matching VCPU */ 599 kvm_for_each_vcpu(idx, vcpu, kvm) { 600 ippn = vcpu->arch.aia_context.imsic_addr >> 601 IMSIC_MMIO_PAGE_SHIFT; 602 if (ippn == tppn) { 603 toff = target & (IMSIC_MMIO_PAGE_SZ - 1); 604 return kvm_riscv_vcpu_aia_imsic_inject(vcpu, g, 605 toff, iid); 606 } 607 } 608 609 return 0; 610 } 611 612 int kvm_riscv_aia_inject_irq(struct kvm *kvm, unsigned int irq, bool level) 613 { 614 /* Proceed only if AIA was initialized successfully */ 615 if (!kvm_riscv_aia_initialized(kvm)) 616 return -EBUSY; 617 618 /* Inject interrupt level change in APLIC */ 619 return kvm_riscv_aia_aplic_inject(kvm, irq, level); 620 } 621 622 void kvm_riscv_aia_init_vm(struct kvm *kvm) 623 { 624 struct kvm_aia *aia = &kvm->arch.aia; 625 626 if (!kvm_riscv_aia_available()) 627 return; 628 629 /* 630 * We don't do any memory allocations over here because these 631 * will be done after AIA device is initialized by the user-space. 632 * 633 * Refer, aia_init() implementation for more details. 634 */ 635 636 /* Initialize default values in AIA global context */ 637 aia->mode = (atomic_read(&kvm_riscv_aia_nr_hgei)) ? 638 KVM_DEV_RISCV_AIA_MODE_AUTO : KVM_DEV_RISCV_AIA_MODE_EMUL; 639 aia->nr_ids = kvm_riscv_aia_max_ids - 1; 640 aia->nr_sources = 0; 641 aia->nr_group_bits = 0; 642 aia->nr_group_shift = KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN; 643 aia->nr_hart_bits = 0; 644 aia->nr_guest_bits = 0; 645 aia->aplic_addr = KVM_RISCV_AIA_UNDEF_ADDR; 646 } 647 648 void kvm_riscv_aia_destroy_vm(struct kvm *kvm) 649 { 650 /* Proceed only if AIA was initialized successfully */ 651 if (!kvm_riscv_aia_initialized(kvm)) 652 return; 653 654 /* Cleanup APLIC context */ 655 kvm_riscv_aia_aplic_cleanup(kvm); 656 } 657