1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2023 SiFive 4 * Author: Andy Chiu <andy.chiu@sifive.com> 5 */ 6 #include <linux/export.h> 7 #include <linux/sched/signal.h> 8 #include <linux/types.h> 9 #include <linux/slab.h> 10 #include <linux/sched.h> 11 #include <linux/uaccess.h> 12 #include <linux/prctl.h> 13 14 #include <asm/thread_info.h> 15 #include <asm/processor.h> 16 #include <asm/insn.h> 17 #include <asm/vector.h> 18 #include <asm/csr.h> 19 #include <asm/elf.h> 20 #include <asm/ptrace.h> 21 #include <asm/bug.h> 22 23 static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE); 24 static struct kmem_cache *riscv_v_user_cachep; 25 #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 26 static struct kmem_cache *riscv_v_kernel_cachep; 27 #endif 28 29 unsigned long riscv_v_vsize __read_mostly; 30 EXPORT_SYMBOL_GPL(riscv_v_vsize); 31 32 int riscv_v_setup_vsize(void) 33 { 34 unsigned long this_vsize; 35 36 /* 37 * There are 32 vector registers with vlenb length. 38 * 39 * If the thead,vlenb property was provided by the firmware, use that 40 * instead of probing the CSRs. 41 */ 42 if (thead_vlenb_of) { 43 riscv_v_vsize = thead_vlenb_of * 32; 44 return 0; 45 } 46 47 riscv_v_enable(); 48 this_vsize = csr_read(CSR_VLENB) * 32; 49 riscv_v_disable(); 50 51 if (!riscv_v_vsize) { 52 riscv_v_vsize = this_vsize; 53 return 0; 54 } 55 56 if (riscv_v_vsize != this_vsize) { 57 WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); 58 return -EOPNOTSUPP; 59 } 60 61 return 0; 62 } 63 64 void __init riscv_v_setup_ctx_cache(void) 65 { 66 if (!(has_vector() || has_xtheadvector())) 67 return; 68 69 riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx", 70 riscv_v_vsize, 16, SLAB_PANIC, 71 0, riscv_v_vsize, NULL); 72 #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 73 riscv_v_kernel_cachep = kmem_cache_create("riscv_vector_kctx", 74 riscv_v_vsize, 16, 75 SLAB_PANIC, NULL); 76 #endif 77 } 78 79 bool insn_is_vector(u32 insn_buf) 80 { 81 u32 opcode = insn_buf & __INSN_OPCODE_MASK; 82 u32 width, csr; 83 84 /* 85 * All V-related instructions, including CSR operations are 4-Byte. So, 86 * do not handle if the instruction length is not 4-Byte. 87 */ 88 if (unlikely(GET_INSN_LENGTH(insn_buf) != 4)) 89 return false; 90 91 switch (opcode) { 92 case RVV_OPCODE_VECTOR: 93 return true; 94 case RVV_OPCODE_VL: 95 case RVV_OPCODE_VS: 96 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf); 97 if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 || 98 width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64) 99 return true; 100 101 break; 102 case RVG_OPCODE_SYSTEM: 103 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf); 104 if ((csr >= CSR_VSTART && csr <= CSR_VCSR) || 105 (csr >= CSR_VL && csr <= CSR_VLENB)) 106 return true; 107 } 108 109 return false; 110 } 111 112 static int riscv_v_thread_zalloc(struct kmem_cache *cache, 113 struct __riscv_v_ext_state *ctx) 114 { 115 void *datap; 116 117 datap = kmem_cache_zalloc(cache, GFP_KERNEL); 118 if (!datap) 119 return -ENOMEM; 120 121 ctx->datap = datap; 122 memset(ctx, 0, offsetof(struct __riscv_v_ext_state, datap)); 123 return 0; 124 } 125 126 void riscv_v_thread_alloc(struct task_struct *tsk) 127 { 128 #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 129 riscv_v_thread_zalloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate); 130 #endif 131 } 132 133 void riscv_v_thread_free(struct task_struct *tsk) 134 { 135 if (tsk->thread.vstate.datap) 136 kmem_cache_free(riscv_v_user_cachep, tsk->thread.vstate.datap); 137 #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE 138 if (tsk->thread.kernel_vstate.datap) 139 kmem_cache_free(riscv_v_kernel_cachep, tsk->thread.kernel_vstate.datap); 140 #endif 141 } 142 143 #define VSTATE_CTRL_GET_CUR(x) ((x) & PR_RISCV_V_VSTATE_CTRL_CUR_MASK) 144 #define VSTATE_CTRL_GET_NEXT(x) (((x) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) >> 2) 145 #define VSTATE_CTRL_MAKE_NEXT(x) (((x) << 2) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) 146 #define VSTATE_CTRL_GET_INHERIT(x) (!!((x) & PR_RISCV_V_VSTATE_CTRL_INHERIT)) 147 static inline int riscv_v_ctrl_get_cur(struct task_struct *tsk) 148 { 149 return VSTATE_CTRL_GET_CUR(tsk->thread.vstate_ctrl); 150 } 151 152 static inline int riscv_v_ctrl_get_next(struct task_struct *tsk) 153 { 154 return VSTATE_CTRL_GET_NEXT(tsk->thread.vstate_ctrl); 155 } 156 157 static inline bool riscv_v_ctrl_test_inherit(struct task_struct *tsk) 158 { 159 return VSTATE_CTRL_GET_INHERIT(tsk->thread.vstate_ctrl); 160 } 161 162 static inline void riscv_v_ctrl_set(struct task_struct *tsk, int cur, int nxt, 163 bool inherit) 164 { 165 unsigned long ctrl; 166 167 ctrl = cur & PR_RISCV_V_VSTATE_CTRL_CUR_MASK; 168 ctrl |= VSTATE_CTRL_MAKE_NEXT(nxt); 169 if (inherit) 170 ctrl |= PR_RISCV_V_VSTATE_CTRL_INHERIT; 171 tsk->thread.vstate_ctrl &= ~PR_RISCV_V_VSTATE_CTRL_MASK; 172 tsk->thread.vstate_ctrl |= ctrl; 173 } 174 175 bool riscv_v_vstate_ctrl_user_allowed(void) 176 { 177 return riscv_v_ctrl_get_cur(current) == PR_RISCV_V_VSTATE_CTRL_ON; 178 } 179 EXPORT_SYMBOL_GPL(riscv_v_vstate_ctrl_user_allowed); 180 181 bool riscv_v_first_use_handler(struct pt_regs *regs) 182 { 183 u32 __user *epc = (u32 __user *)regs->epc; 184 u32 insn = (u32)regs->badaddr; 185 186 if (!(has_vector() || has_xtheadvector())) 187 return false; 188 189 /* Do not handle if V is not supported, or disabled */ 190 if (!riscv_v_vstate_ctrl_user_allowed()) 191 return false; 192 193 /* If V has been enabled then it is not the first-use trap */ 194 if (riscv_v_vstate_query(regs)) 195 return false; 196 197 /* Get the instruction */ 198 if (!insn) { 199 if (__get_user(insn, epc)) 200 return false; 201 } 202 203 /* Filter out non-V instructions */ 204 if (!insn_is_vector(insn)) 205 return false; 206 207 /* Sanity check. datap should be null by the time of the first-use trap */ 208 WARN_ON(current->thread.vstate.datap); 209 210 /* 211 * Now we sure that this is a V instruction. And it executes in the 212 * context where VS has been off. So, try to allocate the user's V 213 * context and resume execution. 214 */ 215 if (riscv_v_thread_zalloc(riscv_v_user_cachep, ¤t->thread.vstate)) { 216 force_sig(SIGBUS); 217 return true; 218 } 219 riscv_v_vstate_on(regs); 220 riscv_v_vstate_set_restore(current, regs); 221 return true; 222 } 223 224 void riscv_v_vstate_ctrl_init(struct task_struct *tsk) 225 { 226 bool inherit; 227 int cur, next; 228 229 if (!(has_vector() || has_xtheadvector())) 230 return; 231 232 next = riscv_v_ctrl_get_next(tsk); 233 if (!next) { 234 if (READ_ONCE(riscv_v_implicit_uacc)) 235 cur = PR_RISCV_V_VSTATE_CTRL_ON; 236 else 237 cur = PR_RISCV_V_VSTATE_CTRL_OFF; 238 } else { 239 cur = next; 240 } 241 /* Clear next mask if inherit-bit is not set */ 242 inherit = riscv_v_ctrl_test_inherit(tsk); 243 if (!inherit) 244 next = PR_RISCV_V_VSTATE_CTRL_DEFAULT; 245 246 riscv_v_ctrl_set(tsk, cur, next, inherit); 247 } 248 249 long riscv_v_vstate_ctrl_get_current(void) 250 { 251 if (!(has_vector() || has_xtheadvector())) 252 return -EINVAL; 253 254 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; 255 } 256 257 long riscv_v_vstate_ctrl_set_current(unsigned long arg) 258 { 259 bool inherit; 260 int cur, next; 261 262 if (!(has_vector() || has_xtheadvector())) 263 return -EINVAL; 264 265 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) 266 return -EINVAL; 267 268 cur = VSTATE_CTRL_GET_CUR(arg); 269 switch (cur) { 270 case PR_RISCV_V_VSTATE_CTRL_OFF: 271 /* Do not allow user to turn off V if current is not off */ 272 if (riscv_v_ctrl_get_cur(current) != PR_RISCV_V_VSTATE_CTRL_OFF) 273 return -EPERM; 274 275 break; 276 case PR_RISCV_V_VSTATE_CTRL_ON: 277 break; 278 case PR_RISCV_V_VSTATE_CTRL_DEFAULT: 279 cur = riscv_v_ctrl_get_cur(current); 280 break; 281 default: 282 return -EINVAL; 283 } 284 285 next = VSTATE_CTRL_GET_NEXT(arg); 286 inherit = VSTATE_CTRL_GET_INHERIT(arg); 287 switch (next) { 288 case PR_RISCV_V_VSTATE_CTRL_DEFAULT: 289 case PR_RISCV_V_VSTATE_CTRL_OFF: 290 case PR_RISCV_V_VSTATE_CTRL_ON: 291 riscv_v_ctrl_set(current, cur, next, inherit); 292 return 0; 293 } 294 295 return -EINVAL; 296 } 297 298 #ifdef CONFIG_SYSCTL 299 300 static const struct ctl_table riscv_v_default_vstate_table[] = { 301 { 302 .procname = "riscv_v_default_allow", 303 .data = &riscv_v_implicit_uacc, 304 .maxlen = sizeof(riscv_v_implicit_uacc), 305 .mode = 0644, 306 .proc_handler = proc_dobool, 307 }, 308 }; 309 310 static int __init riscv_v_sysctl_init(void) 311 { 312 if (has_vector() || has_xtheadvector()) 313 if (!register_sysctl("abi", riscv_v_default_vstate_table)) 314 return -EINVAL; 315 return 0; 316 } 317 318 #else /* ! CONFIG_SYSCTL */ 319 static int __init riscv_v_sysctl_init(void) { return 0; } 320 #endif /* ! CONFIG_SYSCTL */ 321 322 static int __init riscv_v_init(void) 323 { 324 return riscv_v_sysctl_init(); 325 } 326 core_initcall(riscv_v_init); 327