1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 * Copyright (C) 2014 Darius Rad <darius@bluespec.com> 5 * Copyright (C) 2017 SiFive 6 */ 7 8 #include <linux/syscalls.h> 9 #include <asm/cacheflush.h> 10 #include <asm-generic/mman-common.h> 11 12 static long riscv_sys_mmap(unsigned long addr, unsigned long len, 13 unsigned long prot, unsigned long flags, 14 unsigned long fd, unsigned long offset, 15 unsigned long page_shift_offset) 16 { 17 if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) 18 return -EINVAL; 19 20 /* 21 * If PROT_WRITE is specified then extend that to PROT_READ 22 * protection_map[VM_WRITE] is now going to select shadow stack encodings. 23 * So specifying PROT_WRITE actually should select protection_map [VM_WRITE | VM_READ] 24 * If user wants to create shadow stack then they should use `map_shadow_stack` syscall. 25 */ 26 if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) 27 prot |= PROT_READ; 28 29 return ksys_mmap_pgoff(addr, len, prot, flags, fd, 30 offset >> (PAGE_SHIFT - page_shift_offset)); 31 } 32 33 #ifdef CONFIG_64BIT 34 SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, 35 unsigned long, prot, unsigned long, flags, 36 unsigned long, fd, unsigned long, offset) 37 { 38 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0); 39 } 40 #endif 41 42 #if defined(CONFIG_32BIT) || defined(CONFIG_COMPAT) 43 SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 44 unsigned long, prot, unsigned long, flags, 45 unsigned long, fd, unsigned long, offset) 46 { 47 /* 48 * Note that the shift for mmap2 is constant (12), 49 * regardless of PAGE_SIZE 50 */ 51 return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12); 52 } 53 #endif 54 55 /* 56 * Allows the instruction cache to be flushed from userspace. Despite RISC-V 57 * having a direct 'fence.i' instruction available to userspace (which we 58 * can't trap!), that's not actually viable when running on Linux because the 59 * kernel might schedule a process on another hart. There is no way for 60 * userspace to handle this without invoking the kernel (as it doesn't know the 61 * thread->hart mappings), so we've defined a RISC-V specific system call to 62 * flush the instruction cache. 63 * 64 * sys_riscv_flush_icache() is defined to flush the instruction cache over an 65 * address range, with the flush applying to either all threads or just the 66 * caller. We don't currently do anything with the address range, that's just 67 * in there for forwards compatibility. 68 */ 69 SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, 70 uintptr_t, flags) 71 { 72 /* Check the reserved flags. */ 73 if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) 74 return -EINVAL; 75 76 flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); 77 78 return 0; 79 } 80 81 /* Not defined using SYSCALL_DEFINE0 to avoid error injection */ 82 asmlinkage long __riscv_sys_ni_syscall(const struct pt_regs *__unused) 83 { 84 return -ENOSYS; 85 } 86