1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SMP initialisation and IPI support 4 * Based on arch/arm64/kernel/smp.c 5 * 6 * Copyright (C) 2012 ARM Ltd. 7 * Copyright (C) 2015 Regents of the University of California 8 * Copyright (C) 2017 SiFive 9 */ 10 11 #include <linux/cpu.h> 12 #include <linux/clockchips.h> 13 #include <linux/interrupt.h> 14 #include <linux/module.h> 15 #include <linux/profile.h> 16 #include <linux/smp.h> 17 #include <linux/sched.h> 18 #include <linux/seq_file.h> 19 #include <linux/delay.h> 20 #include <linux/irq_work.h> 21 22 #include <asm/sbi.h> 23 #include <asm/tlbflush.h> 24 #include <asm/cacheflush.h> 25 26 enum ipi_message_type { 27 IPI_RESCHEDULE, 28 IPI_CALL_FUNC, 29 IPI_CPU_STOP, 30 IPI_IRQ_WORK, 31 IPI_TIMER, 32 IPI_MAX 33 }; 34 35 unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = { 36 [0 ... NR_CPUS-1] = INVALID_HARTID 37 }; 38 39 void __init smp_setup_processor_id(void) 40 { 41 cpuid_to_hartid_map(0) = boot_cpu_hartid; 42 } 43 44 /* A collection of single bit ipi messages. */ 45 static struct { 46 unsigned long stats[IPI_MAX] ____cacheline_aligned; 47 unsigned long bits ____cacheline_aligned; 48 } ipi_data[NR_CPUS] __cacheline_aligned; 49 50 int riscv_hartid_to_cpuid(unsigned long hartid) 51 { 52 int i; 53 54 for (i = 0; i < NR_CPUS; i++) 55 if (cpuid_to_hartid_map(i) == hartid) 56 return i; 57 58 pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); 59 return -ENOENT; 60 } 61 62 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 63 { 64 return phys_id == cpuid_to_hartid_map(cpu); 65 } 66 67 static void ipi_stop(void) 68 { 69 set_cpu_online(smp_processor_id(), false); 70 while (1) 71 wait_for_interrupt(); 72 } 73 74 static const struct riscv_ipi_ops *ipi_ops __ro_after_init; 75 76 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops) 77 { 78 ipi_ops = ops; 79 } 80 EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); 81 82 void riscv_clear_ipi(void) 83 { 84 if (ipi_ops && ipi_ops->ipi_clear) 85 ipi_ops->ipi_clear(); 86 87 csr_clear(CSR_IP, IE_SIE); 88 } 89 EXPORT_SYMBOL_GPL(riscv_clear_ipi); 90 91 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) 92 { 93 int cpu; 94 95 smp_mb__before_atomic(); 96 for_each_cpu(cpu, mask) 97 set_bit(op, &ipi_data[cpu].bits); 98 smp_mb__after_atomic(); 99 100 if (ipi_ops && ipi_ops->ipi_inject) 101 ipi_ops->ipi_inject(mask); 102 else 103 pr_warn("SMP: IPI inject method not available\n"); 104 } 105 106 static void send_ipi_single(int cpu, enum ipi_message_type op) 107 { 108 smp_mb__before_atomic(); 109 set_bit(op, &ipi_data[cpu].bits); 110 smp_mb__after_atomic(); 111 112 if (ipi_ops && ipi_ops->ipi_inject) 113 ipi_ops->ipi_inject(cpumask_of(cpu)); 114 else 115 pr_warn("SMP: IPI inject method not available\n"); 116 } 117 118 #ifdef CONFIG_IRQ_WORK 119 void arch_irq_work_raise(void) 120 { 121 send_ipi_single(smp_processor_id(), IPI_IRQ_WORK); 122 } 123 #endif 124 125 void handle_IPI(struct pt_regs *regs) 126 { 127 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; 128 unsigned long *stats = ipi_data[smp_processor_id()].stats; 129 130 riscv_clear_ipi(); 131 132 while (true) { 133 unsigned long ops; 134 135 /* Order bit clearing and data access. */ 136 mb(); 137 138 ops = xchg(pending_ipis, 0); 139 if (ops == 0) 140 return; 141 142 if (ops & (1 << IPI_RESCHEDULE)) { 143 stats[IPI_RESCHEDULE]++; 144 scheduler_ipi(); 145 } 146 147 if (ops & (1 << IPI_CALL_FUNC)) { 148 stats[IPI_CALL_FUNC]++; 149 generic_smp_call_function_interrupt(); 150 } 151 152 if (ops & (1 << IPI_CPU_STOP)) { 153 stats[IPI_CPU_STOP]++; 154 ipi_stop(); 155 } 156 157 if (ops & (1 << IPI_IRQ_WORK)) { 158 stats[IPI_IRQ_WORK]++; 159 irq_work_run(); 160 } 161 162 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 163 if (ops & (1 << IPI_TIMER)) { 164 stats[IPI_TIMER]++; 165 tick_receive_broadcast(); 166 } 167 #endif 168 BUG_ON((ops >> IPI_MAX) != 0); 169 170 /* Order data access and bit testing. */ 171 mb(); 172 } 173 } 174 175 static const char * const ipi_names[] = { 176 [IPI_RESCHEDULE] = "Rescheduling interrupts", 177 [IPI_CALL_FUNC] = "Function call interrupts", 178 [IPI_CPU_STOP] = "CPU stop interrupts", 179 [IPI_IRQ_WORK] = "IRQ work interrupts", 180 [IPI_TIMER] = "Timer broadcast interrupts", 181 }; 182 183 void show_ipi_stats(struct seq_file *p, int prec) 184 { 185 unsigned int cpu, i; 186 187 for (i = 0; i < IPI_MAX; i++) { 188 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, 189 prec >= 4 ? " " : ""); 190 for_each_online_cpu(cpu) 191 seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); 192 seq_printf(p, " %s\n", ipi_names[i]); 193 } 194 } 195 196 void arch_send_call_function_ipi_mask(struct cpumask *mask) 197 { 198 send_ipi_mask(mask, IPI_CALL_FUNC); 199 } 200 201 void arch_send_call_function_single_ipi(int cpu) 202 { 203 send_ipi_single(cpu, IPI_CALL_FUNC); 204 } 205 206 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 207 void tick_broadcast(const struct cpumask *mask) 208 { 209 send_ipi_mask(mask, IPI_TIMER); 210 } 211 #endif 212 213 void smp_send_stop(void) 214 { 215 unsigned long timeout; 216 217 if (num_online_cpus() > 1) { 218 cpumask_t mask; 219 220 cpumask_copy(&mask, cpu_online_mask); 221 cpumask_clear_cpu(smp_processor_id(), &mask); 222 223 if (system_state <= SYSTEM_RUNNING) 224 pr_crit("SMP: stopping secondary CPUs\n"); 225 send_ipi_mask(&mask, IPI_CPU_STOP); 226 } 227 228 /* Wait up to one second for other CPUs to stop */ 229 timeout = USEC_PER_SEC; 230 while (num_online_cpus() > 1 && timeout--) 231 udelay(1); 232 233 if (num_online_cpus() > 1) 234 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", 235 cpumask_pr_args(cpu_online_mask)); 236 } 237 238 void smp_send_reschedule(int cpu) 239 { 240 send_ipi_single(cpu, IPI_RESCHEDULE); 241 } 242 EXPORT_SYMBOL_GPL(smp_send_reschedule); 243