1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SMP initialisation and IPI support 4 * Based on arch/arm64/kernel/smp.c 5 * 6 * Copyright (C) 2012 ARM Ltd. 7 * Copyright (C) 2015 Regents of the University of California 8 * Copyright (C) 2017 SiFive 9 */ 10 11 #include <linux/cpu.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/profile.h> 15 #include <linux/smp.h> 16 #include <linux/sched.h> 17 #include <linux/seq_file.h> 18 #include <linux/delay.h> 19 #include <linux/irq_work.h> 20 21 #include <asm/clint.h> 22 #include <asm/sbi.h> 23 #include <asm/tlbflush.h> 24 #include <asm/cacheflush.h> 25 26 enum ipi_message_type { 27 IPI_RESCHEDULE, 28 IPI_CALL_FUNC, 29 IPI_CPU_STOP, 30 IPI_IRQ_WORK, 31 IPI_MAX 32 }; 33 34 unsigned long __cpuid_to_hartid_map[NR_CPUS] = { 35 [0 ... NR_CPUS-1] = INVALID_HARTID 36 }; 37 38 void __init smp_setup_processor_id(void) 39 { 40 cpuid_to_hartid_map(0) = boot_cpu_hartid; 41 } 42 43 /* A collection of single bit ipi messages. */ 44 static struct { 45 unsigned long stats[IPI_MAX] ____cacheline_aligned; 46 unsigned long bits ____cacheline_aligned; 47 } ipi_data[NR_CPUS] __cacheline_aligned; 48 49 int riscv_hartid_to_cpuid(int hartid) 50 { 51 int i; 52 53 for (i = 0; i < NR_CPUS; i++) 54 if (cpuid_to_hartid_map(i) == hartid) 55 return i; 56 57 pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); 58 return i; 59 } 60 61 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out) 62 { 63 int cpu; 64 65 cpumask_clear(out); 66 for_each_cpu(cpu, in) 67 cpumask_set_cpu(cpuid_to_hartid_map(cpu), out); 68 } 69 EXPORT_SYMBOL_GPL(riscv_cpuid_to_hartid_mask); 70 71 bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 72 { 73 return phys_id == cpuid_to_hartid_map(cpu); 74 } 75 76 /* Unsupported */ 77 int setup_profiling_timer(unsigned int multiplier) 78 { 79 return -EINVAL; 80 } 81 82 static void ipi_stop(void) 83 { 84 set_cpu_online(smp_processor_id(), false); 85 while (1) 86 wait_for_interrupt(); 87 } 88 89 static struct riscv_ipi_ops *ipi_ops; 90 91 void riscv_set_ipi_ops(struct riscv_ipi_ops *ops) 92 { 93 ipi_ops = ops; 94 } 95 EXPORT_SYMBOL_GPL(riscv_set_ipi_ops); 96 97 void riscv_clear_ipi(void) 98 { 99 if (ipi_ops && ipi_ops->ipi_clear) 100 ipi_ops->ipi_clear(); 101 102 csr_clear(CSR_IP, IE_SIE); 103 } 104 EXPORT_SYMBOL_GPL(riscv_clear_ipi); 105 106 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) 107 { 108 int cpu; 109 110 smp_mb__before_atomic(); 111 for_each_cpu(cpu, mask) 112 set_bit(op, &ipi_data[cpu].bits); 113 smp_mb__after_atomic(); 114 115 if (ipi_ops && ipi_ops->ipi_inject) 116 ipi_ops->ipi_inject(mask); 117 else 118 pr_warn("SMP: IPI inject method not available\n"); 119 } 120 121 static void send_ipi_single(int cpu, enum ipi_message_type op) 122 { 123 smp_mb__before_atomic(); 124 set_bit(op, &ipi_data[cpu].bits); 125 smp_mb__after_atomic(); 126 127 if (ipi_ops && ipi_ops->ipi_inject) 128 ipi_ops->ipi_inject(cpumask_of(cpu)); 129 else 130 pr_warn("SMP: IPI inject method not available\n"); 131 } 132 133 #ifdef CONFIG_IRQ_WORK 134 void arch_irq_work_raise(void) 135 { 136 send_ipi_single(smp_processor_id(), IPI_IRQ_WORK); 137 } 138 #endif 139 140 void handle_IPI(struct pt_regs *regs) 141 { 142 struct pt_regs *old_regs = set_irq_regs(regs); 143 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits; 144 unsigned long *stats = ipi_data[smp_processor_id()].stats; 145 146 irq_enter(); 147 148 riscv_clear_ipi(); 149 150 while (true) { 151 unsigned long ops; 152 153 /* Order bit clearing and data access. */ 154 mb(); 155 156 ops = xchg(pending_ipis, 0); 157 if (ops == 0) 158 goto done; 159 160 if (ops & (1 << IPI_RESCHEDULE)) { 161 stats[IPI_RESCHEDULE]++; 162 scheduler_ipi(); 163 } 164 165 if (ops & (1 << IPI_CALL_FUNC)) { 166 stats[IPI_CALL_FUNC]++; 167 generic_smp_call_function_interrupt(); 168 } 169 170 if (ops & (1 << IPI_CPU_STOP)) { 171 stats[IPI_CPU_STOP]++; 172 ipi_stop(); 173 } 174 175 if (ops & (1 << IPI_IRQ_WORK)) { 176 stats[IPI_IRQ_WORK]++; 177 irq_work_run(); 178 } 179 180 BUG_ON((ops >> IPI_MAX) != 0); 181 182 /* Order data access and bit testing. */ 183 mb(); 184 } 185 186 done: 187 irq_exit(); 188 set_irq_regs(old_regs); 189 } 190 191 static const char * const ipi_names[] = { 192 [IPI_RESCHEDULE] = "Rescheduling interrupts", 193 [IPI_CALL_FUNC] = "Function call interrupts", 194 [IPI_CPU_STOP] = "CPU stop interrupts", 195 [IPI_IRQ_WORK] = "IRQ work interrupts", 196 }; 197 198 void show_ipi_stats(struct seq_file *p, int prec) 199 { 200 unsigned int cpu, i; 201 202 for (i = 0; i < IPI_MAX; i++) { 203 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, 204 prec >= 4 ? " " : ""); 205 for_each_online_cpu(cpu) 206 seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]); 207 seq_printf(p, " %s\n", ipi_names[i]); 208 } 209 } 210 211 void arch_send_call_function_ipi_mask(struct cpumask *mask) 212 { 213 send_ipi_mask(mask, IPI_CALL_FUNC); 214 } 215 216 void arch_send_call_function_single_ipi(int cpu) 217 { 218 send_ipi_single(cpu, IPI_CALL_FUNC); 219 } 220 221 void smp_send_stop(void) 222 { 223 unsigned long timeout; 224 225 if (num_online_cpus() > 1) { 226 cpumask_t mask; 227 228 cpumask_copy(&mask, cpu_online_mask); 229 cpumask_clear_cpu(smp_processor_id(), &mask); 230 231 if (system_state <= SYSTEM_RUNNING) 232 pr_crit("SMP: stopping secondary CPUs\n"); 233 send_ipi_mask(&mask, IPI_CPU_STOP); 234 } 235 236 /* Wait up to one second for other CPUs to stop */ 237 timeout = USEC_PER_SEC; 238 while (num_online_cpus() > 1 && timeout--) 239 udelay(1); 240 241 if (num_online_cpus() > 1) 242 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n", 243 cpumask_pr_args(cpu_online_mask)); 244 } 245 246 void smp_send_reschedule(int cpu) 247 { 248 send_ipi_single(cpu, IPI_RESCHEDULE); 249 } 250 EXPORT_SYMBOL_GPL(smp_send_reschedule); 251