1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copied from arch/arm64/kernel/cpufeature.c 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitmap.h> 11 #include <linux/cpu.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/ctype.h> 14 #include <linux/log2.h> 15 #include <linux/memory.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <asm/acpi.h> 19 #include <asm/alternative.h> 20 #include <asm/cacheflush.h> 21 #include <asm/cpufeature.h> 22 #include <asm/hwcap.h> 23 #include <asm/text-patching.h> 24 #include <asm/hwprobe.h> 25 #include <asm/processor.h> 26 #include <asm/sbi.h> 27 #include <asm/vector.h> 28 #include <asm/vendor_extensions.h> 29 30 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) 31 32 unsigned long elf_hwcap __read_mostly; 33 34 /* Host ISA bitmap */ 35 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; 36 37 /* Per-cpu ISA extensions. */ 38 struct riscv_isainfo hart_isa[NR_CPUS]; 39 40 /** 41 * riscv_isa_extension_base() - Get base extension word 42 * 43 * @isa_bitmap: ISA bitmap to use 44 * Return: base extension word as unsigned long value 45 * 46 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 47 */ 48 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) 49 { 50 if (!isa_bitmap) 51 return riscv_isa[0]; 52 return isa_bitmap[0]; 53 } 54 EXPORT_SYMBOL_GPL(riscv_isa_extension_base); 55 56 /** 57 * __riscv_isa_extension_available() - Check whether given extension 58 * is available or not 59 * 60 * @isa_bitmap: ISA bitmap to use 61 * @bit: bit position of the desired extension 62 * Return: true or false 63 * 64 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 65 */ 66 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit) 67 { 68 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa; 69 70 if (bit >= RISCV_ISA_EXT_MAX) 71 return false; 72 73 return test_bit(bit, bmap) ? true : false; 74 } 75 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); 76 77 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, 78 const unsigned long *isa_bitmap) 79 { 80 if (!riscv_cbom_block_size) { 81 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); 82 return -EINVAL; 83 } 84 if (!is_power_of_2(riscv_cbom_block_size)) { 85 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); 86 return -EINVAL; 87 } 88 return 0; 89 } 90 91 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, 92 const unsigned long *isa_bitmap) 93 { 94 if (!riscv_cboz_block_size) { 95 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); 96 return -EINVAL; 97 } 98 if (!is_power_of_2(riscv_cboz_block_size)) { 99 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); 100 return -EINVAL; 101 } 102 return 0; 103 } 104 105 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, 106 const unsigned long *isa_bitmap) 107 { 108 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA)) 109 return 0; 110 111 return -EPROBE_DEFER; 112 } 113 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, 114 const unsigned long *isa_bitmap) 115 { 116 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && 117 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) 118 return 0; 119 120 return -EPROBE_DEFER; 121 } 122 123 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, 124 const unsigned long *isa_bitmap) 125 { 126 if (IS_ENABLED(CONFIG_64BIT)) 127 return -EINVAL; 128 129 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && 130 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) 131 return 0; 132 133 return -EPROBE_DEFER; 134 } 135 136 static const unsigned int riscv_zk_bundled_exts[] = { 137 RISCV_ISA_EXT_ZBKB, 138 RISCV_ISA_EXT_ZBKC, 139 RISCV_ISA_EXT_ZBKX, 140 RISCV_ISA_EXT_ZKND, 141 RISCV_ISA_EXT_ZKNE, 142 RISCV_ISA_EXT_ZKR, 143 RISCV_ISA_EXT_ZKT, 144 }; 145 146 static const unsigned int riscv_zkn_bundled_exts[] = { 147 RISCV_ISA_EXT_ZBKB, 148 RISCV_ISA_EXT_ZBKC, 149 RISCV_ISA_EXT_ZBKX, 150 RISCV_ISA_EXT_ZKND, 151 RISCV_ISA_EXT_ZKNE, 152 RISCV_ISA_EXT_ZKNH, 153 }; 154 155 static const unsigned int riscv_zks_bundled_exts[] = { 156 RISCV_ISA_EXT_ZBKB, 157 RISCV_ISA_EXT_ZBKC, 158 RISCV_ISA_EXT_ZKSED, 159 RISCV_ISA_EXT_ZKSH 160 }; 161 162 #define RISCV_ISA_EXT_ZVKN \ 163 RISCV_ISA_EXT_ZVKNED, \ 164 RISCV_ISA_EXT_ZVKNHB, \ 165 RISCV_ISA_EXT_ZVKB, \ 166 RISCV_ISA_EXT_ZVKT 167 168 static const unsigned int riscv_zvkn_bundled_exts[] = { 169 RISCV_ISA_EXT_ZVKN 170 }; 171 172 static const unsigned int riscv_zvknc_bundled_exts[] = { 173 RISCV_ISA_EXT_ZVKN, 174 RISCV_ISA_EXT_ZVBC 175 }; 176 177 static const unsigned int riscv_zvkng_bundled_exts[] = { 178 RISCV_ISA_EXT_ZVKN, 179 RISCV_ISA_EXT_ZVKG 180 }; 181 182 #define RISCV_ISA_EXT_ZVKS \ 183 RISCV_ISA_EXT_ZVKSED, \ 184 RISCV_ISA_EXT_ZVKSH, \ 185 RISCV_ISA_EXT_ZVKB, \ 186 RISCV_ISA_EXT_ZVKT 187 188 static const unsigned int riscv_zvks_bundled_exts[] = { 189 RISCV_ISA_EXT_ZVKS 190 }; 191 192 static const unsigned int riscv_zvksc_bundled_exts[] = { 193 RISCV_ISA_EXT_ZVKS, 194 RISCV_ISA_EXT_ZVBC 195 }; 196 197 static const unsigned int riscv_zvksg_bundled_exts[] = { 198 RISCV_ISA_EXT_ZVKS, 199 RISCV_ISA_EXT_ZVKG 200 }; 201 202 static const unsigned int riscv_zvbb_exts[] = { 203 RISCV_ISA_EXT_ZVKB 204 }; 205 206 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ 207 RISCV_ISA_EXT_ZVE64X, \ 208 RISCV_ISA_EXT_ZVE32F, \ 209 RISCV_ISA_EXT_ZVE32X 210 211 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ 212 RISCV_ISA_EXT_ZVE64F, \ 213 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST 214 215 #define RISCV_ISA_EXT_V_IMPLY_LIST \ 216 RISCV_ISA_EXT_ZVE64D, \ 217 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST 218 219 static const unsigned int riscv_zve32f_exts[] = { 220 RISCV_ISA_EXT_ZVE32X 221 }; 222 223 static const unsigned int riscv_zve64f_exts[] = { 224 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST 225 }; 226 227 static const unsigned int riscv_zve64d_exts[] = { 228 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST 229 }; 230 231 static const unsigned int riscv_v_exts[] = { 232 RISCV_ISA_EXT_V_IMPLY_LIST 233 }; 234 235 static const unsigned int riscv_zve64x_exts[] = { 236 RISCV_ISA_EXT_ZVE32X, 237 RISCV_ISA_EXT_ZVE64X 238 }; 239 240 /* 241 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V 242 * privileged ISA, the existence of the CSRs is implied by any extension which 243 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the 244 * existence of the CSR, and treat it as a subset of those other extensions. 245 */ 246 static const unsigned int riscv_xlinuxenvcfg_exts[] = { 247 RISCV_ISA_EXT_XLINUXENVCFG 248 }; 249 250 /* 251 * Zc* spec states that: 252 * - C always implies Zca 253 * - C+F implies Zcf (RV32 only) 254 * - C+D implies Zcd 255 * 256 * These extensions will be enabled and then validated depending on the 257 * availability of F/D RV32. 258 */ 259 static const unsigned int riscv_c_exts[] = { 260 RISCV_ISA_EXT_ZCA, 261 RISCV_ISA_EXT_ZCF, 262 RISCV_ISA_EXT_ZCD, 263 }; 264 265 /* 266 * The canonical order of ISA extension names in the ISA string is defined in 267 * chapter 27 of the unprivileged specification. 268 * 269 * Ordinarily, for in-kernel data structures, this order is unimportant but 270 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. 271 * 272 * The specification uses vague wording, such as should, when it comes to 273 * ordering, so for our purposes the following rules apply: 274 * 275 * 1. All multi-letter extensions must be separated from other extensions by an 276 * underscore. 277 * 278 * 2. Additional standard extensions (starting with 'Z') must be sorted after 279 * single-letter extensions and before any higher-privileged extensions. 280 * 281 * 3. The first letter following the 'Z' conventionally indicates the most 282 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 283 * If multiple 'Z' extensions are named, they must be ordered first by 284 * category, then alphabetically within a category. 285 * 286 * 3. Standard supervisor-level extensions (starting with 'S') must be listed 287 * after standard unprivileged extensions. If multiple supervisor-level 288 * extensions are listed, they must be ordered alphabetically. 289 * 290 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed 291 * after any lower-privileged, standard extensions. If multiple 292 * machine-level extensions are listed, they must be ordered 293 * alphabetically. 294 * 295 * 5. Non-standard extensions (starting with 'X') must be listed after all 296 * standard extensions. If multiple non-standard extensions are listed, they 297 * must be ordered alphabetically. 298 * 299 * An example string following the order is: 300 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 301 * 302 * New entries to this struct should follow the ordering rules described above. 303 */ 304 const struct riscv_isa_ext_data riscv_isa_ext[] = { 305 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), 306 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), 307 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), 308 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), 309 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), 310 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), 311 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), 312 __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), 313 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), 314 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, 315 riscv_ext_zicbom_validate), 316 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, 317 riscv_ext_zicboz_validate), 318 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 319 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), 320 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), 321 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), 322 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), 323 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 324 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), 325 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), 326 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), 327 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), 328 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), 329 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), 330 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), 331 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), 332 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), 333 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), 334 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate), 335 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends), 336 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), 337 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), 338 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), 339 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), 340 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), 341 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), 342 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), 343 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), 344 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), 345 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), 346 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), 347 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), 348 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), 349 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), 350 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), 351 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), 352 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), 353 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), 354 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), 355 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), 356 __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), 357 __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), 358 __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), 359 __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), 360 __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), 361 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), 362 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), 363 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), 364 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), 365 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), 366 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), 367 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), 368 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), 369 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), 370 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), 371 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), 372 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), 373 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), 374 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), 375 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), 376 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), 377 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), 378 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), 379 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), 380 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 381 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 382 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 383 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 384 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 385 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), 386 }; 387 388 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); 389 390 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap) 391 { 392 if (ext->id != RISCV_ISA_EXT_INVALID) 393 set_bit(ext->id, bitmap); 394 395 for (int i = 0; i < ext->subset_ext_size; i++) { 396 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID) 397 set_bit(ext->subset_ext_ids[i], bitmap); 398 } 399 } 400 401 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id) 402 { 403 for (int i = 0; i < riscv_isa_ext_count; i++) { 404 if (riscv_isa_ext[i].id == ext_id) 405 return &riscv_isa_ext[i]; 406 } 407 408 return NULL; 409 } 410 411 /* 412 * "Resolve" a source ISA bitmap into one that matches kernel configuration as 413 * well as correct extension dependencies. Some extensions depends on specific 414 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance) 415 * and this function will actually validate all the extensions provided in 416 * source_isa into the resolved_isa based on extensions validate() callbacks. 417 */ 418 static void __init riscv_resolve_isa(unsigned long *source_isa, 419 unsigned long *resolved_isa, unsigned long *this_hwcap, 420 unsigned long *isa2hwcap) 421 { 422 bool loop; 423 const struct riscv_isa_ext_data *ext; 424 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX); 425 int max_loop_count = riscv_isa_ext_count, ret; 426 unsigned int bit; 427 428 do { 429 loop = false; 430 if (max_loop_count-- < 0) { 431 pr_err("Failed to reach a stable ISA state\n"); 432 return; 433 } 434 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX); 435 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) { 436 ext = riscv_get_isa_ext_data(bit); 437 438 if (ext && ext->validate) { 439 ret = ext->validate(ext, resolved_isa); 440 if (ret == -EPROBE_DEFER) { 441 loop = true; 442 continue; 443 } else if (ret) { 444 /* Disable the extension entirely */ 445 clear_bit(bit, source_isa); 446 continue; 447 } 448 } 449 450 set_bit(bit, resolved_isa); 451 /* No need to keep it in source isa now that it is enabled */ 452 clear_bit(bit, source_isa); 453 454 /* Single letter extensions get set in hwcap */ 455 if (bit < RISCV_ISA_EXT_BASE) 456 *this_hwcap |= isa2hwcap[bit]; 457 } 458 } while (loop && memcmp(prev_resolved_isa, resolved_isa, sizeof(prev_resolved_isa))); 459 } 460 461 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap) 462 { 463 for (int i = 0; i < riscv_isa_ext_count; i++) { 464 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i]; 465 466 if ((name_end - name == strlen(ext->name)) && 467 !strncasecmp(name, ext->name, name_end - name)) { 468 riscv_isa_set_ext(ext, bitmap); 469 break; 470 } 471 } 472 } 473 474 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap) 475 { 476 /* 477 * For all possible cpus, we have already validated in 478 * the boot process that they at least contain "rv" and 479 * whichever of "32"/"64" this kernel supports, and so this 480 * section can be skipped. 481 */ 482 isa += 4; 483 484 while (*isa) { 485 const char *ext = isa++; 486 const char *ext_end = isa; 487 bool ext_err = false; 488 489 switch (*ext) { 490 case 'x': 491 case 'X': 492 if (acpi_disabled) 493 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); 494 /* 495 * To skip an extension, we find its end. 496 * As multi-letter extensions must be split from other multi-letter 497 * extensions with an "_", the end of a multi-letter extension will 498 * either be the null character or the "_" at the start of the next 499 * multi-letter extension. 500 */ 501 for (; *isa && *isa != '_'; ++isa) 502 ; 503 ext_err = true; 504 break; 505 case 's': 506 /* 507 * Workaround for invalid single-letter 's' & 'u' (QEMU). 508 * No need to set the bit in riscv_isa as 's' & 'u' are 509 * not valid ISA extensions. It works unless the first 510 * multi-letter extension in the ISA string begins with 511 * "Su" and is not prefixed with an underscore. 512 */ 513 if (ext[-1] != '_' && ext[1] == 'u') { 514 ++isa; 515 ext_err = true; 516 break; 517 } 518 fallthrough; 519 case 'S': 520 case 'z': 521 case 'Z': 522 /* 523 * Before attempting to parse the extension itself, we find its end. 524 * As multi-letter extensions must be split from other multi-letter 525 * extensions with an "_", the end of a multi-letter extension will 526 * either be the null character or the "_" at the start of the next 527 * multi-letter extension. 528 * 529 * Next, as the extensions version is currently ignored, we 530 * eliminate that portion. This is done by parsing backwards from 531 * the end of the extension, removing any numbers. This may be a 532 * major or minor number however, so the process is repeated if a 533 * minor number was found. 534 * 535 * ext_end is intended to represent the first character *after* the 536 * name portion of an extension, but will be decremented to the last 537 * character itself while eliminating the extensions version number. 538 * A simple re-increment solves this problem. 539 */ 540 for (; *isa && *isa != '_'; ++isa) 541 if (unlikely(!isalnum(*isa))) 542 ext_err = true; 543 544 ext_end = isa; 545 if (unlikely(ext_err)) 546 break; 547 548 if (!isdigit(ext_end[-1])) 549 break; 550 551 while (isdigit(*--ext_end)) 552 ; 553 554 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { 555 ++ext_end; 556 break; 557 } 558 559 while (isdigit(*--ext_end)) 560 ; 561 562 ++ext_end; 563 break; 564 default: 565 /* 566 * Things are a little easier for single-letter extensions, as they 567 * are parsed forwards. 568 * 569 * After checking that our starting position is valid, we need to 570 * ensure that, when isa was incremented at the start of the loop, 571 * that it arrived at the start of the next extension. 572 * 573 * If we are already on a non-digit, there is nothing to do. Either 574 * we have a multi-letter extension's _, or the start of an 575 * extension. 576 * 577 * Otherwise we have found the current extension's major version 578 * number. Parse past it, and a subsequent p/minor version number 579 * if present. The `p` extension must not appear immediately after 580 * a number, so there is no fear of missing it. 581 * 582 */ 583 if (unlikely(!isalpha(*ext))) { 584 ext_err = true; 585 break; 586 } 587 588 if (!isdigit(*isa)) 589 break; 590 591 while (isdigit(*++isa)) 592 ; 593 594 if (tolower(*isa) != 'p') 595 break; 596 597 if (!isdigit(*++isa)) { 598 --isa; 599 break; 600 } 601 602 while (isdigit(*++isa)) 603 ; 604 605 break; 606 } 607 608 /* 609 * The parser expects that at the start of an iteration isa points to the 610 * first character of the next extension. As we stop parsing an extension 611 * on meeting a non-alphanumeric character, an extra increment is needed 612 * where the succeeding extension is a multi-letter prefixed with an "_". 613 */ 614 if (*isa == '_') 615 ++isa; 616 617 if (unlikely(ext_err)) 618 continue; 619 620 match_isa_ext(ext, ext_end, bitmap); 621 } 622 } 623 624 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) 625 { 626 struct device_node *node; 627 const char *isa; 628 int rc; 629 struct acpi_table_header *rhct; 630 acpi_status status; 631 unsigned int cpu; 632 u64 boot_vendorid; 633 u64 boot_archid; 634 635 if (!acpi_disabled) { 636 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); 637 if (ACPI_FAILURE(status)) 638 return; 639 } 640 641 boot_vendorid = riscv_get_mvendorid(); 642 boot_archid = riscv_get_marchid(); 643 644 for_each_possible_cpu(cpu) { 645 struct riscv_isainfo *isainfo = &hart_isa[cpu]; 646 unsigned long this_hwcap = 0; 647 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 }; 648 649 if (acpi_disabled) { 650 node = of_cpu_device_node_get(cpu); 651 if (!node) { 652 pr_warn("Unable to find cpu node\n"); 653 continue; 654 } 655 656 rc = of_property_read_string(node, "riscv,isa", &isa); 657 of_node_put(node); 658 if (rc) { 659 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); 660 continue; 661 } 662 } else { 663 rc = acpi_get_riscv_isa(rhct, cpu, &isa); 664 if (rc < 0) { 665 pr_warn("Unable to get ISA for the hart - %d\n", cpu); 666 continue; 667 } 668 } 669 670 riscv_parse_isa_string(isa, source_isa); 671 672 /* 673 * These ones were as they were part of the base ISA when the 674 * port & dt-bindings were upstreamed, and so can be set 675 * unconditionally where `i` is in riscv,isa on DT systems. 676 */ 677 if (acpi_disabled) { 678 set_bit(RISCV_ISA_EXT_ZICSR, source_isa); 679 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa); 680 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa); 681 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa); 682 } 683 684 /* 685 * "V" in ISA strings is ambiguous in practice: it should mean 686 * just the standard V-1.0 but vendors aren't well behaved. 687 * Many vendors with T-Head CPU cores which implement the 0.7.1 688 * version of the vector specification put "v" into their DTs. 689 * CPU cores with the ratified spec will contain non-zero 690 * marchid. 691 */ 692 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) { 693 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; 694 clear_bit(RISCV_ISA_EXT_v, source_isa); 695 } 696 697 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); 698 699 /* 700 * All "okay" hart should have same isa. Set HWCAP based on 701 * common capabilities of every "okay" hart, in case they don't 702 * have. 703 */ 704 if (elf_hwcap) 705 elf_hwcap &= this_hwcap; 706 else 707 elf_hwcap = this_hwcap; 708 709 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 710 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 711 else 712 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 713 } 714 715 if (!acpi_disabled && rhct) 716 acpi_put_table((struct acpi_table_header *)rhct); 717 } 718 719 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu) 720 { 721 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) 722 return; 723 724 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { 725 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; 726 727 for (int j = 0; j < ext_list->ext_data_count; j++) { 728 const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; 729 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu]; 730 731 if (of_property_match_string(cpu_node, "riscv,isa-extensions", 732 ext.property) < 0) 733 continue; 734 735 /* 736 * Assume that subset extensions are all members of the 737 * same vendor. 738 */ 739 if (ext.subset_ext_size) 740 for (int k = 0; k < ext.subset_ext_size; k++) 741 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); 742 743 set_bit(ext.id, isavendorinfo->isa); 744 } 745 } 746 } 747 748 /* 749 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that 750 * are shared across CPUs for that vendor. 751 */ 752 static void __init riscv_fill_vendor_ext_list(int cpu) 753 { 754 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) 755 return; 756 757 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { 758 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; 759 760 if (!ext_list->is_initialized) { 761 bitmap_copy(ext_list->all_harts_isa_bitmap.isa, 762 ext_list->per_hart_isa_bitmap[cpu].isa, 763 RISCV_ISA_VENDOR_EXT_MAX); 764 ext_list->is_initialized = true; 765 } else { 766 bitmap_and(ext_list->all_harts_isa_bitmap.isa, 767 ext_list->all_harts_isa_bitmap.isa, 768 ext_list->per_hart_isa_bitmap[cpu].isa, 769 RISCV_ISA_VENDOR_EXT_MAX); 770 } 771 } 772 } 773 774 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) 775 { 776 unsigned int cpu; 777 778 for_each_possible_cpu(cpu) { 779 unsigned long this_hwcap = 0; 780 struct device_node *cpu_node; 781 struct riscv_isainfo *isainfo = &hart_isa[cpu]; 782 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 }; 783 784 cpu_node = of_cpu_device_node_get(cpu); 785 if (!cpu_node) { 786 pr_warn("Unable to find cpu node\n"); 787 continue; 788 } 789 790 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { 791 of_node_put(cpu_node); 792 continue; 793 } 794 795 for (int i = 0; i < riscv_isa_ext_count; i++) { 796 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i]; 797 798 if (of_property_match_string(cpu_node, "riscv,isa-extensions", 799 ext->property) < 0) 800 continue; 801 802 riscv_isa_set_ext(ext, source_isa); 803 } 804 805 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); 806 riscv_fill_cpu_vendor_ext(cpu_node, cpu); 807 808 of_node_put(cpu_node); 809 810 /* 811 * All "okay" harts should have same isa. Set HWCAP based on 812 * common capabilities of every "okay" hart, in case they don't. 813 */ 814 if (elf_hwcap) 815 elf_hwcap &= this_hwcap; 816 else 817 elf_hwcap = this_hwcap; 818 819 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 820 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 821 else 822 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 823 824 riscv_fill_vendor_ext_list(cpu); 825 } 826 827 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 828 return -ENOENT; 829 830 return 0; 831 } 832 833 #ifdef CONFIG_RISCV_ISA_FALLBACK 834 bool __initdata riscv_isa_fallback = true; 835 #else 836 bool __initdata riscv_isa_fallback; 837 static int __init riscv_isa_fallback_setup(char *__unused) 838 { 839 riscv_isa_fallback = true; 840 return 1; 841 } 842 early_param("riscv_isa_fallback", riscv_isa_fallback_setup); 843 #endif 844 845 void __init riscv_fill_hwcap(void) 846 { 847 char print_str[NUM_ALPHA_EXTS + 1]; 848 unsigned long isa2hwcap[26] = {0}; 849 int i, j; 850 851 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; 852 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; 853 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; 854 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; 855 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; 856 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; 857 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; 858 859 if (!acpi_disabled) { 860 riscv_fill_hwcap_from_isa_string(isa2hwcap); 861 } else { 862 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); 863 864 if (ret && riscv_isa_fallback) { 865 pr_info("Falling back to deprecated \"riscv,isa\"\n"); 866 riscv_fill_hwcap_from_isa_string(isa2hwcap); 867 } 868 } 869 870 /* 871 * We don't support systems with F but without D, so mask those out 872 * here. 873 */ 874 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { 875 pr_info("This kernel does not support systems with F but not D\n"); 876 elf_hwcap &= ~COMPAT_HWCAP_ISA_F; 877 } 878 879 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { 880 /* 881 * This cannot fail when called on the boot hart 882 */ 883 riscv_v_setup_vsize(); 884 } 885 886 if (elf_hwcap & COMPAT_HWCAP_ISA_V) { 887 /* 888 * ISA string in device tree might have 'v' flag, but 889 * CONFIG_RISCV_ISA_V is disabled in kernel. 890 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. 891 */ 892 if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) 893 elf_hwcap &= ~COMPAT_HWCAP_ISA_V; 894 } 895 896 memset(print_str, 0, sizeof(print_str)); 897 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 898 if (riscv_isa[0] & BIT_MASK(i)) 899 print_str[j++] = (char)('a' + i); 900 pr_info("riscv: base ISA extensions %s\n", print_str); 901 902 memset(print_str, 0, sizeof(print_str)); 903 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 904 if (elf_hwcap & BIT_MASK(i)) 905 print_str[j++] = (char)('a' + i); 906 pr_info("riscv: ELF capabilities %s\n", print_str); 907 } 908 909 unsigned long riscv_get_elf_hwcap(void) 910 { 911 unsigned long hwcap; 912 913 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); 914 915 if (!riscv_v_vstate_ctrl_user_allowed()) 916 hwcap &= ~COMPAT_HWCAP_ISA_V; 917 918 return hwcap; 919 } 920 921 void riscv_user_isa_enable(void) 922 { 923 if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) 924 csr_set(CSR_ENVCFG, ENVCFG_CBZE); 925 } 926 927 #ifdef CONFIG_RISCV_ALTERNATIVE 928 /* 929 * Alternative patch sites consider 48 bits when determining when to patch 930 * the old instruction sequence with the new. These bits are broken into a 931 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the 932 * patch site is for an erratum, identified by the 32-bit patch ID. When 933 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures 934 * further break down patch ID into two 16-bit numbers. The lower 16 bits 935 * are the cpufeature ID and the upper 16 bits are used for a value specific 936 * to the cpufeature and patch site. If the upper 16 bits are zero, then it 937 * implies no specific value is specified. cpufeatures that want to control 938 * patching on a per-site basis will provide non-zero values and implement 939 * checks here. The checks return true when patching should be done, and 940 * false otherwise. 941 */ 942 static bool riscv_cpufeature_patch_check(u16 id, u16 value) 943 { 944 if (!value) 945 return true; 946 947 switch (id) { 948 case RISCV_ISA_EXT_ZICBOZ: 949 /* 950 * Zicboz alternative applications provide the maximum 951 * supported block size order, or zero when it doesn't 952 * matter. If the current block size exceeds the maximum, 953 * then the alternative cannot be applied. 954 */ 955 return riscv_cboz_block_size <= (1U << value); 956 } 957 958 return false; 959 } 960 961 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, 962 struct alt_entry *end, 963 unsigned int stage) 964 { 965 struct alt_entry *alt; 966 void *oldptr, *altptr; 967 u16 id, value, vendor; 968 969 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) 970 return; 971 972 for (alt = begin; alt < end; alt++) { 973 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); 974 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); 975 976 /* 977 * Any alternative with a patch_id that is less than 978 * RISCV_ISA_EXT_MAX is interpreted as a standard extension. 979 * 980 * Any alternative with patch_id that is greater than or equal 981 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a 982 * vendor extension. 983 */ 984 if (id < RISCV_ISA_EXT_MAX) { 985 /* 986 * This patch should be treated as errata so skip 987 * processing here. 988 */ 989 if (alt->vendor_id != 0) 990 continue; 991 992 if (!__riscv_isa_extension_available(NULL, id)) 993 continue; 994 995 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); 996 if (!riscv_cpufeature_patch_check(id, value)) 997 continue; 998 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { 999 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, 1000 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) 1001 continue; 1002 } else { 1003 WARN(1, "This extension id:%d is not in ISA extension list", id); 1004 continue; 1005 } 1006 1007 oldptr = ALT_OLD_PTR(alt); 1008 altptr = ALT_ALT_PTR(alt); 1009 1010 mutex_lock(&text_mutex); 1011 patch_text_nosync(oldptr, altptr, alt->alt_len); 1012 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); 1013 mutex_unlock(&text_mutex); 1014 } 1015 } 1016 #endif 1017