1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copied from arch/arm64/kernel/cpufeature.c 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitmap.h> 11 #include <linux/cpu.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/ctype.h> 14 #include <linux/log2.h> 15 #include <linux/memory.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <asm/acpi.h> 19 #include <asm/alternative.h> 20 #include <asm/bugs.h> 21 #include <asm/cacheflush.h> 22 #include <asm/cpufeature.h> 23 #include <asm/hwcap.h> 24 #include <asm/text-patching.h> 25 #include <asm/hwprobe.h> 26 #include <asm/processor.h> 27 #include <asm/sbi.h> 28 #include <asm/vector.h> 29 #include <asm/vendor_extensions.h> 30 #include <asm/vendor_extensions/thead.h> 31 32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1) 33 34 static bool any_cpu_has_zicboz; 35 36 unsigned long elf_hwcap __read_mostly; 37 38 /* Host ISA bitmap */ 39 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; 40 41 /* Per-cpu ISA extensions. */ 42 struct riscv_isainfo hart_isa[NR_CPUS]; 43 44 u32 thead_vlenb_of; 45 46 /** 47 * riscv_isa_extension_base() - Get base extension word 48 * 49 * @isa_bitmap: ISA bitmap to use 50 * Return: base extension word as unsigned long value 51 * 52 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 53 */ 54 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap) 55 { 56 if (!isa_bitmap) 57 return riscv_isa[0]; 58 return isa_bitmap[0]; 59 } 60 EXPORT_SYMBOL_GPL(riscv_isa_extension_base); 61 62 /** 63 * __riscv_isa_extension_available() - Check whether given extension 64 * is available or not 65 * 66 * @isa_bitmap: ISA bitmap to use 67 * @bit: bit position of the desired extension 68 * Return: true or false 69 * 70 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used. 71 */ 72 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit) 73 { 74 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa; 75 76 if (bit >= RISCV_ISA_EXT_MAX) 77 return false; 78 79 return test_bit(bit, bmap) ? true : false; 80 } 81 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available); 82 83 static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, 84 const unsigned long *isa_bitmap) 85 { 86 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) 87 return 0; 88 89 return -EPROBE_DEFER; 90 } 91 92 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, 93 const unsigned long *isa_bitmap) 94 { 95 if (!riscv_cbom_block_size) { 96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); 97 return -EINVAL; 98 } 99 if (!is_power_of_2(riscv_cbom_block_size)) { 100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); 101 return -EINVAL; 102 } 103 return 0; 104 } 105 106 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, 107 const unsigned long *isa_bitmap) 108 { 109 if (!riscv_cboz_block_size) { 110 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); 111 return -EINVAL; 112 } 113 if (!is_power_of_2(riscv_cboz_block_size)) { 114 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); 115 return -EINVAL; 116 } 117 any_cpu_has_zicboz = true; 118 return 0; 119 } 120 121 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, 122 const unsigned long *isa_bitmap) 123 { 124 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA)) 125 return 0; 126 127 return -EPROBE_DEFER; 128 } 129 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, 130 const unsigned long *isa_bitmap) 131 { 132 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && 133 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) 134 return 0; 135 136 return -EPROBE_DEFER; 137 } 138 139 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, 140 const unsigned long *isa_bitmap) 141 { 142 if (IS_ENABLED(CONFIG_64BIT)) 143 return -EINVAL; 144 145 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && 146 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) 147 return 0; 148 149 return -EPROBE_DEFER; 150 } 151 152 static int riscv_vector_f_validate(const struct riscv_isa_ext_data *data, 153 const unsigned long *isa_bitmap) 154 { 155 if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) 156 return -EINVAL; 157 158 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F)) 159 return 0; 160 161 return -EPROBE_DEFER; 162 } 163 164 static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data, 165 const unsigned long *isa_bitmap) 166 { 167 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) && 168 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN)) 169 return 0; 170 171 return -EPROBE_DEFER; 172 } 173 174 static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, 175 const unsigned long *isa_bitmap) 176 { 177 /* SVADE has already been detected, use SVADE only */ 178 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE)) 179 return -EOPNOTSUPP; 180 181 return 0; 182 } 183 184 static const unsigned int riscv_zk_bundled_exts[] = { 185 RISCV_ISA_EXT_ZBKB, 186 RISCV_ISA_EXT_ZBKC, 187 RISCV_ISA_EXT_ZBKX, 188 RISCV_ISA_EXT_ZKND, 189 RISCV_ISA_EXT_ZKNE, 190 RISCV_ISA_EXT_ZKR, 191 RISCV_ISA_EXT_ZKT, 192 }; 193 194 static const unsigned int riscv_zkn_bundled_exts[] = { 195 RISCV_ISA_EXT_ZBKB, 196 RISCV_ISA_EXT_ZBKC, 197 RISCV_ISA_EXT_ZBKX, 198 RISCV_ISA_EXT_ZKND, 199 RISCV_ISA_EXT_ZKNE, 200 RISCV_ISA_EXT_ZKNH, 201 }; 202 203 static const unsigned int riscv_zks_bundled_exts[] = { 204 RISCV_ISA_EXT_ZBKB, 205 RISCV_ISA_EXT_ZBKC, 206 RISCV_ISA_EXT_ZKSED, 207 RISCV_ISA_EXT_ZKSH 208 }; 209 210 #define RISCV_ISA_EXT_ZVKN \ 211 RISCV_ISA_EXT_ZVKNED, \ 212 RISCV_ISA_EXT_ZVKNHB, \ 213 RISCV_ISA_EXT_ZVKB, \ 214 RISCV_ISA_EXT_ZVKT 215 216 static const unsigned int riscv_zvkn_bundled_exts[] = { 217 RISCV_ISA_EXT_ZVKN 218 }; 219 220 static const unsigned int riscv_zvknc_bundled_exts[] = { 221 RISCV_ISA_EXT_ZVKN, 222 RISCV_ISA_EXT_ZVBC 223 }; 224 225 static const unsigned int riscv_zvkng_bundled_exts[] = { 226 RISCV_ISA_EXT_ZVKN, 227 RISCV_ISA_EXT_ZVKG 228 }; 229 230 #define RISCV_ISA_EXT_ZVKS \ 231 RISCV_ISA_EXT_ZVKSED, \ 232 RISCV_ISA_EXT_ZVKSH, \ 233 RISCV_ISA_EXT_ZVKB, \ 234 RISCV_ISA_EXT_ZVKT 235 236 static const unsigned int riscv_zvks_bundled_exts[] = { 237 RISCV_ISA_EXT_ZVKS 238 }; 239 240 static const unsigned int riscv_zvksc_bundled_exts[] = { 241 RISCV_ISA_EXT_ZVKS, 242 RISCV_ISA_EXT_ZVBC 243 }; 244 245 static const unsigned int riscv_zvksg_bundled_exts[] = { 246 RISCV_ISA_EXT_ZVKS, 247 RISCV_ISA_EXT_ZVKG 248 }; 249 250 static const unsigned int riscv_zvbb_exts[] = { 251 RISCV_ISA_EXT_ZVKB 252 }; 253 254 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ 255 RISCV_ISA_EXT_ZVE64X, \ 256 RISCV_ISA_EXT_ZVE32F, \ 257 RISCV_ISA_EXT_ZVE32X 258 259 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ 260 RISCV_ISA_EXT_ZVE64F, \ 261 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST 262 263 #define RISCV_ISA_EXT_V_IMPLY_LIST \ 264 RISCV_ISA_EXT_ZVE64D, \ 265 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST 266 267 static const unsigned int riscv_zve32f_exts[] = { 268 RISCV_ISA_EXT_ZVE32X 269 }; 270 271 static const unsigned int riscv_zve64f_exts[] = { 272 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST 273 }; 274 275 static const unsigned int riscv_zve64d_exts[] = { 276 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST 277 }; 278 279 static const unsigned int riscv_v_exts[] = { 280 RISCV_ISA_EXT_V_IMPLY_LIST 281 }; 282 283 static const unsigned int riscv_zve64x_exts[] = { 284 RISCV_ISA_EXT_ZVE32X, 285 RISCV_ISA_EXT_ZVE64X 286 }; 287 288 /* 289 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V 290 * privileged ISA, the existence of the CSRs is implied by any extension which 291 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the 292 * existence of the CSR, and treat it as a subset of those other extensions. 293 */ 294 static const unsigned int riscv_xlinuxenvcfg_exts[] = { 295 RISCV_ISA_EXT_XLINUXENVCFG 296 }; 297 298 /* 299 * Zc* spec states that: 300 * - C always implies Zca 301 * - C+F implies Zcf (RV32 only) 302 * - C+D implies Zcd 303 * 304 * These extensions will be enabled and then validated depending on the 305 * availability of F/D RV32. 306 */ 307 static const unsigned int riscv_c_exts[] = { 308 RISCV_ISA_EXT_ZCA, 309 RISCV_ISA_EXT_ZCF, 310 RISCV_ISA_EXT_ZCD, 311 }; 312 313 /* 314 * The canonical order of ISA extension names in the ISA string is defined in 315 * chapter 27 of the unprivileged specification. 316 * 317 * Ordinarily, for in-kernel data structures, this order is unimportant but 318 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. 319 * 320 * The specification uses vague wording, such as should, when it comes to 321 * ordering, so for our purposes the following rules apply: 322 * 323 * 1. All multi-letter extensions must be separated from other extensions by an 324 * underscore. 325 * 326 * 2. Additional standard extensions (starting with 'Z') must be sorted after 327 * single-letter extensions and before any higher-privileged extensions. 328 * 329 * 3. The first letter following the 'Z' conventionally indicates the most 330 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 331 * If multiple 'Z' extensions are named, they must be ordered first by 332 * category, then alphabetically within a category. 333 * 334 * 3. Standard supervisor-level extensions (starting with 'S') must be listed 335 * after standard unprivileged extensions. If multiple supervisor-level 336 * extensions are listed, they must be ordered alphabetically. 337 * 338 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed 339 * after any lower-privileged, standard extensions. If multiple 340 * machine-level extensions are listed, they must be ordered 341 * alphabetically. 342 * 343 * 5. Non-standard extensions (starting with 'X') must be listed after all 344 * standard extensions. If multiple non-standard extensions are listed, they 345 * must be ordered alphabetically. 346 * 347 * An example string following the order is: 348 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 349 * 350 * New entries to this struct should follow the ordering rules described above. 351 */ 352 const struct riscv_isa_ext_data riscv_isa_ext[] = { 353 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), 354 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), 355 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), 356 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), 357 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), 358 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), 359 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), 360 __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), 361 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), 362 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, 363 riscv_ext_zicbom_validate), 364 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, 365 riscv_ext_zicboz_validate), 366 __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), 367 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 368 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), 369 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), 370 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), 371 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), 372 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 373 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), 374 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), 375 __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), 376 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), 377 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), 378 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), 379 __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends), 380 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), 381 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), 382 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), 383 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), 384 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), 385 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate), 386 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends), 387 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), 388 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), 389 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), 390 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), 391 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), 392 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), 393 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), 394 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), 395 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), 396 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), 397 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), 398 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), 399 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), 400 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), 401 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), 402 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), 403 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), 404 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), 405 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), 406 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), 407 __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), 408 __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), 409 __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), 410 __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), 411 __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), 412 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN, riscv_vector_f_validate), 413 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA, 414 riscv_ext_zvfbfwma_validate), 415 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), 416 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), 417 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), 418 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), 419 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), 420 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), 421 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), 422 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), 423 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), 424 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), 425 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), 426 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), 427 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), 428 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), 429 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), 430 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), 431 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), 432 __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), 433 __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), 434 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), 435 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), 436 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 437 __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), 438 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 439 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), 440 __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate), 441 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 442 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 443 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 444 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), 445 }; 446 447 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); 448 449 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap) 450 { 451 if (ext->id != RISCV_ISA_EXT_INVALID) 452 set_bit(ext->id, bitmap); 453 454 for (int i = 0; i < ext->subset_ext_size; i++) { 455 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID) 456 set_bit(ext->subset_ext_ids[i], bitmap); 457 } 458 } 459 460 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id) 461 { 462 for (int i = 0; i < riscv_isa_ext_count; i++) { 463 if (riscv_isa_ext[i].id == ext_id) 464 return &riscv_isa_ext[i]; 465 } 466 467 return NULL; 468 } 469 470 /* 471 * "Resolve" a source ISA bitmap into one that matches kernel configuration as 472 * well as correct extension dependencies. Some extensions depends on specific 473 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance) 474 * and this function will actually validate all the extensions provided in 475 * source_isa into the resolved_isa based on extensions validate() callbacks. 476 */ 477 static void __init riscv_resolve_isa(unsigned long *source_isa, 478 unsigned long *resolved_isa, unsigned long *this_hwcap, 479 unsigned long *isa2hwcap) 480 { 481 bool loop; 482 const struct riscv_isa_ext_data *ext; 483 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX); 484 int max_loop_count = riscv_isa_ext_count, ret; 485 unsigned int bit; 486 487 do { 488 loop = false; 489 if (max_loop_count-- < 0) { 490 pr_err("Failed to reach a stable ISA state\n"); 491 return; 492 } 493 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX); 494 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) { 495 ext = riscv_get_isa_ext_data(bit); 496 497 if (ext && ext->validate) { 498 ret = ext->validate(ext, resolved_isa); 499 if (ret == -EPROBE_DEFER) { 500 loop = true; 501 continue; 502 } else if (ret) { 503 /* Disable the extension entirely */ 504 clear_bit(bit, source_isa); 505 continue; 506 } 507 } 508 509 set_bit(bit, resolved_isa); 510 /* No need to keep it in source isa now that it is enabled */ 511 clear_bit(bit, source_isa); 512 513 /* Single letter extensions get set in hwcap */ 514 if (bit < RISCV_ISA_EXT_BASE) 515 *this_hwcap |= isa2hwcap[bit]; 516 } 517 } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX)); 518 } 519 520 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap) 521 { 522 for (int i = 0; i < riscv_isa_ext_count; i++) { 523 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i]; 524 525 if ((name_end - name == strlen(ext->name)) && 526 !strncasecmp(name, ext->name, name_end - name)) { 527 riscv_isa_set_ext(ext, bitmap); 528 break; 529 } 530 } 531 } 532 533 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap) 534 { 535 /* 536 * For all possible cpus, we have already validated in 537 * the boot process that they at least contain "rv" and 538 * whichever of "32"/"64" this kernel supports, and so this 539 * section can be skipped. 540 */ 541 isa += 4; 542 543 while (*isa) { 544 const char *ext = isa++; 545 const char *ext_end = isa; 546 bool ext_err = false; 547 548 switch (*ext) { 549 case 'x': 550 case 'X': 551 if (acpi_disabled) 552 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); 553 /* 554 * To skip an extension, we find its end. 555 * As multi-letter extensions must be split from other multi-letter 556 * extensions with an "_", the end of a multi-letter extension will 557 * either be the null character or the "_" at the start of the next 558 * multi-letter extension. 559 */ 560 for (; *isa && *isa != '_'; ++isa) 561 ; 562 ext_err = true; 563 break; 564 case 's': 565 /* 566 * Workaround for invalid single-letter 's' & 'u' (QEMU). 567 * No need to set the bit in riscv_isa as 's' & 'u' are 568 * not valid ISA extensions. It works unless the first 569 * multi-letter extension in the ISA string begins with 570 * "Su" and is not prefixed with an underscore. 571 */ 572 if (ext[-1] != '_' && ext[1] == 'u') { 573 ++isa; 574 ext_err = true; 575 break; 576 } 577 fallthrough; 578 case 'S': 579 case 'z': 580 case 'Z': 581 /* 582 * Before attempting to parse the extension itself, we find its end. 583 * As multi-letter extensions must be split from other multi-letter 584 * extensions with an "_", the end of a multi-letter extension will 585 * either be the null character or the "_" at the start of the next 586 * multi-letter extension. 587 * 588 * Next, as the extensions version is currently ignored, we 589 * eliminate that portion. This is done by parsing backwards from 590 * the end of the extension, removing any numbers. This may be a 591 * major or minor number however, so the process is repeated if a 592 * minor number was found. 593 * 594 * ext_end is intended to represent the first character *after* the 595 * name portion of an extension, but will be decremented to the last 596 * character itself while eliminating the extensions version number. 597 * A simple re-increment solves this problem. 598 */ 599 for (; *isa && *isa != '_'; ++isa) 600 if (unlikely(!isalnum(*isa))) 601 ext_err = true; 602 603 ext_end = isa; 604 if (unlikely(ext_err)) 605 break; 606 607 if (!isdigit(ext_end[-1])) 608 break; 609 610 while (isdigit(*--ext_end)) 611 ; 612 613 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { 614 ++ext_end; 615 break; 616 } 617 618 while (isdigit(*--ext_end)) 619 ; 620 621 ++ext_end; 622 break; 623 default: 624 /* 625 * Things are a little easier for single-letter extensions, as they 626 * are parsed forwards. 627 * 628 * After checking that our starting position is valid, we need to 629 * ensure that, when isa was incremented at the start of the loop, 630 * that it arrived at the start of the next extension. 631 * 632 * If we are already on a non-digit, there is nothing to do. Either 633 * we have a multi-letter extension's _, or the start of an 634 * extension. 635 * 636 * Otherwise we have found the current extension's major version 637 * number. Parse past it, and a subsequent p/minor version number 638 * if present. The `p` extension must not appear immediately after 639 * a number, so there is no fear of missing it. 640 * 641 */ 642 if (unlikely(!isalpha(*ext))) { 643 ext_err = true; 644 break; 645 } 646 647 if (!isdigit(*isa)) 648 break; 649 650 while (isdigit(*++isa)) 651 ; 652 653 if (tolower(*isa) != 'p') 654 break; 655 656 if (!isdigit(*++isa)) { 657 --isa; 658 break; 659 } 660 661 while (isdigit(*++isa)) 662 ; 663 664 break; 665 } 666 667 /* 668 * The parser expects that at the start of an iteration isa points to the 669 * first character of the next extension. As we stop parsing an extension 670 * on meeting a non-alphanumeric character, an extra increment is needed 671 * where the succeeding extension is a multi-letter prefixed with an "_". 672 */ 673 if (*isa == '_') 674 ++isa; 675 676 if (unlikely(ext_err)) 677 continue; 678 679 match_isa_ext(ext, ext_end, bitmap); 680 } 681 } 682 683 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) 684 { 685 struct device_node *node; 686 const char *isa; 687 int rc; 688 struct acpi_table_header *rhct; 689 acpi_status status; 690 unsigned int cpu; 691 u64 boot_vendorid; 692 u64 boot_archid; 693 694 if (!acpi_disabled) { 695 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); 696 if (ACPI_FAILURE(status)) 697 return; 698 } 699 700 boot_vendorid = riscv_get_mvendorid(); 701 boot_archid = riscv_get_marchid(); 702 703 for_each_possible_cpu(cpu) { 704 struct riscv_isainfo *isainfo = &hart_isa[cpu]; 705 unsigned long this_hwcap = 0; 706 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 }; 707 708 if (acpi_disabled) { 709 node = of_cpu_device_node_get(cpu); 710 if (!node) { 711 pr_warn("Unable to find cpu node\n"); 712 continue; 713 } 714 715 rc = of_property_read_string(node, "riscv,isa", &isa); 716 of_node_put(node); 717 if (rc) { 718 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); 719 continue; 720 } 721 } else { 722 rc = acpi_get_riscv_isa(rhct, cpu, &isa); 723 if (rc < 0) { 724 pr_warn("Unable to get ISA for the hart - %d\n", cpu); 725 continue; 726 } 727 } 728 729 riscv_parse_isa_string(isa, source_isa); 730 731 /* 732 * These ones were as they were part of the base ISA when the 733 * port & dt-bindings were upstreamed, and so can be set 734 * unconditionally where `i` is in riscv,isa on DT systems. 735 */ 736 if (acpi_disabled) { 737 set_bit(RISCV_ISA_EXT_ZICSR, source_isa); 738 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa); 739 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa); 740 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa); 741 } 742 743 /* 744 * "V" in ISA strings is ambiguous in practice: it should mean 745 * just the standard V-1.0 but vendors aren't well behaved. 746 * Many vendors with T-Head CPU cores which implement the 0.7.1 747 * version of the vector specification put "v" into their DTs. 748 * CPU cores with the ratified spec will contain non-zero 749 * marchid. 750 */ 751 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) { 752 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; 753 clear_bit(RISCV_ISA_EXT_v, source_isa); 754 } 755 756 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); 757 758 /* 759 * All "okay" hart should have same isa. Set HWCAP based on 760 * common capabilities of every "okay" hart, in case they don't 761 * have. 762 */ 763 if (elf_hwcap) 764 elf_hwcap &= this_hwcap; 765 else 766 elf_hwcap = this_hwcap; 767 768 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 769 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 770 else 771 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 772 } 773 774 if (!acpi_disabled && rhct) 775 acpi_put_table((struct acpi_table_header *)rhct); 776 } 777 778 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu) 779 { 780 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) 781 return; 782 783 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { 784 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; 785 786 for (int j = 0; j < ext_list->ext_data_count; j++) { 787 const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; 788 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu]; 789 790 if (of_property_match_string(cpu_node, "riscv,isa-extensions", 791 ext.property) < 0) 792 continue; 793 794 /* 795 * Assume that subset extensions are all members of the 796 * same vendor. 797 */ 798 if (ext.subset_ext_size) 799 for (int k = 0; k < ext.subset_ext_size; k++) 800 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); 801 802 set_bit(ext.id, isavendorinfo->isa); 803 } 804 } 805 } 806 807 /* 808 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that 809 * are shared across CPUs for that vendor. 810 */ 811 static void __init riscv_fill_vendor_ext_list(int cpu) 812 { 813 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT)) 814 return; 815 816 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { 817 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; 818 819 if (!ext_list->is_initialized) { 820 bitmap_copy(ext_list->all_harts_isa_bitmap.isa, 821 ext_list->per_hart_isa_bitmap[cpu].isa, 822 RISCV_ISA_VENDOR_EXT_MAX); 823 ext_list->is_initialized = true; 824 } else { 825 bitmap_and(ext_list->all_harts_isa_bitmap.isa, 826 ext_list->all_harts_isa_bitmap.isa, 827 ext_list->per_hart_isa_bitmap[cpu].isa, 828 RISCV_ISA_VENDOR_EXT_MAX); 829 } 830 } 831 } 832 833 static int has_thead_homogeneous_vlenb(void) 834 { 835 int cpu; 836 u32 prev_vlenb = 0; 837 u32 vlenb; 838 839 /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */ 840 if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) 841 return 0; 842 843 for_each_possible_cpu(cpu) { 844 struct device_node *cpu_node; 845 846 cpu_node = of_cpu_device_node_get(cpu); 847 if (!cpu_node) { 848 pr_warn("Unable to find cpu node\n"); 849 return -ENOENT; 850 } 851 852 if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) { 853 of_node_put(cpu_node); 854 855 if (prev_vlenb) 856 return -ENOENT; 857 continue; 858 } 859 860 if (prev_vlenb && vlenb != prev_vlenb) { 861 of_node_put(cpu_node); 862 return -ENOENT; 863 } 864 865 prev_vlenb = vlenb; 866 of_node_put(cpu_node); 867 } 868 869 thead_vlenb_of = vlenb; 870 return 0; 871 } 872 873 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) 874 { 875 unsigned int cpu; 876 bool mitigated; 877 878 for_each_possible_cpu(cpu) { 879 unsigned long this_hwcap = 0; 880 struct device_node *cpu_node; 881 struct riscv_isainfo *isainfo = &hart_isa[cpu]; 882 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 }; 883 884 cpu_node = of_cpu_device_node_get(cpu); 885 if (!cpu_node) { 886 pr_warn("Unable to find cpu node\n"); 887 continue; 888 } 889 890 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { 891 of_node_put(cpu_node); 892 continue; 893 } 894 895 for (int i = 0; i < riscv_isa_ext_count; i++) { 896 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i]; 897 898 if (of_property_match_string(cpu_node, "riscv,isa-extensions", 899 ext->property) < 0) 900 continue; 901 902 riscv_isa_set_ext(ext, source_isa); 903 } 904 905 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap); 906 riscv_fill_cpu_vendor_ext(cpu_node, cpu); 907 908 of_node_put(cpu_node); 909 910 /* 911 * All "okay" harts should have same isa. Set HWCAP based on 912 * common capabilities of every "okay" hart, in case they don't. 913 */ 914 if (elf_hwcap) 915 elf_hwcap &= this_hwcap; 916 else 917 elf_hwcap = this_hwcap; 918 919 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 920 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 921 else 922 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); 923 924 riscv_fill_vendor_ext_list(cpu); 925 } 926 927 /* 928 * Execute ghostwrite mitigation immediately after detecting extensions 929 * to disable xtheadvector if necessary. 930 */ 931 mitigated = ghostwrite_enable_mitigation(); 932 933 if (!mitigated && has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() < 0) { 934 pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n"); 935 disable_xtheadvector(); 936 } 937 938 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) 939 return -ENOENT; 940 941 return 0; 942 } 943 944 #ifdef CONFIG_RISCV_ISA_FALLBACK 945 bool __initdata riscv_isa_fallback = true; 946 #else 947 bool __initdata riscv_isa_fallback; 948 static int __init riscv_isa_fallback_setup(char *__unused) 949 { 950 riscv_isa_fallback = true; 951 return 1; 952 } 953 early_param("riscv_isa_fallback", riscv_isa_fallback_setup); 954 #endif 955 956 void __init riscv_fill_hwcap(void) 957 { 958 char print_str[NUM_ALPHA_EXTS + 1]; 959 unsigned long isa2hwcap[26] = {0}; 960 int i, j; 961 962 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; 963 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; 964 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; 965 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; 966 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; 967 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; 968 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; 969 970 if (!acpi_disabled) { 971 riscv_fill_hwcap_from_isa_string(isa2hwcap); 972 } else { 973 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap); 974 975 if (ret && riscv_isa_fallback) { 976 pr_info("Falling back to deprecated \"riscv,isa\"\n"); 977 riscv_fill_hwcap_from_isa_string(isa2hwcap); 978 } 979 } 980 981 /* 982 * We don't support systems with F but without D, so mask those out 983 * here. 984 */ 985 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { 986 pr_info("This kernel does not support systems with F but not D\n"); 987 elf_hwcap &= ~COMPAT_HWCAP_ISA_F; 988 } 989 990 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) || 991 has_xtheadvector_no_alternatives()) { 992 /* 993 * This cannot fail when called on the boot hart 994 */ 995 riscv_v_setup_vsize(); 996 } 997 998 if (elf_hwcap & COMPAT_HWCAP_ISA_V) { 999 /* 1000 * ISA string in device tree might have 'v' flag, but 1001 * CONFIG_RISCV_ISA_V is disabled in kernel. 1002 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. 1003 */ 1004 if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) 1005 elf_hwcap &= ~COMPAT_HWCAP_ISA_V; 1006 } 1007 1008 memset(print_str, 0, sizeof(print_str)); 1009 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 1010 if (riscv_isa[0] & BIT_MASK(i)) 1011 print_str[j++] = (char)('a' + i); 1012 pr_info("riscv: base ISA extensions %s\n", print_str); 1013 1014 memset(print_str, 0, sizeof(print_str)); 1015 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) 1016 if (elf_hwcap & BIT_MASK(i)) 1017 print_str[j++] = (char)('a' + i); 1018 pr_info("riscv: ELF capabilities %s\n", print_str); 1019 } 1020 1021 unsigned long riscv_get_elf_hwcap(void) 1022 { 1023 unsigned long hwcap; 1024 1025 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); 1026 1027 if (!riscv_v_vstate_ctrl_user_allowed()) 1028 hwcap &= ~COMPAT_HWCAP_ISA_V; 1029 1030 return hwcap; 1031 } 1032 1033 void __init riscv_user_isa_enable(void) 1034 { 1035 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) 1036 current->thread.envcfg |= ENVCFG_CBZE; 1037 else if (any_cpu_has_zicboz) 1038 pr_warn("Zicboz disabled as it is unavailable on some harts\n"); 1039 } 1040 1041 #ifdef CONFIG_RISCV_ALTERNATIVE 1042 /* 1043 * Alternative patch sites consider 48 bits when determining when to patch 1044 * the old instruction sequence with the new. These bits are broken into a 1045 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the 1046 * patch site is for an erratum, identified by the 32-bit patch ID. When 1047 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures 1048 * further break down patch ID into two 16-bit numbers. The lower 16 bits 1049 * are the cpufeature ID and the upper 16 bits are used for a value specific 1050 * to the cpufeature and patch site. If the upper 16 bits are zero, then it 1051 * implies no specific value is specified. cpufeatures that want to control 1052 * patching on a per-site basis will provide non-zero values and implement 1053 * checks here. The checks return true when patching should be done, and 1054 * false otherwise. 1055 */ 1056 static bool riscv_cpufeature_patch_check(u16 id, u16 value) 1057 { 1058 if (!value) 1059 return true; 1060 1061 switch (id) { 1062 case RISCV_ISA_EXT_ZICBOZ: 1063 /* 1064 * Zicboz alternative applications provide the maximum 1065 * supported block size order, or zero when it doesn't 1066 * matter. If the current block size exceeds the maximum, 1067 * then the alternative cannot be applied. 1068 */ 1069 return riscv_cboz_block_size <= (1U << value); 1070 } 1071 1072 return false; 1073 } 1074 1075 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, 1076 struct alt_entry *end, 1077 unsigned int stage) 1078 { 1079 struct alt_entry *alt; 1080 void *oldptr, *altptr; 1081 u16 id, value, vendor; 1082 1083 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) 1084 return; 1085 1086 for (alt = begin; alt < end; alt++) { 1087 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); 1088 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id); 1089 1090 /* 1091 * Any alternative with a patch_id that is less than 1092 * RISCV_ISA_EXT_MAX is interpreted as a standard extension. 1093 * 1094 * Any alternative with patch_id that is greater than or equal 1095 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a 1096 * vendor extension. 1097 */ 1098 if (id < RISCV_ISA_EXT_MAX) { 1099 /* 1100 * This patch should be treated as errata so skip 1101 * processing here. 1102 */ 1103 if (alt->vendor_id != 0) 1104 continue; 1105 1106 if (!__riscv_isa_extension_available(NULL, id)) 1107 continue; 1108 1109 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); 1110 if (!riscv_cpufeature_patch_check(id, value)) 1111 continue; 1112 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) { 1113 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, 1114 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE)) 1115 continue; 1116 } else { 1117 WARN(1, "This extension id:%d is not in ISA extension list", id); 1118 continue; 1119 } 1120 1121 oldptr = ALT_OLD_PTR(alt); 1122 altptr = ALT_ALT_PTR(alt); 1123 1124 mutex_lock(&text_mutex); 1125 patch_text_nosync(oldptr, altptr, alt->alt_len); 1126 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); 1127 mutex_unlock(&text_mutex); 1128 } 1129 } 1130 #endif 1131