xref: /linux/arch/riscv/kernel/cpufeature.c (revision 1631ba1259d6d7f49b6028f2a1a0fa02be1c522a) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copied from arch/arm64/kernel/cpufeature.c
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  * Copyright (C) 2017 SiFive
7  */
8 
9 #include <linux/bitmap.h>
10 #include <linux/ctype.h>
11 #include <linux/libfdt.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <asm/alternative.h>
15 #include <asm/cacheflush.h>
16 #include <asm/errata_list.h>
17 #include <asm/hwcap.h>
18 #include <asm/patch.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/smp.h>
22 #include <asm/switch_to.h>
23 
24 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
25 
26 unsigned long elf_hwcap __read_mostly;
27 
28 /* Host ISA bitmap */
29 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
30 
31 __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
32 EXPORT_SYMBOL(riscv_isa_ext_keys);
33 
34 /**
35  * riscv_isa_extension_base() - Get base extension word
36  *
37  * @isa_bitmap: ISA bitmap to use
38  * Return: base extension word as unsigned long value
39  *
40  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
41  */
42 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
43 {
44 	if (!isa_bitmap)
45 		return riscv_isa[0];
46 	return isa_bitmap[0];
47 }
48 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
49 
50 /**
51  * __riscv_isa_extension_available() - Check whether given extension
52  * is available or not
53  *
54  * @isa_bitmap: ISA bitmap to use
55  * @bit: bit position of the desired extension
56  * Return: true or false
57  *
58  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
59  */
60 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
61 {
62 	const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
63 
64 	if (bit >= RISCV_ISA_EXT_MAX)
65 		return false;
66 
67 	return test_bit(bit, bmap) ? true : false;
68 }
69 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
70 
71 void __init riscv_fill_hwcap(void)
72 {
73 	struct device_node *node;
74 	const char *isa;
75 	char print_str[NUM_ALPHA_EXTS + 1];
76 	int i, j;
77 	static unsigned long isa2hwcap[256] = {0};
78 
79 	isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
80 	isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
81 	isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
82 	isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
83 	isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
84 	isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
85 
86 	elf_hwcap = 0;
87 
88 	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
89 
90 	for_each_of_cpu_node(node) {
91 		unsigned long this_hwcap = 0;
92 		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
93 		const char *temp;
94 
95 		if (riscv_of_processor_hartid(node) < 0)
96 			continue;
97 
98 		if (of_property_read_string(node, "riscv,isa", &isa)) {
99 			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
100 			continue;
101 		}
102 
103 		temp = isa;
104 #if IS_ENABLED(CONFIG_32BIT)
105 		if (!strncmp(isa, "rv32", 4))
106 			isa += 4;
107 #elif IS_ENABLED(CONFIG_64BIT)
108 		if (!strncmp(isa, "rv64", 4))
109 			isa += 4;
110 #endif
111 		/* The riscv,isa DT property must start with rv64 or rv32 */
112 		if (temp == isa)
113 			continue;
114 		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
115 		for (; *isa; ++isa) {
116 			const char *ext = isa++;
117 			const char *ext_end = isa;
118 			bool ext_long = false, ext_err = false;
119 
120 			switch (*ext) {
121 			case 's':
122 				/**
123 				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
124 				 * No need to set the bit in riscv_isa as 's' & 'u' are
125 				 * not valid ISA extensions. It works until multi-letter
126 				 * extension starting with "Su" appears.
127 				 */
128 				if (ext[-1] != '_' && ext[1] == 'u') {
129 					++isa;
130 					ext_err = true;
131 					break;
132 				}
133 				fallthrough;
134 			case 'x':
135 			case 'z':
136 				ext_long = true;
137 				/* Multi-letter extension must be delimited */
138 				for (; *isa && *isa != '_'; ++isa)
139 					if (unlikely(!islower(*isa)
140 						     && !isdigit(*isa)))
141 						ext_err = true;
142 				/* Parse backwards */
143 				ext_end = isa;
144 				if (unlikely(ext_err))
145 					break;
146 				if (!isdigit(ext_end[-1]))
147 					break;
148 				/* Skip the minor version */
149 				while (isdigit(*--ext_end))
150 					;
151 				if (ext_end[0] != 'p'
152 				    || !isdigit(ext_end[-1])) {
153 					/* Advance it to offset the pre-decrement */
154 					++ext_end;
155 					break;
156 				}
157 				/* Skip the major version */
158 				while (isdigit(*--ext_end))
159 					;
160 				++ext_end;
161 				break;
162 			default:
163 				if (unlikely(!islower(*ext))) {
164 					ext_err = true;
165 					break;
166 				}
167 				/* Find next extension */
168 				if (!isdigit(*isa))
169 					break;
170 				/* Skip the minor version */
171 				while (isdigit(*++isa))
172 					;
173 				if (*isa != 'p')
174 					break;
175 				if (!isdigit(*++isa)) {
176 					--isa;
177 					break;
178 				}
179 				/* Skip the major version */
180 				while (isdigit(*++isa))
181 					;
182 				break;
183 			}
184 			if (*isa != '_')
185 				--isa;
186 
187 #define SET_ISA_EXT_MAP(name, bit)						\
188 			do {							\
189 				if ((ext_end - ext == sizeof(name) - 1) &&	\
190 				     !memcmp(ext, name, sizeof(name) - 1))	\
191 					set_bit(bit, this_isa);			\
192 			} while (false)						\
193 
194 			if (unlikely(ext_err))
195 				continue;
196 			if (!ext_long) {
197 				this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
198 				set_bit(*ext - 'a', this_isa);
199 			} else {
200 				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
201 				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
202 				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
203 			}
204 #undef SET_ISA_EXT_MAP
205 		}
206 
207 		/*
208 		 * All "okay" hart should have same isa. Set HWCAP based on
209 		 * common capabilities of every "okay" hart, in case they don't
210 		 * have.
211 		 */
212 		if (elf_hwcap)
213 			elf_hwcap &= this_hwcap;
214 		else
215 			elf_hwcap = this_hwcap;
216 
217 		if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
218 			bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
219 		else
220 			bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
221 	}
222 
223 	/* We don't support systems with F but without D, so mask those out
224 	 * here. */
225 	if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
226 		pr_info("This kernel does not support systems with F but not D\n");
227 		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
228 	}
229 
230 	memset(print_str, 0, sizeof(print_str));
231 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
232 		if (riscv_isa[0] & BIT_MASK(i))
233 			print_str[j++] = (char)('a' + i);
234 	pr_info("riscv: base ISA extensions %s\n", print_str);
235 
236 	memset(print_str, 0, sizeof(print_str));
237 	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
238 		if (elf_hwcap & BIT_MASK(i))
239 			print_str[j++] = (char)('a' + i);
240 	pr_info("riscv: ELF capabilities %s\n", print_str);
241 
242 	for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
243 		j = riscv_isa_ext2key(i);
244 		if (j >= 0)
245 			static_branch_enable(&riscv_isa_ext_keys[j]);
246 	}
247 }
248 
249 #ifdef CONFIG_RISCV_ALTERNATIVE
250 static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
251 {
252 #ifdef CONFIG_RISCV_ISA_SVPBMT
253 	switch (stage) {
254 	case RISCV_ALTERNATIVES_EARLY_BOOT:
255 		return false;
256 	default:
257 		return riscv_isa_extension_available(NULL, SVPBMT);
258 	}
259 #endif
260 
261 	return false;
262 }
263 
264 static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
265 {
266 #ifdef CONFIG_RISCV_ISA_ZICBOM
267 	switch (stage) {
268 	case RISCV_ALTERNATIVES_EARLY_BOOT:
269 		return false;
270 	default:
271 		if (riscv_isa_extension_available(NULL, ZICBOM)) {
272 			riscv_noncoherent_supported();
273 			return true;
274 		} else {
275 			return false;
276 		}
277 	}
278 #endif
279 
280 	return false;
281 }
282 
283 /*
284  * Probe presence of individual extensions.
285  *
286  * This code may also be executed before kernel relocation, so we cannot use
287  * addresses generated by the address-of operator as they won't be valid in
288  * this context.
289  */
290 static u32 __init_or_module cpufeature_probe(unsigned int stage)
291 {
292 	u32 cpu_req_feature = 0;
293 
294 	if (cpufeature_probe_svpbmt(stage))
295 		cpu_req_feature |= (1U << CPUFEATURE_SVPBMT);
296 
297 	if (cpufeature_probe_zicbom(stage))
298 		cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
299 
300 	return cpu_req_feature;
301 }
302 
303 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
304 						  struct alt_entry *end,
305 						  unsigned int stage)
306 {
307 	u32 cpu_req_feature = cpufeature_probe(stage);
308 	struct alt_entry *alt;
309 	u32 tmp;
310 
311 	for (alt = begin; alt < end; alt++) {
312 		if (alt->vendor_id != 0)
313 			continue;
314 		if (alt->errata_id >= CPUFEATURE_NUMBER) {
315 			WARN(1, "This feature id:%d is not in kernel cpufeature list",
316 				alt->errata_id);
317 			continue;
318 		}
319 
320 		tmp = (1U << alt->errata_id);
321 		if (cpu_req_feature & tmp)
322 			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
323 	}
324 }
325 #endif
326