1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Regents of the University of California 4 */ 5 6 #include <linux/cpu.h> 7 #include <linux/init.h> 8 #include <linux/seq_file.h> 9 #include <linux/of.h> 10 #include <asm/cpufeature.h> 11 #include <asm/csr.h> 12 #include <asm/hwcap.h> 13 #include <asm/sbi.h> 14 #include <asm/smp.h> 15 #include <asm/pgtable.h> 16 17 /* 18 * Returns the hart ID of the given device tree node, or -ENODEV if the node 19 * isn't an enabled and valid RISC-V hart node. 20 */ 21 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) 22 { 23 const char *isa; 24 25 if (!of_device_is_compatible(node, "riscv")) { 26 pr_warn("Found incompatible CPU\n"); 27 return -ENODEV; 28 } 29 30 *hart = (unsigned long) of_get_cpu_hwid(node, 0); 31 if (*hart == ~0UL) { 32 pr_warn("Found CPU without hart ID\n"); 33 return -ENODEV; 34 } 35 36 if (!of_device_is_available(node)) { 37 pr_info("CPU with hartid=%lu is not available\n", *hart); 38 return -ENODEV; 39 } 40 41 if (of_property_read_string(node, "riscv,isa", &isa)) { 42 pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); 43 return -ENODEV; 44 } 45 if (isa[0] != 'r' || isa[1] != 'v') { 46 pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); 47 return -ENODEV; 48 } 49 50 return 0; 51 } 52 53 /* 54 * Find hart ID of the CPU DT node under which given DT node falls. 55 * 56 * To achieve this, we walk up the DT tree until we find an active 57 * RISC-V core (HART) node and extract the cpuid from it. 58 */ 59 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) 60 { 61 int rc; 62 63 for (; node; node = node->parent) { 64 if (of_device_is_compatible(node, "riscv")) { 65 rc = riscv_of_processor_hartid(node, hartid); 66 if (!rc) 67 return 0; 68 } 69 } 70 71 return -1; 72 } 73 74 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); 75 76 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) 77 { 78 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 79 80 return ci->mvendorid; 81 } 82 EXPORT_SYMBOL(riscv_cached_mvendorid); 83 84 unsigned long riscv_cached_marchid(unsigned int cpu_id) 85 { 86 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 87 88 return ci->marchid; 89 } 90 EXPORT_SYMBOL(riscv_cached_marchid); 91 92 unsigned long riscv_cached_mimpid(unsigned int cpu_id) 93 { 94 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 95 96 return ci->mimpid; 97 } 98 EXPORT_SYMBOL(riscv_cached_mimpid); 99 100 static int riscv_cpuinfo_starting(unsigned int cpu) 101 { 102 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); 103 104 #if IS_ENABLED(CONFIG_RISCV_SBI) 105 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); 106 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); 107 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); 108 #elif IS_ENABLED(CONFIG_RISCV_M_MODE) 109 ci->mvendorid = csr_read(CSR_MVENDORID); 110 ci->marchid = csr_read(CSR_MARCHID); 111 ci->mimpid = csr_read(CSR_MIMPID); 112 #else 113 ci->mvendorid = 0; 114 ci->marchid = 0; 115 ci->mimpid = 0; 116 #endif 117 118 return 0; 119 } 120 121 static int __init riscv_cpuinfo_init(void) 122 { 123 int ret; 124 125 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting", 126 riscv_cpuinfo_starting, NULL); 127 if (ret < 0) { 128 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 129 return ret; 130 } 131 132 return 0; 133 } 134 arch_initcall(riscv_cpuinfo_init); 135 136 #ifdef CONFIG_PROC_FS 137 138 #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ 139 { \ 140 .uprop = #UPROP, \ 141 .isa_ext_id = EXTID, \ 142 } 143 144 /* 145 * The canonical order of ISA extension names in the ISA string is defined in 146 * chapter 27 of the unprivileged specification. 147 * 148 * Ordinarily, for in-kernel data structures, this order is unimportant but 149 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. 150 * 151 * The specification uses vague wording, such as should, when it comes to 152 * ordering, so for our purposes the following rules apply: 153 * 154 * 1. All multi-letter extensions must be separated from other extensions by an 155 * underscore. 156 * 157 * 2. Additional standard extensions (starting with 'Z') must be sorted after 158 * single-letter extensions and before any higher-privileged extensions. 159 160 * 3. The first letter following the 'Z' conventionally indicates the most 161 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 162 * If multiple 'Z' extensions are named, they must be ordered first by 163 * category, then alphabetically within a category. 164 * 165 * 3. Standard supervisor-level extensions (starting with 'S') must be listed 166 * after standard unprivileged extensions. If multiple supervisor-level 167 * extensions are listed, they must be ordered alphabetically. 168 * 169 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed 170 * after any lower-privileged, standard extensions. If multiple 171 * machine-level extensions are listed, they must be ordered 172 * alphabetically. 173 * 174 * 5. Non-standard extensions (starting with 'X') must be listed after all 175 * standard extensions. If multiple non-standard extensions are listed, they 176 * must be ordered alphabetically. 177 * 178 * An example string following the order is: 179 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux 180 * 181 * New entries to this struct should follow the ordering rules described above. 182 */ 183 static struct riscv_isa_ext_data isa_ext_arr[] = { 184 __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), 185 __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), 186 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), 187 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), 188 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), 189 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), 190 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), 191 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), 192 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), 193 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), 194 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), 195 __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), 196 }; 197 198 static void print_isa_ext(struct seq_file *f) 199 { 200 struct riscv_isa_ext_data *edata; 201 int i = 0, arr_sz; 202 203 arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; 204 205 /* No extension support available */ 206 if (arr_sz <= 0) 207 return; 208 209 for (i = 0; i <= arr_sz; i++) { 210 edata = &isa_ext_arr[i]; 211 if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) 212 continue; 213 seq_printf(f, "_%s", edata->uprop); 214 } 215 } 216 217 /* 218 * These are the only valid base (single letter) ISA extensions as per the spec. 219 * It also specifies the canonical order in which it appears in the spec. 220 * Some of the extension may just be a place holder for now (B, K, P, J). 221 * This should be updated once corresponding extensions are ratified. 222 */ 223 static const char base_riscv_exts[13] = "imafdqcbkjpvh"; 224 225 static void print_isa(struct seq_file *f, const char *isa) 226 { 227 int i; 228 229 seq_puts(f, "isa\t\t: "); 230 /* Print the rv[64/32] part */ 231 seq_write(f, isa, 4); 232 for (i = 0; i < sizeof(base_riscv_exts); i++) { 233 if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) 234 /* Print only enabled the base ISA extensions */ 235 seq_write(f, &base_riscv_exts[i], 1); 236 } 237 print_isa_ext(f); 238 seq_puts(f, "\n"); 239 } 240 241 static void print_mmu(struct seq_file *f) 242 { 243 char sv_type[16]; 244 245 #ifdef CONFIG_MMU 246 #if defined(CONFIG_32BIT) 247 strncpy(sv_type, "sv32", 5); 248 #elif defined(CONFIG_64BIT) 249 if (pgtable_l5_enabled) 250 strncpy(sv_type, "sv57", 5); 251 else if (pgtable_l4_enabled) 252 strncpy(sv_type, "sv48", 5); 253 else 254 strncpy(sv_type, "sv39", 5); 255 #endif 256 #else 257 strncpy(sv_type, "none", 5); 258 #endif /* CONFIG_MMU */ 259 seq_printf(f, "mmu\t\t: %s\n", sv_type); 260 } 261 262 static void *c_start(struct seq_file *m, loff_t *pos) 263 { 264 if (*pos == nr_cpu_ids) 265 return NULL; 266 267 *pos = cpumask_next(*pos - 1, cpu_online_mask); 268 if ((*pos) < nr_cpu_ids) 269 return (void *)(uintptr_t)(1 + *pos); 270 return NULL; 271 } 272 273 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 274 { 275 (*pos)++; 276 return c_start(m, pos); 277 } 278 279 static void c_stop(struct seq_file *m, void *v) 280 { 281 } 282 283 static int c_show(struct seq_file *m, void *v) 284 { 285 unsigned long cpu_id = (unsigned long)v - 1; 286 struct device_node *node = of_get_cpu_node(cpu_id, NULL); 287 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); 288 const char *compat, *isa; 289 290 seq_printf(m, "processor\t: %lu\n", cpu_id); 291 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); 292 if (!of_property_read_string(node, "riscv,isa", &isa)) 293 print_isa(m, isa); 294 print_mmu(m); 295 if (!of_property_read_string(node, "compatible", &compat) 296 && strcmp(compat, "riscv")) 297 seq_printf(m, "uarch\t\t: %s\n", compat); 298 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); 299 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); 300 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); 301 seq_puts(m, "\n"); 302 of_node_put(node); 303 304 return 0; 305 } 306 307 const struct seq_operations cpuinfo_op = { 308 .start = c_start, 309 .next = c_next, 310 .stop = c_stop, 311 .show = c_show 312 }; 313 314 #endif /* CONFIG_PROC_FS */ 315