1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 SiFive 4 */ 5 6 #include <linux/cpu.h> 7 #include <linux/of.h> 8 #include <asm/cacheinfo.h> 9 10 static struct riscv_cacheinfo_ops *rv_cache_ops; 11 12 void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) 13 { 14 rv_cache_ops = ops; 15 } 16 EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); 17 18 const struct attribute_group * 19 cache_get_priv_group(struct cacheinfo *this_leaf) 20 { 21 if (rv_cache_ops && rv_cache_ops->get_priv_group) 22 return rv_cache_ops->get_priv_group(this_leaf); 23 return NULL; 24 } 25 26 static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) 27 { 28 /* 29 * Using raw_smp_processor_id() elides a preemptability check, but this 30 * is really indicative of a larger problem: the cacheinfo UABI assumes 31 * that cores have a homonogenous view of the cache hierarchy. That 32 * happens to be the case for the current set of RISC-V systems, but 33 * likely won't be true in general. Since there's no way to provide 34 * correct information for these systems via the current UABI we're 35 * just eliding the check for now. 36 */ 37 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id()); 38 struct cacheinfo *this_leaf; 39 int index; 40 41 for (index = 0; index < this_cpu_ci->num_leaves; index++) { 42 this_leaf = this_cpu_ci->info_list + index; 43 if (this_leaf->level == level && this_leaf->type == type) 44 return this_leaf; 45 } 46 47 return NULL; 48 } 49 50 uintptr_t get_cache_size(u32 level, enum cache_type type) 51 { 52 struct cacheinfo *this_leaf = get_cacheinfo(level, type); 53 54 return this_leaf ? this_leaf->size : 0; 55 } 56 57 uintptr_t get_cache_geometry(u32 level, enum cache_type type) 58 { 59 struct cacheinfo *this_leaf = get_cacheinfo(level, type); 60 61 return this_leaf ? (this_leaf->ways_of_associativity << 16 | 62 this_leaf->coherency_line_size) : 63 0; 64 } 65 66 static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, 67 unsigned int level, unsigned int size, 68 unsigned int sets, unsigned int line_size) 69 { 70 this_leaf->level = level; 71 this_leaf->type = type; 72 this_leaf->size = size; 73 this_leaf->number_of_sets = sets; 74 this_leaf->coherency_line_size = line_size; 75 76 /* 77 * If the cache is fully associative, there is no need to 78 * check the other properties. 79 */ 80 if (sets == 1) 81 return; 82 83 /* 84 * Set the ways number for n-ways associative, make sure 85 * all properties are big than zero. 86 */ 87 if (sets > 0 && size > 0 && line_size > 0) 88 this_leaf->ways_of_associativity = (size / sets) / line_size; 89 } 90 91 static void fill_cacheinfo(struct cacheinfo **this_leaf, 92 struct device_node *node, unsigned int level) 93 { 94 unsigned int size, sets, line_size; 95 96 if (!of_property_read_u32(node, "cache-size", &size) && 97 !of_property_read_u32(node, "cache-block-size", &line_size) && 98 !of_property_read_u32(node, "cache-sets", &sets)) { 99 ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); 100 } 101 102 if (!of_property_read_u32(node, "i-cache-size", &size) && 103 !of_property_read_u32(node, "i-cache-sets", &sets) && 104 !of_property_read_u32(node, "i-cache-block-size", &line_size)) { 105 ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); 106 } 107 108 if (!of_property_read_u32(node, "d-cache-size", &size) && 109 !of_property_read_u32(node, "d-cache-sets", &sets) && 110 !of_property_read_u32(node, "d-cache-block-size", &line_size)) { 111 ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); 112 } 113 } 114 115 int populate_cache_leaves(unsigned int cpu) 116 { 117 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); 118 struct cacheinfo *this_leaf = this_cpu_ci->info_list; 119 struct device_node *np = of_cpu_device_node_get(cpu); 120 struct device_node *prev = NULL; 121 int levels = 1, level = 1; 122 123 /* Level 1 caches in cpu node */ 124 fill_cacheinfo(&this_leaf, np, level); 125 126 /* Next level caches in cache nodes */ 127 prev = np; 128 while ((np = of_find_next_cache_node(np))) { 129 of_node_put(prev); 130 prev = np; 131 132 if (!of_device_is_compatible(np, "cache")) 133 break; 134 if (of_property_read_u32(np, "cache-level", &level)) 135 break; 136 if (level <= levels) 137 break; 138 139 fill_cacheinfo(&this_leaf, np, level); 140 141 levels = level; 142 } 143 of_node_put(np); 144 145 return 0; 146 } 147