1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #ifndef __LINUX_KVM_RISCV_H 10 #define __LINUX_KVM_RISCV_H 11 12 #ifndef __ASSEMBLY__ 13 14 #include <linux/types.h> 15 #include <asm/bitsperlong.h> 16 #include <asm/ptrace.h> 17 18 #define __KVM_HAVE_READONLY_MEM 19 20 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 21 22 #define KVM_INTERRUPT_SET -1U 23 #define KVM_INTERRUPT_UNSET -2U 24 25 /* for KVM_GET_REGS and KVM_SET_REGS */ 26 struct kvm_regs { 27 }; 28 29 /* for KVM_GET_FPU and KVM_SET_FPU */ 30 struct kvm_fpu { 31 }; 32 33 /* KVM Debug exit structure */ 34 struct kvm_debug_exit_arch { 35 }; 36 37 /* for KVM_SET_GUEST_DEBUG */ 38 struct kvm_guest_debug_arch { 39 }; 40 41 /* definition of registers in kvm_run */ 42 struct kvm_sync_regs { 43 }; 44 45 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 46 struct kvm_sregs { 47 }; 48 49 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 50 struct kvm_riscv_config { 51 unsigned long isa; 52 unsigned long zicbom_block_size; 53 unsigned long mvendorid; 54 unsigned long marchid; 55 unsigned long mimpid; 56 unsigned long zicboz_block_size; 57 }; 58 59 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 60 struct kvm_riscv_core { 61 struct user_regs_struct regs; 62 unsigned long mode; 63 }; 64 65 /* Possible privilege modes for kvm_riscv_core */ 66 #define KVM_RISCV_MODE_S 1 67 #define KVM_RISCV_MODE_U 0 68 69 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 70 struct kvm_riscv_csr { 71 unsigned long sstatus; 72 unsigned long sie; 73 unsigned long stvec; 74 unsigned long sscratch; 75 unsigned long sepc; 76 unsigned long scause; 77 unsigned long stval; 78 unsigned long sip; 79 unsigned long satp; 80 unsigned long scounteren; 81 }; 82 83 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 84 struct kvm_riscv_aia_csr { 85 unsigned long siselect; 86 unsigned long iprio1; 87 unsigned long iprio2; 88 unsigned long sieh; 89 unsigned long siph; 90 unsigned long iprio1h; 91 unsigned long iprio2h; 92 }; 93 94 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 95 struct kvm_riscv_timer { 96 __u64 frequency; 97 __u64 time; 98 __u64 compare; 99 __u64 state; 100 }; 101 102 /* 103 * ISA extension IDs specific to KVM. This is not the same as the host ISA 104 * extension IDs as that is internal to the host and should not be exposed 105 * to the guest. This should always be contiguous to keep the mapping simple 106 * in KVM implementation. 107 */ 108 enum KVM_RISCV_ISA_EXT_ID { 109 KVM_RISCV_ISA_EXT_A = 0, 110 KVM_RISCV_ISA_EXT_C, 111 KVM_RISCV_ISA_EXT_D, 112 KVM_RISCV_ISA_EXT_F, 113 KVM_RISCV_ISA_EXT_H, 114 KVM_RISCV_ISA_EXT_I, 115 KVM_RISCV_ISA_EXT_M, 116 KVM_RISCV_ISA_EXT_SVPBMT, 117 KVM_RISCV_ISA_EXT_SSTC, 118 KVM_RISCV_ISA_EXT_SVINVAL, 119 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 120 KVM_RISCV_ISA_EXT_ZICBOM, 121 KVM_RISCV_ISA_EXT_ZICBOZ, 122 KVM_RISCV_ISA_EXT_ZBB, 123 KVM_RISCV_ISA_EXT_SSAIA, 124 KVM_RISCV_ISA_EXT_V, 125 KVM_RISCV_ISA_EXT_MAX, 126 }; 127 128 /* 129 * SBI extension IDs specific to KVM. This is not the same as the SBI 130 * extension IDs defined by the RISC-V SBI specification. 131 */ 132 enum KVM_RISCV_SBI_EXT_ID { 133 KVM_RISCV_SBI_EXT_V01 = 0, 134 KVM_RISCV_SBI_EXT_TIME, 135 KVM_RISCV_SBI_EXT_IPI, 136 KVM_RISCV_SBI_EXT_RFENCE, 137 KVM_RISCV_SBI_EXT_SRST, 138 KVM_RISCV_SBI_EXT_HSM, 139 KVM_RISCV_SBI_EXT_PMU, 140 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 141 KVM_RISCV_SBI_EXT_VENDOR, 142 KVM_RISCV_SBI_EXT_MAX, 143 }; 144 145 /* Possible states for kvm_riscv_timer */ 146 #define KVM_RISCV_TIMER_STATE_OFF 0 147 #define KVM_RISCV_TIMER_STATE_ON 1 148 149 #define KVM_REG_SIZE(id) \ 150 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 151 152 /* If you need to interpret the index values, here is the key: */ 153 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 154 #define KVM_REG_RISCV_TYPE_SHIFT 24 155 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 156 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 157 158 /* Config registers are mapped as type 1 */ 159 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 160 #define KVM_REG_RISCV_CONFIG_REG(name) \ 161 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 162 163 /* Core registers are mapped as type 2 */ 164 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 165 #define KVM_REG_RISCV_CORE_REG(name) \ 166 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 167 168 /* Control and status registers are mapped as type 3 */ 169 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 170 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 171 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 172 #define KVM_REG_RISCV_CSR_REG(name) \ 173 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 174 #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 175 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 176 177 /* Timer registers are mapped as type 4 */ 178 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 179 #define KVM_REG_RISCV_TIMER_REG(name) \ 180 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 181 182 /* F extension registers are mapped as type 5 */ 183 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 184 #define KVM_REG_RISCV_FP_F_REG(name) \ 185 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 186 187 /* D extension registers are mapped as type 6 */ 188 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 189 #define KVM_REG_RISCV_FP_D_REG(name) \ 190 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 191 192 /* ISA Extension registers are mapped as type 7 */ 193 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 194 195 /* SBI extension registers are mapped as type 8 */ 196 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 197 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 198 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 199 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 200 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 201 ((__ext_id) / __BITS_PER_LONG) 202 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 203 (1UL << ((__ext_id) % __BITS_PER_LONG)) 204 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 205 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 206 207 /* V extension registers are mapped as type 9 */ 208 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 209 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 210 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 211 #define KVM_REG_RISCV_VECTOR_REG(n) \ 212 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 213 214 #endif 215 216 #endif /* __LINUX_KVM_RISCV_H */ 217