1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #ifndef __LINUX_KVM_RISCV_H 10 #define __LINUX_KVM_RISCV_H 11 12 #ifndef __ASSEMBLER__ 13 14 #include <linux/types.h> 15 #include <asm/bitsperlong.h> 16 #include <asm/ptrace.h> 17 18 #define __KVM_HAVE_IRQ_LINE 19 20 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 21 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 22 23 #define KVM_INTERRUPT_SET -1U 24 #define KVM_INTERRUPT_UNSET -2U 25 26 /* for KVM_GET_REGS and KVM_SET_REGS */ 27 struct kvm_regs { 28 }; 29 30 /* for KVM_GET_FPU and KVM_SET_FPU */ 31 struct kvm_fpu { 32 }; 33 34 /* KVM Debug exit structure */ 35 struct kvm_debug_exit_arch { 36 }; 37 38 /* for KVM_SET_GUEST_DEBUG */ 39 struct kvm_guest_debug_arch { 40 }; 41 42 /* definition of registers in kvm_run */ 43 struct kvm_sync_regs { 44 }; 45 46 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 47 struct kvm_sregs { 48 }; 49 50 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 51 struct kvm_riscv_config { 52 unsigned long isa; 53 unsigned long zicbom_block_size; 54 unsigned long mvendorid; 55 unsigned long marchid; 56 unsigned long mimpid; 57 unsigned long zicboz_block_size; 58 unsigned long satp_mode; 59 unsigned long zicbop_block_size; 60 }; 61 62 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 63 struct kvm_riscv_core { 64 struct user_regs_struct regs; 65 unsigned long mode; 66 }; 67 68 /* Possible privilege modes for kvm_riscv_core */ 69 #define KVM_RISCV_MODE_S 1 70 #define KVM_RISCV_MODE_U 0 71 72 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 73 struct kvm_riscv_csr { 74 unsigned long sstatus; 75 unsigned long sie; 76 unsigned long stvec; 77 unsigned long sscratch; 78 unsigned long sepc; 79 unsigned long scause; 80 unsigned long stval; 81 unsigned long sip; 82 unsigned long satp; 83 unsigned long scounteren; 84 unsigned long senvcfg; 85 }; 86 87 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 88 struct kvm_riscv_aia_csr { 89 unsigned long siselect; 90 unsigned long iprio1; 91 unsigned long iprio2; 92 unsigned long sieh; 93 unsigned long siph; 94 unsigned long iprio1h; 95 unsigned long iprio2h; 96 }; 97 98 /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 99 struct kvm_riscv_smstateen_csr { 100 unsigned long sstateen0; 101 }; 102 103 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 104 struct kvm_riscv_timer { 105 __u64 frequency; 106 __u64 time; 107 __u64 compare; 108 __u64 state; 109 }; 110 111 /* 112 * ISA extension IDs specific to KVM. This is not the same as the host ISA 113 * extension IDs as that is internal to the host and should not be exposed 114 * to the guest. This should always be contiguous to keep the mapping simple 115 * in KVM implementation. 116 */ 117 enum KVM_RISCV_ISA_EXT_ID { 118 KVM_RISCV_ISA_EXT_A = 0, 119 KVM_RISCV_ISA_EXT_C, 120 KVM_RISCV_ISA_EXT_D, 121 KVM_RISCV_ISA_EXT_F, 122 KVM_RISCV_ISA_EXT_H, 123 KVM_RISCV_ISA_EXT_I, 124 KVM_RISCV_ISA_EXT_M, 125 KVM_RISCV_ISA_EXT_SVPBMT, 126 KVM_RISCV_ISA_EXT_SSTC, 127 KVM_RISCV_ISA_EXT_SVINVAL, 128 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 129 KVM_RISCV_ISA_EXT_ZICBOM, 130 KVM_RISCV_ISA_EXT_ZICBOZ, 131 KVM_RISCV_ISA_EXT_ZBB, 132 KVM_RISCV_ISA_EXT_SSAIA, 133 KVM_RISCV_ISA_EXT_V, 134 KVM_RISCV_ISA_EXT_SVNAPOT, 135 KVM_RISCV_ISA_EXT_ZBA, 136 KVM_RISCV_ISA_EXT_ZBS, 137 KVM_RISCV_ISA_EXT_ZICNTR, 138 KVM_RISCV_ISA_EXT_ZICSR, 139 KVM_RISCV_ISA_EXT_ZIFENCEI, 140 KVM_RISCV_ISA_EXT_ZIHPM, 141 KVM_RISCV_ISA_EXT_SMSTATEEN, 142 KVM_RISCV_ISA_EXT_ZICOND, 143 KVM_RISCV_ISA_EXT_ZBC, 144 KVM_RISCV_ISA_EXT_ZBKB, 145 KVM_RISCV_ISA_EXT_ZBKC, 146 KVM_RISCV_ISA_EXT_ZBKX, 147 KVM_RISCV_ISA_EXT_ZKND, 148 KVM_RISCV_ISA_EXT_ZKNE, 149 KVM_RISCV_ISA_EXT_ZKNH, 150 KVM_RISCV_ISA_EXT_ZKR, 151 KVM_RISCV_ISA_EXT_ZKSED, 152 KVM_RISCV_ISA_EXT_ZKSH, 153 KVM_RISCV_ISA_EXT_ZKT, 154 KVM_RISCV_ISA_EXT_ZVBB, 155 KVM_RISCV_ISA_EXT_ZVBC, 156 KVM_RISCV_ISA_EXT_ZVKB, 157 KVM_RISCV_ISA_EXT_ZVKG, 158 KVM_RISCV_ISA_EXT_ZVKNED, 159 KVM_RISCV_ISA_EXT_ZVKNHA, 160 KVM_RISCV_ISA_EXT_ZVKNHB, 161 KVM_RISCV_ISA_EXT_ZVKSED, 162 KVM_RISCV_ISA_EXT_ZVKSH, 163 KVM_RISCV_ISA_EXT_ZVKT, 164 KVM_RISCV_ISA_EXT_ZFH, 165 KVM_RISCV_ISA_EXT_ZFHMIN, 166 KVM_RISCV_ISA_EXT_ZIHINTNTL, 167 KVM_RISCV_ISA_EXT_ZVFH, 168 KVM_RISCV_ISA_EXT_ZVFHMIN, 169 KVM_RISCV_ISA_EXT_ZFA, 170 KVM_RISCV_ISA_EXT_ZTSO, 171 KVM_RISCV_ISA_EXT_ZACAS, 172 KVM_RISCV_ISA_EXT_SSCOFPMF, 173 KVM_RISCV_ISA_EXT_ZIMOP, 174 KVM_RISCV_ISA_EXT_ZCA, 175 KVM_RISCV_ISA_EXT_ZCB, 176 KVM_RISCV_ISA_EXT_ZCD, 177 KVM_RISCV_ISA_EXT_ZCF, 178 KVM_RISCV_ISA_EXT_ZCMOP, 179 KVM_RISCV_ISA_EXT_ZAWRS, 180 KVM_RISCV_ISA_EXT_SMNPM, 181 KVM_RISCV_ISA_EXT_SSNPM, 182 KVM_RISCV_ISA_EXT_SVADE, 183 KVM_RISCV_ISA_EXT_SVADU, 184 KVM_RISCV_ISA_EXT_SVVPTC, 185 KVM_RISCV_ISA_EXT_ZABHA, 186 KVM_RISCV_ISA_EXT_ZICCRSE, 187 KVM_RISCV_ISA_EXT_ZAAMO, 188 KVM_RISCV_ISA_EXT_ZALRSC, 189 KVM_RISCV_ISA_EXT_ZICBOP, 190 KVM_RISCV_ISA_EXT_ZFBFMIN, 191 KVM_RISCV_ISA_EXT_ZVFBFMIN, 192 KVM_RISCV_ISA_EXT_ZVFBFWMA, 193 KVM_RISCV_ISA_EXT_MAX, 194 }; 195 196 /* 197 * SBI extension IDs specific to KVM. This is not the same as the SBI 198 * extension IDs defined by the RISC-V SBI specification. 199 */ 200 enum KVM_RISCV_SBI_EXT_ID { 201 KVM_RISCV_SBI_EXT_V01 = 0, 202 KVM_RISCV_SBI_EXT_TIME, 203 KVM_RISCV_SBI_EXT_IPI, 204 KVM_RISCV_SBI_EXT_RFENCE, 205 KVM_RISCV_SBI_EXT_SRST, 206 KVM_RISCV_SBI_EXT_HSM, 207 KVM_RISCV_SBI_EXT_PMU, 208 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 209 KVM_RISCV_SBI_EXT_VENDOR, 210 KVM_RISCV_SBI_EXT_DBCN, 211 KVM_RISCV_SBI_EXT_STA, 212 KVM_RISCV_SBI_EXT_SUSP, 213 KVM_RISCV_SBI_EXT_FWFT, 214 KVM_RISCV_SBI_EXT_MAX, 215 }; 216 217 /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 218 struct kvm_riscv_sbi_sta { 219 unsigned long shmem_lo; 220 unsigned long shmem_hi; 221 }; 222 223 struct kvm_riscv_sbi_fwft_feature { 224 unsigned long enable; 225 unsigned long flags; 226 unsigned long value; 227 }; 228 229 /* SBI FWFT extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 230 struct kvm_riscv_sbi_fwft { 231 struct kvm_riscv_sbi_fwft_feature misaligned_deleg; 232 struct kvm_riscv_sbi_fwft_feature pointer_masking; 233 }; 234 235 /* Possible states for kvm_riscv_timer */ 236 #define KVM_RISCV_TIMER_STATE_OFF 0 237 #define KVM_RISCV_TIMER_STATE_ON 1 238 239 /* If you need to interpret the index values, here is the key: */ 240 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 241 #define KVM_REG_RISCV_TYPE_SHIFT 24 242 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 243 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 244 245 /* Config registers are mapped as type 1 */ 246 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 247 #define KVM_REG_RISCV_CONFIG_REG(name) \ 248 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 249 250 /* Core registers are mapped as type 2 */ 251 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 252 #define KVM_REG_RISCV_CORE_REG(name) \ 253 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 254 255 /* Control and status registers are mapped as type 3 */ 256 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 257 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 258 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 259 #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 260 #define KVM_REG_RISCV_CSR_REG(name) \ 261 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 262 #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 263 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 264 #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ 265 (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) 266 267 /* Timer registers are mapped as type 4 */ 268 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 269 #define KVM_REG_RISCV_TIMER_REG(name) \ 270 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 271 272 /* F extension registers are mapped as type 5 */ 273 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 274 #define KVM_REG_RISCV_FP_F_REG(name) \ 275 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 276 277 /* D extension registers are mapped as type 6 */ 278 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 279 #define KVM_REG_RISCV_FP_D_REG(name) \ 280 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 281 282 /* ISA Extension registers are mapped as type 7 */ 283 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 284 #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 285 #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 286 #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 287 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \ 288 ((__ext_id) / __BITS_PER_LONG) 289 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \ 290 (1UL << ((__ext_id) % __BITS_PER_LONG)) 291 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST \ 292 KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) 293 294 /* SBI extension registers are mapped as type 8 */ 295 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 296 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 297 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 298 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 299 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 300 ((__ext_id) / __BITS_PER_LONG) 301 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 302 (1UL << ((__ext_id) % __BITS_PER_LONG)) 303 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 304 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 305 306 /* V extension registers are mapped as type 9 */ 307 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 308 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 309 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 310 #define KVM_REG_RISCV_VECTOR_REG(n) \ 311 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 312 313 /* Registers for specific SBI extensions are mapped as type 10 */ 314 #define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) 315 #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 316 #define KVM_REG_RISCV_SBI_STA_REG(name) \ 317 (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) 318 #define KVM_REG_RISCV_SBI_FWFT (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 319 #define KVM_REG_RISCV_SBI_FWFT_REG(name) \ 320 (offsetof(struct kvm_riscv_sbi_fwft, name) / sizeof(unsigned long)) 321 322 /* Device Control API: RISC-V AIA */ 323 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 324 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 325 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 326 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 327 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 328 329 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 330 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 331 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 332 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 333 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 334 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 335 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 336 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 337 338 /* 339 * Modes of RISC-V AIA device: 340 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 341 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 342 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 343 * available otherwise fallback to trap-n-emulation 344 */ 345 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 346 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 347 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 348 349 #define KVM_DEV_RISCV_AIA_IDS_MIN 63 350 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 351 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 352 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 353 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 354 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 355 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 356 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 357 358 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 359 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 360 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 361 #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 362 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 363 364 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 365 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 366 367 /* 368 * The device attribute type contains the memory mapped offset of the 369 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 370 */ 371 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 372 373 /* 374 * The lower 12-bits of the device attribute type contains the iselect 375 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 376 * bits contains the VCPU id. 377 */ 378 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 379 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 380 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 381 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 382 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 383 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 384 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 385 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 386 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 387 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 388 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 389 390 /* One single KVM irqchip, ie. the AIA */ 391 #define KVM_NR_IRQCHIPS 1 392 393 #endif 394 395 #endif /* __LINUX_KVM_RISCV_H */ 396